Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable
This commit is contained in:
Russell King
Коммит
9326845f45
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@ -9,6 +9,12 @@ config MACH_DOVE_DB
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Say 'Y' here if you want your kernel to support the
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Marvell DB-MV88AP510 Development Board.
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config MACH_CM_A510
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bool "CompuLab CM-A510 Board"
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help
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Say 'Y' here if you want your kernel to support the
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CompuLab CM-A510 Board.
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endmenu
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endif
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@ -1,3 +1,4 @@
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obj-y += common.o addr-map.o irq.o pcie.o
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obj-y += common.o addr-map.o irq.o pcie.o mpp.o
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obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
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obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
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@ -0,0 +1,95 @@
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/*
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* arch/arm/mach-dove/cm-a510.c
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*
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* Copyright (C) 2010 CompuLab, Ltd.
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* Konstantin Sinyuk <kostyas@compulab.co.il>
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*
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* Based on Marvell DB-MV88AP510-BP Development Board Setup
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/dove.h>
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#include "common.h"
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static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
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};
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static struct mv_sata_platform_data cm_a510_sata_data = {
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.n_ports = 1,
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};
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/*
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* SPI Devices:
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* SPI0: 1M Flash Winbond w25q32bv
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*/
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static const struct flash_platform_data cm_a510_spi_flash_data = {
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.type = "w25q32bv",
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};
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static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
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{
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.modalias = "m25p80",
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.platform_data = &cm_a510_spi_flash_data,
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.irq = -1,
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.max_speed_hz = 20000000,
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.bus_num = 0,
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.chip_select = 0,
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},
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};
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static int __init cm_a510_pci_init(void)
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{
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if (machine_is_cm_a510())
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dove_pcie_init(1, 1);
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return 0;
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}
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subsys_initcall(cm_a510_pci_init);
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/* Board Init */
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static void __init cm_a510_init(void)
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{
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/*
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* Basic Dove setup. Needs to be called early.
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*/
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dove_init();
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dove_ge00_init(&cm_a510_ge00_data);
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dove_ehci0_init();
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dove_ehci1_init();
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dove_sata_init(&cm_a510_sata_data);
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dove_sdio0_init();
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dove_sdio1_init();
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dove_spi0_init();
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dove_spi1_init();
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dove_uart0_init();
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dove_uart1_init();
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dove_i2c_init();
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spi_register_board_info(cm_a510_spi_flash_info,
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ARRAY_SIZE(cm_a510_spi_flash_info));
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}
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MACHINE_START(CM_A510, "Compulab CM-A510 Board")
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.boot_params = 0x00000100,
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.init_machine = cm_a510_init,
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.map_io = dove_map_io,
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.init_irq = dove_init_irq,
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.timer = &dove_timer,
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MACHINE_END
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@ -131,14 +131,21 @@
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#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
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#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
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#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
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#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
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#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
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#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
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#define DOVE_NAND_GPIO_EN (1 << 0)
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#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
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#define DOVE_SPI_GPIO_SEL (1 << 5)
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#define DOVE_UART1_GPIO_SEL (1 << 4)
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#define DOVE_AU1_GPIO_SEL (1 << 3)
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#define DOVE_CAM_GPIO_SEL (1 << 2)
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#define DOVE_SD1_GPIO_SEL (1 << 1)
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#define DOVE_SD0_GPIO_SEL (1 << 0)
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/* Power Management */
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#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
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#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
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/* Real Time Clock */
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#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
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@ -14,12 +14,14 @@
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#include <plat/gpio.h>
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#include <asm-generic/gpio.h> /* cansleep wrappers */
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#define GPIO_MAX 64
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#define GPIO_MAX 72
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#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
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#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
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#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
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#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
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((pin < 64) ? GPIO_BASE_HI : \
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DOVE_GPIO2_VIRT_BASE))
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#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
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#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
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@ -0,0 +1,212 @@
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/*
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* arch/arm/mach-dove/mpp.c
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*
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* MPP functions for Marvell Dove SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <mach/dove.h>
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#include "mpp.h"
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#define MPP_NR_REGS 4
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#define MPP_CTRL(i) ((i) == 3 ? \
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DOVE_MPP_CTRL4_VIRT_BASE : \
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DOVE_MPP_VIRT_BASE + (i) * 4)
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#define PMU_SIG_REGS 2
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#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
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struct dove_mpp_grp {
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int start;
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int end;
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};
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static struct dove_mpp_grp dove_mpp_grp[] = {
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[MPP_24_39] = {
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.start = 24,
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.end = 39,
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},
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[MPP_40_45] = {
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.start = 40,
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.end = 45,
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},
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[MPP_46_51] = {
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.start = 40,
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.end = 45,
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},
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[MPP_58_61] = {
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.start = 58,
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.end = 61,
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},
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[MPP_62_63] = {
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.start = 62,
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.end = 63,
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},
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};
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static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
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{
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int i;
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for (i = start; i <= end; i++)
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orion_gpio_set_valid(i, gpio_mode);
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}
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static void dove_mpp_dump_regs(void)
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{
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#ifdef DEBUG
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int i;
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pr_debug("MPP_CTRL regs:");
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for (i = 0; i < MPP_NR_REGS; i++)
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printk(" %08x", readl(MPP_CTRL(i)));
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printk("\n");
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pr_debug("PMU_SIG_CTRL regs:");
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for (i = 0; i < PMU_SIG_REGS; i++)
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printk(" %08x", readl(PMU_SIG_CTRL(i)));
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printk("\n");
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pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
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pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
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#endif
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}
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static void dove_mpp_cfg_nfc(int sel)
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{
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u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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mpp_gen_cfg &= ~0x1;
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mpp_gen_cfg |= sel;
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writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
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dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
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}
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static void dove_mpp_cfg_au1(int sel)
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{
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u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
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u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
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mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
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ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
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mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
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global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
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if (!sel || sel == 0x2)
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dove_mpp_gpio_mode(52, 57, 0);
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else
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dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
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if (sel & 0x1) {
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global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
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dove_mpp_gpio_mode(56, 57, 0);
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}
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if (sel & 0x2) {
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mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
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dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
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}
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if (sel & 0x4) {
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ssp_ctrl1 |= DOVE_SSP_ON_AU1;
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dove_mpp_gpio_mode(52, 55, 0);
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}
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if (sel & 0x8)
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mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
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writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
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writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
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writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
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writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
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}
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static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
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{
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int start = dove_mpp_grp[num].start;
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int end = dove_mpp_grp[num].end;
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int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
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*mpp_ctrl &= ~(0x1 << num);
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*mpp_ctrl |= sel << num;
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dove_mpp_gpio_mode(start, end, gpio_mode);
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}
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void __init dove_mpp_conf(unsigned int *mpp_list)
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{
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u32 mpp_ctrl[MPP_NR_REGS];
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u32 pmu_mpp_ctrl = 0;
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u32 pmu_sig_ctrl[PMU_SIG_REGS];
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int i;
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/* Initialize gpiolib. */
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orion_gpio_init();
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for (i = 0; i < MPP_NR_REGS; i++)
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mpp_ctrl[i] = readl(MPP_CTRL(i));
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for (i = 0; i < PMU_SIG_REGS; i++)
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pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
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pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
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dove_mpp_dump_regs();
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for ( ; *mpp_list != MPP_END; mpp_list++) {
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unsigned int num = MPP_NUM(*mpp_list);
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unsigned int sel = MPP_SEL(*mpp_list);
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int shift, gpio_mode;
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if (num > MPP_MAX) {
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pr_err("dove: invalid MPP number (%u)\n", num);
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continue;
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}
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if (*mpp_list & MPP_NFC_MASK) {
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dove_mpp_cfg_nfc(sel);
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continue;
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}
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if (*mpp_list & MPP_AU1_MASK) {
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dove_mpp_cfg_au1(sel);
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continue;
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}
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if (*mpp_list & MPP_GRP_MASK) {
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dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
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continue;
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}
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||||
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shift = (num & 7) << 2;
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if (*mpp_list & MPP_PMU_MASK) {
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pmu_mpp_ctrl |= (0x1 << num);
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pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
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pmu_sig_ctrl[num / 8] |= 0xf << shift;
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gpio_mode = 0;
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} else {
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mpp_ctrl[num / 8] &= ~(0xf << shift);
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mpp_ctrl[num / 8] |= sel << shift;
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gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
|
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}
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orion_gpio_set_valid(num, gpio_mode);
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||||
}
|
||||
|
||||
for (i = 0; i < MPP_NR_REGS; i++)
|
||||
writel(mpp_ctrl[i], MPP_CTRL(i));
|
||||
|
||||
for (i = 0; i < PMU_SIG_REGS; i++)
|
||||
writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
|
||||
|
||||
writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
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||||
|
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dove_mpp_dump_regs();
|
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}
|
||||
|
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@ -0,0 +1,220 @@
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#ifndef __ARCH_DOVE_MPP_CODED_H
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||||
#define __ARCH_DOVE_MPP_CODED_H
|
||||
|
||||
#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \
|
||||
/* MPP/group number */ ((_num) & 0xff) | \
|
||||
/* MPP select value */ (((_mode) & 0xf) << 8) | \
|
||||
/* MPP PMU */ ((!!(_pmu)) << 12) | \
|
||||
/* group flag */ ((!!(_grp)) << 13) | \
|
||||
/* AU1 flag */ ((!!(_au1)) << 14) | \
|
||||
/* NFCE flag */ ((!!(_nfc)) << 15))
|
||||
|
||||
#define MPP_MAX 71
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||||
|
||||
#define MPP_NUM(x) ((x) & 0xff)
|
||||
#define MPP_SEL(x) (((x) >> 8) & 0xf)
|
||||
|
||||
#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)
|
||||
#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)
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#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)
|
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#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)
|
||||
|
||||
#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)
|
||||
|
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#define MPP_PMU_DRIVE_0 0x1
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#define MPP_PMU_DRIVE_1 0x2
|
||||
#define MPP_PMU_SDI 0x3
|
||||
#define MPP_PMU_CPU_PWRDWN 0x4
|
||||
#define MPP_PMU_STBY_PWRDWN 0x5
|
||||
#define MPP_PMU_CORE_PWR_GOOD 0x8
|
||||
#define MPP_PMU_BAT_FAULT 0xa
|
||||
#define MPP_PMU_EXT0_WU 0xb
|
||||
#define MPP_PMU_EXT1_WU 0xc
|
||||
#define MPP_PMU_EXT2_WU 0xd
|
||||
#define MPP_PMU_BLINK 0xe
|
||||
#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
|
||||
|
||||
#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)
|
||||
#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)
|
||||
#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)
|
||||
#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)
|
||||
|
||||
#define MPP0_GPIO0 MPP_PIN(0, 0x0)
|
||||
#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)
|
||||
#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)
|
||||
#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)
|
||||
|
||||
#define MPP1_GPIO1 MPP_PIN(1, 0x0)
|
||||
#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)
|
||||
#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)
|
||||
#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)
|
||||
|
||||
#define MPP2_GPIO2 MPP_PIN(2, 0x0)
|
||||
#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)
|
||||
#define MPP2_UA2_TXD MPP_PIN(2, 0x2)
|
||||
#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)
|
||||
#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)
|
||||
|
||||
#define MPP3_GPIO3 MPP_PIN(3, 0x0)
|
||||
#define MPP3_SATA_ACT MPP_PIN(3, 0x1)
|
||||
#define MPP3_UA2_RXD MPP_PIN(3, 0x2)
|
||||
#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)
|
||||
#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)
|
||||
#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)
|
||||
|
||||
#define MPP4_GPIO4 MPP_PIN(4, 0x0)
|
||||
#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)
|
||||
#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)
|
||||
#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)
|
||||
|
||||
#define MPP5_GPIO5 MPP_PIN(5, 0x0)
|
||||
#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)
|
||||
#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)
|
||||
#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)
|
||||
|
||||
#define MPP6_GPIO6 MPP_PIN(6, 0x0)
|
||||
#define MPP6_UA3_TXD MPP_PIN(6, 0x2)
|
||||
#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)
|
||||
#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)
|
||||
|
||||
#define MPP7_GPIO7 MPP_PIN(7, 0x0)
|
||||
#define MPP7_UA3_RXD MPP_PIN(7, 0x2)
|
||||
#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)
|
||||
#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)
|
||||
|
||||
#define MPP8_GPIO8 MPP_PIN(8, 0x0)
|
||||
#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)
|
||||
|
||||
#define MPP9_GPIO9 MPP_PIN(9, 0x0)
|
||||
#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)
|
||||
|
||||
#define MPP10_GPIO10 MPP_PIN(10, 0x0)
|
||||
#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)
|
||||
|
||||
#define MPP11_GPIO11 MPP_PIN(11, 0x0)
|
||||
#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)
|
||||
#define MPP11_SATA_ACT MPP_PIN(11, 0x2)
|
||||
#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)
|
||||
#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)
|
||||
#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)
|
||||
|
||||
#define MPP12_GPIO12 MPP_PIN(12, 0x0)
|
||||
#define MPP12_SATA_ACT MPP_PIN(12, 0x1)
|
||||
#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)
|
||||
#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)
|
||||
#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)
|
||||
|
||||
#define MPP13_GPIO13 MPP_PIN(13, 0x0)
|
||||
#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)
|
||||
#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)
|
||||
#define MPP13_SDIO1WP MPP_PIN(13, 0x4)
|
||||
#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)
|
||||
|
||||
#define MPP14_GPIO14 MPP_PIN(14, 0x0)
|
||||
#define MPP14_UA2_TXD MPP_PIN(14, 0x2)
|
||||
#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)
|
||||
#define MPP14_SSP_RXD MPP_PIN(14, 0x5)
|
||||
|
||||
#define MPP15_GPIO15 MPP_PIN(15, 0x0)
|
||||
#define MPP15_UA2_RXD MPP_PIN(15, 0x2)
|
||||
#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)
|
||||
#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)
|
||||
|
||||
#define MPP16_GPIO16 MPP_PIN(16, 0x0)
|
||||
#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)
|
||||
#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)
|
||||
#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)
|
||||
#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)
|
||||
|
||||
#define MPP17_GPIO17 MPP_PIN(17, 0x0)
|
||||
#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)
|
||||
#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)
|
||||
#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)
|
||||
#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)
|
||||
#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)
|
||||
|
||||
#define MPP18_GPIO18 MPP_PIN(18, 0x0)
|
||||
#define MPP18_UA3_TXD MPP_PIN(18, 0x2)
|
||||
#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)
|
||||
#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)
|
||||
#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)
|
||||
|
||||
#define MPP19_GPIO19 MPP_PIN(19, 0x0)
|
||||
#define MPP19_UA3_RXD MPP_PIN(19, 0x2)
|
||||
#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)
|
||||
#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)
|
||||
|
||||
#define MPP20_GPIO20 MPP_PIN(20, 0x0)
|
||||
#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
|
||||
#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
|
||||
#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
|
||||
#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
|
||||
#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
|
||||
|
||||
#define MPP21_GPIO21 MPP_PIN(21, 0x0)
|
||||
#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
|
||||
#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
|
||||
#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
|
||||
#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
|
||||
#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
|
||||
#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
|
||||
|
||||
#define MPP22_GPIO22 MPP_PIN(22, 0x0)
|
||||
#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
|
||||
#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
|
||||
#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
|
||||
#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
|
||||
#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
|
||||
#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
|
||||
|
||||
#define MPP23_GPIO23 MPP_PIN(23, 0x0)
|
||||
#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
|
||||
#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
|
||||
#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
|
||||
#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
|
||||
#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
|
||||
|
||||
/* for MPP groups _num is a group index */
|
||||
enum dove_mpp_grp_idx {
|
||||
MPP_24_39 = 2,
|
||||
MPP_40_45 = 0,
|
||||
MPP_46_51 = 1,
|
||||
MPP_58_61 = 5,
|
||||
MPP_62_63 = 4,
|
||||
};
|
||||
|
||||
#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
|
||||
#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)
|
||||
|
||||
#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
|
||||
#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
|
||||
|
||||
#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
|
||||
#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
|
||||
|
||||
#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
|
||||
#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)
|
||||
|
||||
#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
|
||||
#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
|
||||
|
||||
/* The MPP[64:71] control differs from other groups */
|
||||
#define MPP64_71_GPO MPP_GRP_NFC(0x1)
|
||||
#define MPP64_71_NFC MPP_GRP_NFC(0x0)
|
||||
|
||||
/*
|
||||
* The MPP[52:57] functionality is encoded by 4 bits in different
|
||||
* registers. The _num field in this case encodes those bits in
|
||||
* correspodence with Table 135 of 88AP510 Functional specification
|
||||
*/
|
||||
#define MPP52_57_AU1 MPP_GRP_AU1(0x0)
|
||||
#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)
|
||||
#define MPP52_57_GPIO MPP_GRP_AU1(0xa)
|
||||
#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)
|
||||
#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)
|
||||
#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)
|
||||
#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)
|
||||
|
||||
void dove_mpp_conf(unsigned int *mpp_list);
|
||||
|
||||
#endif /* __ARCH_DOVE_MPP_CODED_H */
|
||||
|
|
@ -45,18 +45,18 @@ config MACH_GURUPLUG
|
|||
Marvell GuruPlug Reference Board.
|
||||
|
||||
config MACH_TS219
|
||||
bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
|
||||
bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the
|
||||
QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
|
||||
devices.
|
||||
QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
|
||||
TS-219P+ Turbo NAS devices.
|
||||
|
||||
config MACH_TS41X
|
||||
bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
|
||||
bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the
|
||||
QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
|
||||
devices.
|
||||
QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
|
||||
NAS devices.
|
||||
|
||||
config MACH_DOCKSTAR
|
||||
bool "Seagate FreeAgent DockStar"
|
||||
|
|
|
|||
|
|
@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
|
|||
MPP11_UART0_RXD,
|
||||
MPP13_UART1_TXD, /* PIC controller */
|
||||
MPP14_UART1_RXD, /* PIC controller */
|
||||
MPP15_GPIO, /* USB Copy button */
|
||||
MPP16_GPIO, /* Reset button */
|
||||
MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */
|
||||
MPP16_GPIO, /* Reset button (on devices with 88F6281) */
|
||||
MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
|
||||
MPP37_GPIO, /* Reset button (on devices with 88F6282) */
|
||||
MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */
|
||||
MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
|
||||
0
|
||||
};
|
||||
|
||||
static void __init qnap_ts219_init(void)
|
||||
{
|
||||
u32 dev, rev;
|
||||
|
||||
/*
|
||||
* Basic setup. Needs to be called early.
|
||||
*/
|
||||
|
|
@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void)
|
|||
qnap_tsx1x_register_flash();
|
||||
kirkwood_i2c_init();
|
||||
i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
|
||||
|
||||
kirkwood_pcie_id(&dev, &rev);
|
||||
if (dev == MV88F6282_DEV_ID) {
|
||||
qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */
|
||||
qnap_ts219_buttons[1].gpio = 37; /* Reset button */
|
||||
qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
|
||||
}
|
||||
|
||||
kirkwood_ge00_init(&qnap_ts219_ge00_data);
|
||||
kirkwood_sata_init(&qnap_ts219_sata_data);
|
||||
kirkwood_ehci_init();
|
||||
|
|
|
|||
|
|
@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
|
|||
|
||||
static void __init qnap_ts41x_init(void)
|
||||
{
|
||||
u32 dev, rev;
|
||||
|
||||
/*
|
||||
* Basic setup. Needs to be called early.
|
||||
*/
|
||||
|
|
@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void)
|
|||
qnap_tsx1x_register_flash();
|
||||
kirkwood_i2c_init();
|
||||
i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
|
||||
|
||||
kirkwood_pcie_id(&dev, &rev);
|
||||
if (dev == MV88F6282_DEV_ID) {
|
||||
qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
|
||||
qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
|
||||
}
|
||||
kirkwood_ge00_init(&qnap_ts41x_ge00_data);
|
||||
kirkwood_ge01_init(&qnap_ts41x_ge01_data);
|
||||
|
||||
kirkwood_sata_init(&qnap_ts41x_sata_data);
|
||||
kirkwood_ehci_init();
|
||||
platform_device_register(&qnap_ts41x_button_device);
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@
|
|||
*/
|
||||
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
|
||||
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
|
||||
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
|
||||
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570)
|
||||
|
||||
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
|
||||
|
|
|
|||
|
|
@ -51,6 +51,13 @@ config MACH_LINKSTATION_PRO
|
|||
Buffalo Linkstation Pro/Live platform. Both v1 and
|
||||
v2 devices are supported.
|
||||
|
||||
config MACH_LINKSTATION_LSCHL
|
||||
bool "Buffalo Linkstation Live v3 (LS-CHL)"
|
||||
select I2C_BOARDINFO
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the
|
||||
Buffalo Linkstation Live v3 (LS-CHL) platform.
|
||||
|
||||
config MACH_LINKSTATION_MINI
|
||||
bool "Buffalo Linkstation Mini"
|
||||
select I2C_BOARDINFO
|
||||
|
|
|
|||
|
|
@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o
|
|||
obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o
|
||||
obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o
|
||||
obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o
|
||||
obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,327 @@
|
|||
/*
|
||||
* arch/arm/mach-orion5x/ls-chl-setup.c
|
||||
*
|
||||
* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/gpio-fan.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/system.h>
|
||||
#include <mach/orion5x.h>
|
||||
#include "common.h"
|
||||
#include "mpp.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Linkstation LS-CHL Info
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* 256K NOR flash Device bus boot chip select
|
||||
*/
|
||||
|
||||
#define LSCHL_NOR_BOOT_BASE 0xf4000000
|
||||
#define LSCHL_NOR_BOOT_SIZE SZ_256K
|
||||
|
||||
/*****************************************************************************
|
||||
* 256KB NOR Flash on BOOT Device
|
||||
****************************************************************************/
|
||||
|
||||
static struct physmap_flash_data lschl_nor_flash_data = {
|
||||
.width = 1,
|
||||
};
|
||||
|
||||
static struct resource lschl_nor_flash_resource = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = LSCHL_NOR_BOOT_BASE,
|
||||
.end = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1,
|
||||
};
|
||||
|
||||
static struct platform_device lschl_nor_flash = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &lschl_nor_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &lschl_nor_flash_resource,
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* Ethernet
|
||||
****************************************************************************/
|
||||
|
||||
static struct mv643xx_eth_platform_data lschl_eth_data = {
|
||||
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* RTC 5C372a on I2C bus
|
||||
****************************************************************************/
|
||||
|
||||
static struct i2c_board_info __initdata lschl_i2c_rtc = {
|
||||
I2C_BOARD_INFO("rs5c372a", 0x32),
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* LEDs attached to GPIO
|
||||
****************************************************************************/
|
||||
|
||||
#define LSCHL_GPIO_LED_ALARM 2
|
||||
#define LSCHL_GPIO_LED_INFO 3
|
||||
#define LSCHL_GPIO_LED_FUNC 17
|
||||
#define LSCHL_GPIO_LED_PWR 0
|
||||
|
||||
static struct gpio_led lschl_led_pins[] = {
|
||||
{
|
||||
.name = "alarm:red",
|
||||
.gpio = LSCHL_GPIO_LED_ALARM,
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.name = "info:amber",
|
||||
.gpio = LSCHL_GPIO_LED_INFO,
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.name = "func:blue:top",
|
||||
.gpio = LSCHL_GPIO_LED_FUNC,
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.name = "power:blue:bottom",
|
||||
.gpio = LSCHL_GPIO_LED_PWR,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data lschl_led_data = {
|
||||
.leds = lschl_led_pins,
|
||||
.num_leds = ARRAY_SIZE(lschl_led_pins),
|
||||
};
|
||||
|
||||
static struct platform_device lschl_leds = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &lschl_led_data,
|
||||
},
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* SATA
|
||||
****************************************************************************/
|
||||
static struct mv_sata_platform_data lschl_sata_data = {
|
||||
.n_ports = 2,
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* LS-CHL specific power off method: reboot
|
||||
****************************************************************************/
|
||||
/*
|
||||
* On the LS-CHL, the shutdown process is following:
|
||||
* - Userland monitors key events until the power switch goes to off position
|
||||
* - The board reboots
|
||||
* - U-boot starts and goes into an idle mode waiting for the user
|
||||
* to move the switch to ON position
|
||||
*
|
||||
*/
|
||||
|
||||
static void lschl_power_off(void)
|
||||
{
|
||||
arm_machine_restart('h', NULL);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* General Setup
|
||||
****************************************************************************/
|
||||
#define LSCHL_GPIO_USB_POWER 9
|
||||
#define LSCHL_GPIO_AUTO_POWER 17
|
||||
#define LSCHL_GPIO_POWER 18
|
||||
|
||||
/****************************************************************************
|
||||
* GPIO Attached Keys
|
||||
****************************************************************************/
|
||||
#define LSCHL_GPIO_KEY_FUNC 15
|
||||
#define LSCHL_GPIO_KEY_POWER 8
|
||||
#define LSCHL_GPIO_KEY_AUTOPOWER 10
|
||||
#define LSCHL_SW_POWER 0x00
|
||||
#define LSCHL_SW_AUTOPOWER 0x01
|
||||
#define LSCHL_SW_FUNC 0x02
|
||||
|
||||
static struct gpio_keys_button lschl_buttons[] = {
|
||||
{
|
||||
.type = EV_SW,
|
||||
.code = LSCHL_SW_POWER,
|
||||
.gpio = LSCHL_GPIO_KEY_POWER,
|
||||
.desc = "Power-on Switch",
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.type = EV_SW,
|
||||
.code = LSCHL_SW_AUTOPOWER,
|
||||
.gpio = LSCHL_GPIO_KEY_AUTOPOWER,
|
||||
.desc = "Power-auto Switch",
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.type = EV_SW,
|
||||
.code = LSCHL_SW_FUNC,
|
||||
.gpio = LSCHL_GPIO_KEY_FUNC,
|
||||
.desc = "Function Switch",
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data lschl_button_data = {
|
||||
.buttons = lschl_buttons,
|
||||
.nbuttons = ARRAY_SIZE(lschl_buttons),
|
||||
};
|
||||
|
||||
static struct platform_device lschl_button_device = {
|
||||
.name = "gpio-keys",
|
||||
.id = -1,
|
||||
.num_resources = 0,
|
||||
.dev = {
|
||||
.platform_data = &lschl_button_data,
|
||||
},
|
||||
};
|
||||
|
||||
#define LSCHL_GPIO_HDD_POWER 1
|
||||
|
||||
/****************************************************************************
|
||||
* GPIO Fan
|
||||
****************************************************************************/
|
||||
|
||||
#define LSCHL_GPIO_FAN_LOW 16
|
||||
#define LSCHL_GPIO_FAN_HIGH 14
|
||||
#define LSCHL_GPIO_FAN_LOCK 6
|
||||
|
||||
static struct gpio_fan_alarm lschl_alarm = {
|
||||
.gpio = LSCHL_GPIO_FAN_LOCK,
|
||||
};
|
||||
|
||||
static struct gpio_fan_speed lschl_speeds[] = {
|
||||
{
|
||||
.rpm = 0,
|
||||
.ctrl_val = 3,
|
||||
}, {
|
||||
.rpm = 1500,
|
||||
.ctrl_val = 2,
|
||||
}, {
|
||||
.rpm = 3250,
|
||||
.ctrl_val = 1,
|
||||
}, {
|
||||
.rpm = 5000,
|
||||
.ctrl_val = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static int lschl_gpio_list[] = {
|
||||
LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW,
|
||||
};
|
||||
|
||||
static struct gpio_fan_platform_data lschl_fan_data = {
|
||||
.num_ctrl = ARRAY_SIZE(lschl_gpio_list),
|
||||
.ctrl = lschl_gpio_list,
|
||||
.alarm = &lschl_alarm,
|
||||
.num_speed = ARRAY_SIZE(lschl_speeds),
|
||||
.speed = lschl_speeds,
|
||||
};
|
||||
|
||||
static struct platform_device lschl_fan_device = {
|
||||
.name = "gpio-fan",
|
||||
.id = -1,
|
||||
.num_resources = 0,
|
||||
.dev = {
|
||||
.platform_data = &lschl_fan_data,
|
||||
},
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* GPIO Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
|
||||
{ 0, MPP_GPIO }, /* LED POWER */
|
||||
{ 1, MPP_GPIO }, /* HDD POWER */
|
||||
{ 2, MPP_GPIO }, /* LED ALARM */
|
||||
{ 3, MPP_GPIO }, /* LED INFO */
|
||||
{ 4, MPP_UNUSED },
|
||||
{ 5, MPP_UNUSED },
|
||||
{ 6, MPP_GPIO }, /* FAN LOCK */
|
||||
{ 7, MPP_GPIO }, /* SW INIT */
|
||||
{ 8, MPP_GPIO }, /* SW POWER */
|
||||
{ 9, MPP_GPIO }, /* USB POWER */
|
||||
{ 10, MPP_GPIO }, /* SW AUTO POWER */
|
||||
{ 11, MPP_UNUSED },
|
||||
{ 12, MPP_UNUSED },
|
||||
{ 13, MPP_UNUSED },
|
||||
{ 14, MPP_GPIO }, /* FAN HIGH */
|
||||
{ 15, MPP_GPIO }, /* SW FUNC */
|
||||
{ 16, MPP_GPIO }, /* FAN LOW */
|
||||
{ 17, MPP_GPIO }, /* LED FUNC */
|
||||
{ 18, MPP_UNUSED },
|
||||
{ 19, MPP_UNUSED },
|
||||
{ -1 },
|
||||
};
|
||||
|
||||
static void __init lschl_init(void)
|
||||
{
|
||||
/*
|
||||
* Setup basic Orion functions. Needs to be called early.
|
||||
*/
|
||||
orion5x_init();
|
||||
|
||||
orion5x_mpp_conf(lschl_mpp_modes);
|
||||
|
||||
/*
|
||||
* Configure peripherals.
|
||||
*/
|
||||
orion5x_ehci0_init();
|
||||
orion5x_ehci1_init();
|
||||
orion5x_eth_init(&lschl_eth_data);
|
||||
orion5x_i2c_init();
|
||||
orion5x_sata_init(&lschl_sata_data);
|
||||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE,
|
||||
LSCHL_NOR_BOOT_SIZE);
|
||||
platform_device_register(&lschl_nor_flash);
|
||||
|
||||
platform_device_register(&lschl_leds);
|
||||
|
||||
platform_device_register(&lschl_button_device);
|
||||
|
||||
platform_device_register(&lschl_fan_device);
|
||||
|
||||
i2c_register_board_info(0, &lschl_i2c_rtc, 1);
|
||||
|
||||
/* usb power on */
|
||||
gpio_set_value(LSCHL_GPIO_USB_POWER, 1);
|
||||
|
||||
/* register power-off method */
|
||||
pm_power_off = lschl_power_off;
|
||||
|
||||
pr_info("%s: finished\n", __func__);
|
||||
}
|
||||
|
||||
MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
|
||||
/* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
|
||||
.boot_params = 0x00000100,
|
||||
.init_machine = lschl_init,
|
||||
.map_io = orion5x_map_io,
|
||||
.init_irq = orion5x_init_irq,
|
||||
.timer = &orion5x_timer,
|
||||
.fixup = tag_fixup_mem32,
|
||||
MACHINE_END
|
||||
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