gpio/rockchip: add driver for rockchip gpio
This patch add support for rockchip gpio controller, which is supported in pinctrl driver in the past. With this patch, the pinctrl-rockchip driver will drop gpio related codes and populate platform driver to gpio-rockchip. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816012053.1119069-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jianqun Xu
Linus Walleij
Родитель
75d1415ea5
Коммит
936ee2675e
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@ -520,6 +520,14 @@ config GPIO_REG
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A 32-bit single register GPIO fixed in/out implementation. This
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can be used to represent any register as a set of GPIO signals.
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config GPIO_ROCKCHIP
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tristate "Rockchip GPIO support"
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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select GPIOLIB_IRQCHIP
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default ARCH_ROCKCHIP
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help
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Say yes here to support GPIO on Rockchip SoCs.
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config GPIO_SAMA5D2_PIOBU
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tristate "SAMA5D2 PIOBU GPIO support"
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depends on MFD_SYSCON
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@ -128,6 +128,7 @@ obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
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obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
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obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o
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obj-$(CONFIG_GPIO_REG) += gpio-reg.o
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obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o
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obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
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obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
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@ -0,0 +1,626 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include "../pinctrl/core.h"
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#include "../pinctrl/pinctrl-rockchip.h"
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/* GPIO control registers */
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#define GPIO_SWPORT_DR 0x00
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#define GPIO_SWPORT_DDR 0x04
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INT_STATUS 0x40
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#define GPIO_INT_RAWSTATUS 0x44
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#define GPIO_DEBOUNCE 0x48
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#define GPIO_PORTS_EOI 0x4c
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#define GPIO_EXT_PORT 0x50
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#define GPIO_LS_SYNC 0x60
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static int rockchip_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data;
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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if (data & BIT(offset))
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static int rockchip_gpio_set_direction(struct gpio_chip *chip,
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unsigned int offset, bool input)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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unsigned long flags;
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u32 data;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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/* set bit to 1 for output, 0 for input */
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if (!input)
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data |= BIT(offset);
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else
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data &= ~BIT(offset);
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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}
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
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unsigned long flags;
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u32 data;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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data &= ~BIT(offset);
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if (value)
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data |= BIT(offset);
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writel(data, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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u32 data;
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data = readl(bank->reg_base + GPIO_EXT_PORT);
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data >>= offset;
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data &= 1;
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return data;
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}
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static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset, bool enable)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
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unsigned long flags;
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u32 data;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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if (enable)
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data |= BIT(offset);
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else
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data &= ~BIT(offset);
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writel(data, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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static int rockchip_gpio_direction_input(struct gpio_chip *gc,
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unsigned int offset)
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{
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return rockchip_gpio_set_direction(gc, offset, true);
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}
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static int rockchip_gpio_direction_output(struct gpio_chip *gc,
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unsigned int offset, int value)
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{
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rockchip_gpio_set(gc, offset, value);
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return rockchip_gpio_set_direction(gc, offset, false);
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}
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/*
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* gpiolib set_config callback function. The setting of the pin
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* mux function as 'gpio output' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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unsigned long config)
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{
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enum pin_config_param param = pinconf_to_config_param(config);
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switch (param) {
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case PIN_CONFIG_INPUT_DEBOUNCE:
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rockchip_gpio_set_debounce(gc, offset, true);
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/*
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* Rockchip's gpio could only support up to one period
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* of the debounce clock(pclk), which is far away from
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* satisftying the requirement, as pclk is usually near
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* 100MHz shared by all peripherals. So the fact is it
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* has crippled debounce capability could only be useful
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* to prevent any spurious glitches from waking up the system
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* if the gpio is conguired as wakeup interrupt source. Let's
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* still return -ENOTSUPP as before, to make sure the caller
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* of gpiod_set_debounce won't change its behaviour.
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*/
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return -ENOTSUPP;
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default:
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return -ENOTSUPP;
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}
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}
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/*
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* gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
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* and a virtual IRQ, if not already present.
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*/
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static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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unsigned int virq;
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if (!bank->domain)
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return -ENXIO;
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virq = irq_create_mapping(bank->domain, offset);
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return (virq) ? : -ENXIO;
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}
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static const struct gpio_chip rockchip_gpiolib_chip = {
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.request = gpiochip_generic_request,
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.free = gpiochip_generic_free,
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.set = rockchip_gpio_set,
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.get = rockchip_gpio_get,
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.get_direction = rockchip_gpio_get_direction,
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.direction_input = rockchip_gpio_direction_input,
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.direction_output = rockchip_gpio_direction_output,
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.set_config = rockchip_gpio_set_config,
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.to_irq = rockchip_gpio_to_irq,
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.owner = THIS_MODULE,
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};
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static void rockchip_irq_demux(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
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u32 pend;
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dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
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chained_irq_enter(chip, desc);
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pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
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while (pend) {
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unsigned int irq, virq;
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irq = __ffs(pend);
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pend &= ~BIT(irq);
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virq = irq_find_mapping(bank->domain, irq);
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if (!virq) {
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dev_err(bank->dev, "unmapped irq %d\n", irq);
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continue;
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}
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dev_dbg(bank->dev, "handling irq %d\n", irq);
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/*
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* Triggering IRQ on both rising and falling edge
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* needs manual intervention.
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*/
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if (bank->toggle_edge_mode & BIT(irq)) {
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u32 data, data_old, polarity;
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unsigned long flags;
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data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
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do {
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raw_spin_lock_irqsave(&bank->slock, flags);
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polarity = readl_relaxed(bank->reg_base +
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GPIO_INT_POLARITY);
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if (data & BIT(irq))
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polarity &= ~BIT(irq);
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else
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polarity |= BIT(irq);
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writel(polarity,
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bank->reg_base + GPIO_INT_POLARITY);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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data_old = data;
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data = readl_relaxed(bank->reg_base +
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GPIO_EXT_PORT);
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} while ((data & BIT(irq)) != (data_old & BIT(irq)));
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}
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generic_handle_irq(virq);
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}
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chained_irq_exit(chip, desc);
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}
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static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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u32 mask = BIT(d->hwirq);
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u32 polarity;
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u32 level;
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u32 data;
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unsigned long flags;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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data &= ~mask;
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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raw_spin_lock_irqsave(&bank->slock, flags);
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irq_gc_lock(gc);
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level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
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polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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bank->toggle_edge_mode |= mask;
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level |= mask;
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/*
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* Determine gpio state. If 1 next interrupt should be falling
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* otherwise rising.
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*/
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data = readl(bank->reg_base + GPIO_EXT_PORT);
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if (data & mask)
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polarity &= ~mask;
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else
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polarity |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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bank->toggle_edge_mode &= ~mask;
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level |= mask;
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polarity |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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bank->toggle_edge_mode &= ~mask;
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level |= mask;
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polarity &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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bank->toggle_edge_mode &= ~mask;
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level &= ~mask;
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polarity |= mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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bank->toggle_edge_mode &= ~mask;
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level &= ~mask;
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polarity &= ~mask;
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break;
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default:
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irq_gc_unlock(gc);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return -EINVAL;
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}
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writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
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writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
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irq_gc_unlock(gc);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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}
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static void rockchip_irq_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
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irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
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}
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static void rockchip_irq_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
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}
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static void rockchip_irq_enable(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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irq_gc_mask_clr_bit(d);
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}
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static void rockchip_irq_disable(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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irq_gc_mask_set_bit(d);
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clk_disable(bank->clk);
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}
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static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct irq_chip_generic *gc;
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int ret;
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bank->domain = irq_domain_add_linear(bank->of_node, 32,
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&irq_generic_chip_ops, NULL);
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if (!bank->domain) {
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dev_warn(bank->dev, "could not init irq domain for bank %s\n",
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bank->name);
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return -EINVAL;
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}
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ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
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"rockchip_gpio_irq",
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handle_level_irq,
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clr, 0, 0);
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if (ret) {
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dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
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bank->name);
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irq_domain_remove(bank->domain);
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return -EINVAL;
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}
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gc = irq_get_domain_generic_chip(bank->domain, 0);
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gc->reg_base = bank->reg_base;
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gc->private = bank;
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gc->chip_types[0].regs.mask = GPIO_INTMASK;
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gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
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gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
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gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
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gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
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gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
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gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
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gc->wake_enabled = IRQ_MSK(bank->nr_pins);
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/*
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* Linux assumes that all interrupts start out disabled/masked.
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* Our driver only uses the concept of masked and always keeps
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* things enabled, so for us that's all masked and all enabled.
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*/
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writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
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writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI);
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writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
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gc->mask_cache = 0xffffffff;
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irq_set_chained_handler_and_data(bank->irq,
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rockchip_irq_demux, bank);
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||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
|
||||
{
|
||||
struct gpio_chip *gc;
|
||||
int ret;
|
||||
|
||||
bank->gpio_chip = rockchip_gpiolib_chip;
|
||||
|
||||
gc = &bank->gpio_chip;
|
||||
gc->base = bank->pin_base;
|
||||
gc->ngpio = bank->nr_pins;
|
||||
gc->label = bank->name;
|
||||
gc->parent = bank->dev;
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
gc->of_node = of_node_get(bank->of_node);
|
||||
#endif
|
||||
|
||||
ret = gpiochip_add_data(gc, bank);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
|
||||
gc->label, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* For DeviceTree-supported systems, the gpio core checks the
|
||||
* pinctrl's device node for the "gpio-ranges" property.
|
||||
* If it is present, it takes care of adding the pin ranges
|
||||
* for the driver. In this case the driver can skip ahead.
|
||||
*
|
||||
* In order to remain compatible with older, existing DeviceTree
|
||||
* files which don't set the "gpio-ranges" property or systems that
|
||||
* utilize ACPI the driver has to call gpiochip_add_pin_range().
|
||||
*/
|
||||
if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
|
||||
struct device_node *pctlnp = of_get_parent(bank->of_node);
|
||||
struct pinctrl_dev *pctldev = NULL;
|
||||
|
||||
if (!pctlnp)
|
||||
return -ENODATA;
|
||||
|
||||
pctldev = of_pinctrl_get(pctlnp);
|
||||
if (!pctldev)
|
||||
return -ENODEV;
|
||||
|
||||
ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
|
||||
gc->base, gc->ngpio);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "Failed to add pin range\n");
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
ret = rockchip_interrupts_register(bank);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
|
||||
{
|
||||
struct resource res;
|
||||
|
||||
if (of_address_to_resource(bank->of_node, 0, &res)) {
|
||||
dev_err(bank->dev, "cannot find IO resource for bank\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
bank->reg_base = devm_ioremap_resource(bank->dev, &res);
|
||||
if (IS_ERR(bank->reg_base))
|
||||
return PTR_ERR(bank->reg_base);
|
||||
|
||||
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
|
||||
|
||||
bank->clk = of_clk_get(bank->of_node, 0);
|
||||
if (!IS_ERR(bank->clk))
|
||||
return clk_prepare_enable(bank->clk);
|
||||
|
||||
bank->clk = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct rockchip_pin_bank *
|
||||
rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
|
||||
{
|
||||
struct rockchip_pinctrl *info;
|
||||
struct rockchip_pin_bank *bank;
|
||||
int i, found = 0;
|
||||
|
||||
info = pinctrl_dev_get_drvdata(pctldev);
|
||||
bank = info->ctrl->pin_banks;
|
||||
for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
|
||||
if (bank->bank_num == id) {
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return found ? bank : NULL;
|
||||
}
|
||||
|
||||
static int rockchip_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *pctlnp = of_get_parent(np);
|
||||
struct pinctrl_dev *pctldev = NULL;
|
||||
struct rockchip_pin_bank *bank = NULL;
|
||||
static int gpio;
|
||||
int id, ret;
|
||||
|
||||
if (!np || !pctlnp)
|
||||
return -ENODEV;
|
||||
|
||||
pctldev = of_pinctrl_get(pctlnp);
|
||||
if (!pctldev)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
id = of_alias_get_id(np, "gpio");
|
||||
if (id < 0)
|
||||
id = gpio++;
|
||||
|
||||
bank = rockchip_gpio_find_bank(pctldev, id);
|
||||
if (!bank)
|
||||
return -EINVAL;
|
||||
|
||||
bank->dev = dev;
|
||||
bank->of_node = np;
|
||||
|
||||
raw_spin_lock_init(&bank->slock);
|
||||
|
||||
ret = rockchip_get_bank_data(bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rockchip_gpiolib_register(bank);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(bank->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, bank);
|
||||
dev_info(dev, "probed %pOF\n", np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(bank->clk);
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_gpio_match[] = {
|
||||
{ .compatible = "rockchip,gpio-bank", },
|
||||
{ .compatible = "rockchip,rk3188-gpio-bank0" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver rockchip_gpio_driver = {
|
||||
.probe = rockchip_gpio_probe,
|
||||
.remove = rockchip_gpio_remove,
|
||||
.driver = {
|
||||
.name = "rockchip-gpio",
|
||||
.of_match_table = rockchip_gpio_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rockchip_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&rockchip_gpio_driver);
|
||||
}
|
||||
postcore_initcall(rockchip_gpio_init);
|
||||
|
||||
static void __exit rockchip_gpio_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&rockchip_gpio_driver);
|
||||
}
|
||||
module_exit(rockchip_gpio_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Rockchip gpio driver");
|
||||
MODULE_ALIAS("platform:rockchip-gpio");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
|
||||
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