EDAC, amd64: Reserve correct PCI devices on AMD Fam17h
Fam17h needs PCI device functions 0 and 6 instead of 1 and 2 as on older systems. Update struct amd64_pvt to hold the new functions and reserve them if on Fam17h. Also, allocate an array of UMC structs within our newly allocated PVT struct. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1479423463-8536-11-git-send-email-Yazen.Ghannam@amd.com [ init_one_instance() error handling, shorten lines, unbreak >80 cols lines. ] Signed-off-by: Borislav Petkov <bp@suse.de>
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@ -2274,30 +2274,55 @@ static inline void decode_bus_error(int node_id, struct mce *m)
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/*
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* Use pvt->F3 which contains the F3 CPU PCI device to get the related
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* F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
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* Reserve F0 and F6 on systems with a UMC.
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*/
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static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f2_id)
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static int
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reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
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{
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if (pvt->umc) {
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pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
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if (!pvt->F0) {
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amd64_err("error F0 device not found: vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, pci_id1);
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return -ENODEV;
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}
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pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
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if (!pvt->F6) {
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pci_dev_put(pvt->F0);
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pvt->F0 = NULL;
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amd64_err("error F6 device not found: vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, pci_id2);
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return -ENODEV;
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}
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edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
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edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
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edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));
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return 0;
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}
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/* Reserve the ADDRESS MAP Device */
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pvt->F1 = pci_get_related_function(pvt->F3->vendor, f1_id, pvt->F3);
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pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
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if (!pvt->F1) {
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amd64_err("error address map device not found: "
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"vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, f1_id);
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amd64_err("error address map device not found: vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, pci_id1);
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return -ENODEV;
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}
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/* Reserve the DCT Device */
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pvt->F2 = pci_get_related_function(pvt->F3->vendor, f2_id, pvt->F3);
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pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
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if (!pvt->F2) {
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pci_dev_put(pvt->F1);
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pvt->F1 = NULL;
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amd64_err("error F2 device not found: "
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"vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, f2_id);
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return -ENODEV;
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amd64_err("error F2 device not found: vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, pci_id2);
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return -ENODEV;
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}
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edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
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edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
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edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
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@ -2307,8 +2332,13 @@ static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f2_id)
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static void free_mc_sibling_devs(struct amd64_pvt *pvt)
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{
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pci_dev_put(pvt->F1);
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pci_dev_put(pvt->F2);
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if (pvt->umc) {
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pci_dev_put(pvt->F0);
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pci_dev_put(pvt->F6);
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} else {
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pci_dev_put(pvt->F1);
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pci_dev_put(pvt->F2);
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}
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}
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/*
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@ -2864,6 +2894,7 @@ static int init_one_instance(unsigned int nid)
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struct mem_ctl_info *mci = NULL;
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struct edac_mc_layer layers[2];
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struct amd64_pvt *pvt = NULL;
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u16 pci_id1, pci_id2;
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int err = 0, ret;
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ret = -ENOMEM;
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@ -2879,10 +2910,23 @@ static int init_one_instance(unsigned int nid)
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if (!fam_type)
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goto err_free;
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ret = -ENODEV;
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err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f2_id);
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if (pvt->fam >= 0x17) {
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pvt->umc = kcalloc(NUM_UMCS, sizeof(struct amd64_umc), GFP_KERNEL);
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if (!pvt->umc) {
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ret = -ENOMEM;
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goto err_free;
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}
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pci_id1 = fam_type->f0_id;
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pci_id2 = fam_type->f6_id;
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} else {
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pci_id1 = fam_type->f1_id;
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pci_id2 = fam_type->f2_id;
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}
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err = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2);
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if (err)
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goto err_free;
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goto err_post_init;
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read_mc_regs(pvt);
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@ -2942,6 +2986,10 @@ err_add_mc:
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err_siblings:
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free_mc_sibling_devs(pvt);
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err_post_init:
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if (pvt->fam >= 0x17)
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kfree(pvt->umc);
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err_free:
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kfree(pvt);
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@ -3044,7 +3092,10 @@ static void setup_pci_device(void)
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return;
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pvt = mci->pvt_info;
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pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
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if (pvt->umc)
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pci_ctl = edac_pci_create_generic_ctl(&pvt->F0->dev, EDAC_MOD_STR);
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else
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pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
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if (!pci_ctl) {
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pr_warn("%s(): Unable to create PCI control\n", __func__);
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pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
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@ -309,7 +309,7 @@ struct amd64_pvt {
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struct low_ops *ops;
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/* pci_device handles which we utilize */
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struct pci_dev *F1, *F2, *F3;
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struct pci_dev *F0, *F1, *F2, *F3, *F6;
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u16 mc_node_id; /* MC index of this MC node */
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u8 fam; /* CPU family */
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