[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Родитель
31aa36658a
Коммит
937a801576
|
@ -160,7 +160,7 @@ void dump_au1000_dma_channel(unsigned int dmanr)
|
|||
* Requests the DMA done IRQ if irqhandler != NULL.
|
||||
*/
|
||||
int request_au1000_dma(int dev_id, const char *dev_str,
|
||||
irqreturn_t (*irqhandler)(int, void *, struct pt_regs *),
|
||||
irqreturn_t (*irqhandler)(int, void *),
|
||||
unsigned long irqflags,
|
||||
void *irq_dev_id)
|
||||
{
|
||||
|
|
|
@ -67,7 +67,7 @@
|
|||
|
||||
extern void set_debug_traps(void);
|
||||
extern irq_cpustat_t irq_stat [NR_CPUS];
|
||||
extern void mips_timer_interrupt(struct pt_regs *regs);
|
||||
extern void mips_timer_interrupt(void);
|
||||
|
||||
static void setup_local_irq(unsigned int irq, int type, int int_req);
|
||||
static unsigned int startup_irq(unsigned int irq);
|
||||
|
@ -81,10 +81,6 @@ inline void local_disable_irq(unsigned int irq_nr);
|
|||
|
||||
void (*board_init_irq)(void);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
|
||||
#endif
|
||||
|
||||
static DEFINE_SPINLOCK(irq_lock);
|
||||
|
||||
|
||||
|
@ -292,7 +288,7 @@ static struct irq_chip level_irq_type = {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *))
|
||||
void startup_match20_interrupt(irqreturn_t (*handler)(int, void *))
|
||||
{
|
||||
struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
|
||||
|
||||
|
@ -501,14 +497,15 @@ void __init arch_init_irq(void)
|
|||
* intcX_reqX_irqdispatch().
|
||||
*/
|
||||
|
||||
void intc0_req0_irqdispatch(struct pt_regs *regs)
|
||||
static void intc0_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc0_req0 = 0;
|
||||
|
||||
intc0_req0 |= au_readl(IC0_REQ0INT);
|
||||
|
||||
if (!intc0_req0) return;
|
||||
if (!intc0_req0)
|
||||
return;
|
||||
#ifdef AU1000_USB_DEV_REQ_INT
|
||||
/*
|
||||
* Because of the tight timing of SETUP token to reply
|
||||
|
@ -517,28 +514,29 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
|
|||
*/
|
||||
if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
|
||||
intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
|
||||
do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
|
||||
do_IRQ(AU1000_USB_DEV_REQ_INT);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
irq = au_ffs(intc0_req0) - 1;
|
||||
intc0_req0 &= ~(1<<irq);
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
void intc0_req1_irqdispatch(struct pt_regs *regs)
|
||||
static void intc0_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc0_req1 = 0;
|
||||
|
||||
intc0_req1 |= au_readl(IC0_REQ1INT);
|
||||
|
||||
if (!intc0_req1) return;
|
||||
if (!intc0_req1)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc0_req1) - 1;
|
||||
intc0_req1 &= ~(1<<irq);
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
|
@ -546,35 +544,37 @@ void intc0_req1_irqdispatch(struct pt_regs *regs)
|
|||
* Interrupt Controller 1:
|
||||
* interrupts 32 - 63
|
||||
*/
|
||||
void intc1_req0_irqdispatch(struct pt_regs *regs)
|
||||
static void intc1_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req0 = 0;
|
||||
|
||||
intc1_req0 |= au_readl(IC1_REQ0INT);
|
||||
|
||||
if (!intc1_req0) return;
|
||||
if (!intc1_req0)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc1_req0) - 1;
|
||||
intc1_req0 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
|
||||
void intc1_req1_irqdispatch(struct pt_regs *regs)
|
||||
static void intc1_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req1 = 0;
|
||||
|
||||
intc1_req1 |= au_readl(IC1_REQ1INT);
|
||||
|
||||
if (!intc1_req1) return;
|
||||
if (!intc1_req1)
|
||||
return;
|
||||
|
||||
irq = au_ffs(intc1_req1) - 1;
|
||||
intc1_req1 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
@ -660,20 +660,20 @@ restore_au1xxx_intctl(void)
|
|||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
mips_timer_interrupt(regs);
|
||||
mips_timer_interrupt();
|
||||
else if (pending & CAUSEF_IP2)
|
||||
intc0_req0_irqdispatch(regs);
|
||||
intc0_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP3)
|
||||
intc0_req1_irqdispatch(regs);
|
||||
intc0_req1_irqdispatch();
|
||||
else if (pending & CAUSEF_IP4)
|
||||
intc1_req0_irqdispatch(regs);
|
||||
intc1_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP5)
|
||||
intc1_req1_irqdispatch(regs);
|
||||
intc1_req1_irqdispatch();
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
|
|
@ -62,7 +62,7 @@ static unsigned int timerhi = 0, timerlo = 0;
|
|||
#error "unsupported HZ value! Must be in [100,1000]"
|
||||
#endif
|
||||
#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
|
||||
extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *));
|
||||
extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *));
|
||||
static unsigned long last_pc0, last_match20;
|
||||
#endif
|
||||
|
||||
|
@ -79,7 +79,8 @@ static inline void ack_r4ktimer(unsigned long newval)
|
|||
* is provably more robust.
|
||||
*/
|
||||
unsigned long wtimer;
|
||||
void mips_timer_interrupt(struct pt_regs *regs)
|
||||
|
||||
void mips_timer_interrupt(void)
|
||||
{
|
||||
int irq = 63;
|
||||
unsigned long count;
|
||||
|
@ -98,7 +99,7 @@ void mips_timer_interrupt(struct pt_regs *regs)
|
|||
kstat_this_cpu.irqs[irq]++;
|
||||
do_timer(1);
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(regs));
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
r4k_cur += r4k_offset;
|
||||
ack_r4ktimer(r4k_cur);
|
||||
|
@ -115,7 +116,7 @@ null:
|
|||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
|
||||
irqreturn_t counter0_irq(int irq, void *dev_id)
|
||||
{
|
||||
unsigned long pc0;
|
||||
int time_elapsed;
|
||||
|
@ -139,7 +140,7 @@ irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
|
|||
while (time_elapsed > 0) {
|
||||
do_timer(1);
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(regs));
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
time_elapsed -= MATCH20_INC;
|
||||
last_match20 += MATCH20_INC;
|
||||
|
@ -158,7 +159,7 @@ irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
|
|||
jiffie_drift -= 999;
|
||||
do_timer(1); /* increment jiffies by one */
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(regs));
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -1031,8 +1031,7 @@ process_ep_receive (struct usb_dev* dev, endpoint_t *ep)
|
|||
|
||||
|
||||
/* This ISR handles the receive complete and suspend events */
|
||||
static void
|
||||
req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
|
||||
static void req_sus_intr (int irq, void *dev_id)
|
||||
{
|
||||
struct usb_dev *dev = (struct usb_dev *) dev_id;
|
||||
u32 status;
|
||||
|
@ -1050,8 +1049,7 @@ req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
|
|||
|
||||
|
||||
/* This ISR handles the DMA done events on EP0 */
|
||||
static void
|
||||
dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static void dma_done_ep0_intr(int irq, void *dev_id)
|
||||
{
|
||||
struct usb_dev *dev = (struct usb_dev *) dev_id;
|
||||
usbdev_pkt_t* pkt;
|
||||
|
@ -1094,8 +1092,7 @@ dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
|
|||
}
|
||||
|
||||
/* This ISR handles the DMA done events on endpoints 2,3,4,5 */
|
||||
static void
|
||||
dma_done_ep_intr(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static void dma_done_ep_intr(int irq, void *dev_id)
|
||||
{
|
||||
struct usb_dev *dev = (struct usb_dev *) dev_id;
|
||||
int i;
|
||||
|
|
|
@ -65,7 +65,7 @@ int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
|
|||
*/
|
||||
static volatile int pb1200_cascade_en=0;
|
||||
|
||||
irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
|
||||
irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
|
||||
{
|
||||
unsigned short bisr = bcsr->int_status;
|
||||
int extirq_nr = 0;
|
||||
|
@ -76,8 +76,9 @@ irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
|
|||
{
|
||||
extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
|
||||
/* Ack and dispatch IRQ */
|
||||
do_IRQ(extirq_nr,regs);
|
||||
do_IRQ(extirq_nr);
|
||||
}
|
||||
|
||||
return IRQ_RETVAL(1);
|
||||
}
|
||||
|
||||
|
|
|
@ -112,7 +112,7 @@ int putDebugChar(int data)
|
|||
}
|
||||
|
||||
/* KGDB interrupt handler */
|
||||
asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
|
||||
asmlinkage void excite_kgdb_inthdl(void)
|
||||
{
|
||||
if (unlikely(
|
||||
((titan_readl(UAIIR) & 0x7) == 4)
|
||||
|
|
|
@ -38,7 +38,7 @@ static int iodev_open(struct inode *, struct file *);
|
|||
static int iodev_release(struct inode *, struct file *);
|
||||
static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
|
||||
static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
|
||||
static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
|
||||
static irqreturn_t iodev_irqhdl(int, void *);
|
||||
|
||||
|
||||
|
||||
|
@ -108,16 +108,12 @@ static int __exit iodev_remove(struct device *dev)
|
|||
return misc_deregister(&miscdev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int iodev_open(struct inode *i, struct file *f)
|
||||
{
|
||||
return request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
|
||||
iodev_name, &miscdev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int iodev_release(struct inode *i, struct file *f)
|
||||
{
|
||||
free_irq(iodev_irq, &miscdev);
|
||||
|
@ -148,17 +144,13 @@ static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
|
|||
return POLLOUT | POLLWRNORM;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
|
||||
static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
|
||||
{
|
||||
wake_up(&wq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int __init iodev_init_module(void)
|
||||
{
|
||||
return driver_register(&iodev_driver);
|
||||
|
|
|
@ -56,7 +56,7 @@ void __init arch_init_irq(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
const u32
|
||||
interrupts = read_c0_cause() >> 8,
|
||||
|
@ -67,7 +67,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
/* process timer interrupt */
|
||||
if (pending & (1 << TIMER_IRQ)) {
|
||||
do_IRQ(TIMER_IRQ, regs);
|
||||
do_IRQ(TIMER_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -80,7 +80,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
#else
|
||||
if (pending & (1 << USB_IRQ)) {
|
||||
#endif
|
||||
do_IRQ(USB_IRQ, regs);
|
||||
do_IRQ(USB_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -91,9 +91,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
if ((pending & (1 << TITAN_IRQ)) && msgint) {
|
||||
ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
|
||||
#if defined(CONFIG_KGDB)
|
||||
excite_kgdb_inthdl(regs);
|
||||
excite_kgdb_inthdl();
|
||||
#endif
|
||||
do_IRQ(TITAN_IRQ, regs);
|
||||
do_IRQ(TITAN_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -102,7 +102,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
|
||||
if ((pending & (1 << FPGA0_IRQ)) && msgint) {
|
||||
do_IRQ(FPGA0_IRQ, regs);
|
||||
do_IRQ(FPGA0_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -111,7 +111,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
|
||||
if ((pending & (1 << FPGA1_IRQ)) && msgint) {
|
||||
do_IRQ(FPGA1_IRQ, regs);
|
||||
do_IRQ(FPGA1_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -120,10 +120,10 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
|
||||
if ((pending & (1 << PHY_IRQ)) && msgint) {
|
||||
do_IRQ(PHY_IRQ, regs);
|
||||
do_IRQ(PHY_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process spurious interrupts */
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
|
|
@ -42,7 +42,7 @@
|
|||
* 15 - IDE1
|
||||
*/
|
||||
|
||||
static inline void galileo_irq(struct pt_regs *regs)
|
||||
static inline void galileo_irq(void)
|
||||
{
|
||||
unsigned int mask, pending, devfn;
|
||||
|
||||
|
@ -52,7 +52,7 @@ static inline void galileo_irq(struct pt_regs *regs)
|
|||
if (pending & GALILEO_INTR_T0EXP) {
|
||||
|
||||
GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
|
||||
do_IRQ(COBALT_GALILEO_IRQ, regs);
|
||||
do_IRQ(COBALT_GALILEO_IRQ);
|
||||
|
||||
} else if (pending & GALILEO_INTR_RETRY_CTR) {
|
||||
|
||||
|
@ -68,44 +68,31 @@ static inline void galileo_irq(struct pt_regs *regs)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void via_pic_irq(struct pt_regs *regs)
|
||||
static inline void via_pic_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
irq = i8259_irq();
|
||||
if (irq >= 0)
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned pending;
|
||||
unsigned pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
|
||||
|
||||
galileo_irq(regs);
|
||||
|
||||
else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
|
||||
|
||||
via_pic_irq(regs);
|
||||
|
||||
else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
|
||||
|
||||
do_IRQ(COBALT_CPU_IRQ + 3, regs);
|
||||
|
||||
else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
|
||||
|
||||
do_IRQ(COBALT_CPU_IRQ + 4, regs);
|
||||
|
||||
else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
|
||||
|
||||
do_IRQ(COBALT_CPU_IRQ + 5, regs);
|
||||
|
||||
else if (pending & CAUSEF_IP7) /* IRQ 23 */
|
||||
|
||||
do_IRQ(COBALT_CPU_IRQ + 7, regs);
|
||||
if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
|
||||
galileo_irq();
|
||||
else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
|
||||
via_pic_irq();
|
||||
else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
|
||||
do_IRQ(COBALT_CPU_IRQ + 3);
|
||||
else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
|
||||
do_IRQ(COBALT_CPU_IRQ + 4);
|
||||
else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
|
||||
do_IRQ(COBALT_CPU_IRQ + 5);
|
||||
else if (pending & CAUSEF_IP7) /* IRQ 23 */
|
||||
do_IRQ(COBALT_CPU_IRQ + 7);
|
||||
}
|
||||
|
||||
static struct irqaction irq_via = {
|
||||
|
|
|
@ -153,8 +153,7 @@ u8 i8259_interrupt_ack(void)
|
|||
* the first level int-handler will jump here if it is a vrc5477 irq
|
||||
*/
|
||||
#define NUM_5477_IRQS 32
|
||||
static void
|
||||
vrc5477_irq_dispatch(struct pt_regs *regs)
|
||||
static void vrc5477_irq_dispatch(void)
|
||||
{
|
||||
u32 intStatus;
|
||||
u32 bitmask;
|
||||
|
@ -178,7 +177,7 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
|
|||
/* check for i8259 interrupts */
|
||||
if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
|
||||
int i8259_irq = i8259_interrupt_ack();
|
||||
do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
|
||||
do_IRQ(I8259_IRQ_BASE + i8259_irq);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -186,7 +185,7 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
|
|||
for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
|
||||
/* do we need to "and" with the int mask? */
|
||||
if (intStatus & bitmask) {
|
||||
do_IRQ(VRC5477_IRQ_BASE + i, regs);
|
||||
do_IRQ(VRC5477_IRQ_BASE + i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -194,18 +193,18 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(CPU_IRQ_BASE + 7, regs);
|
||||
do_IRQ(CPU_IRQ_BASE + 7);
|
||||
else if (pending & VR5477INTS)
|
||||
vrc5477_irq_dispatch(regs);
|
||||
vrc5477_irq_dispatch();
|
||||
else if (pending & STATUSF_IP0)
|
||||
do_IRQ(CPU_IRQ_BASE, regs);
|
||||
do_IRQ(CPU_IRQ_BASE);
|
||||
else if (pending & STATUSF_IP1)
|
||||
do_IRQ(CPU_IRQ_BASE + 1, regs);
|
||||
do_IRQ(CPU_IRQ_BASE + 1);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
|
|
@ -264,8 +264,10 @@
|
|||
srlv t3,t1,t2
|
||||
|
||||
handle_it:
|
||||
LONG_L s0, TI_REGS($28)
|
||||
LONG_S sp, TI_REGS($28)
|
||||
jal do_IRQ
|
||||
move a1,sp
|
||||
LONG_S s0, TI_REGS($28)
|
||||
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
/*
|
||||
* the first level int-handler will jump here if it is a emma2rh irq
|
||||
*/
|
||||
asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
|
||||
void emma2rh_irq_dispatch(void)
|
||||
{
|
||||
u32 intStatus;
|
||||
u32 bitmask;
|
||||
|
@ -56,7 +56,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
|
|||
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
|
||||
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
|
||||
if (swIntStatus & bitmask) {
|
||||
do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
|
||||
do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -65,7 +65,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
|
||||
if (intStatus & bitmask) {
|
||||
do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
|
||||
do_IRQ(EMMA2RH_IRQ_BASE + i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -81,7 +81,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
|
|||
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
|
||||
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
|
||||
if (gpioIntStatus & bitmask) {
|
||||
do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
|
||||
do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -90,7 +90,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
|
||||
if (intStatus & bitmask) {
|
||||
do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
|
||||
do_IRQ(EMMA2RH_IRQ_BASE + i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -100,7 +100,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
|
||||
if (intStatus & bitmask) {
|
||||
do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
|
||||
do_IRQ(EMMA2RH_IRQ_BASE + i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -57,7 +57,7 @@
|
|||
extern void emma2rh_sw_irq_init(u32 base);
|
||||
extern void emma2rh_gpio_irq_init(u32 base);
|
||||
extern void emma2rh_irq_init(u32 base);
|
||||
extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs);
|
||||
extern void emma2rh_irq_dispatch(void);
|
||||
|
||||
static struct irqaction irq_cascade = {
|
||||
.handler = no_action,
|
||||
|
@ -114,20 +114,20 @@ void __init arch_init_irq(void)
|
|||
setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(CPU_IRQ_BASE + 7, regs);
|
||||
do_IRQ(CPU_IRQ_BASE + 7);
|
||||
else if (pending & STATUSF_IP2)
|
||||
emma2rh_irq_dispatch(regs);
|
||||
emma2rh_irq_dispatch();
|
||||
else if (pending & STATUSF_IP1)
|
||||
do_IRQ(CPU_IRQ_BASE + 1, regs);
|
||||
do_IRQ(CPU_IRQ_BASE + 1);
|
||||
else if (pending & STATUSF_IP0)
|
||||
do_IRQ(CPU_IRQ_BASE + 0, regs);
|
||||
do_IRQ(CPU_IRQ_BASE + 0);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
|
@ -19,7 +20,7 @@
|
|||
* differently than other MIPS interrupts.
|
||||
*/
|
||||
|
||||
static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static void gt64120_irq(int irq, void *dev_id)
|
||||
{
|
||||
unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
|
||||
int handled = 0;
|
||||
|
@ -36,7 +37,7 @@ static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs)
|
|||
irq_src &= ~0x00000800;
|
||||
do_timer(1);
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(regs));
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -46,22 +46,22 @@
|
|||
#include <asm/system.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP2) /* int0 hardware line */
|
||||
do_IRQ(GT_INTA, regs);
|
||||
do_IRQ(GT_INTA);
|
||||
else if (pending & STATUSF_IP5) /* int3 hardware line */
|
||||
do_IRQ(GT_INTD, regs);
|
||||
do_IRQ(GT_INTD);
|
||||
else if (pending & STATUSF_IP6) /* int4 hardware line */
|
||||
do_IRQ(6, regs);
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7) /* compare int */
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
static void disable_ev64120_irq(unsigned int irq_nr)
|
||||
|
|
|
@ -48,22 +48,22 @@
|
|||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & STATUSF_IP2) /* int0 hardware line */
|
||||
do_IRQ(2, regs);
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3) /* int1 hardware line */
|
||||
do_IRQ(3, regs);
|
||||
do_IRQ(3);
|
||||
else if (pending & STATUSF_IP4) /* int2 hardware line */
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5) /* int3 hardware line */
|
||||
do_IRQ(5, regs);
|
||||
do_IRQ(5);
|
||||
else if (pending & STATUSF_IP6) /* int4 hardware line */
|
||||
do_IRQ(6, regs);
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7) /* cpu timer */
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
else {
|
||||
/*
|
||||
* Now look at the extended interrupts
|
||||
|
@ -71,13 +71,13 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
|
||||
|
||||
if (pending & STATUSF_IP8) /* int6 hardware line */
|
||||
do_IRQ(8, regs);
|
||||
do_IRQ(8);
|
||||
else if (pending & STATUSF_IP9) /* int7 hardware line */
|
||||
do_IRQ(9, regs);
|
||||
do_IRQ(9);
|
||||
else if (pending & STATUSF_IP10) /* int8 hardware line */
|
||||
do_IRQ(10, regs);
|
||||
do_IRQ(10);
|
||||
else if (pending & STATUSF_IP11) /* int9 hardware line */
|
||||
do_IRQ(11, regs);
|
||||
do_IRQ(11);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -30,18 +30,18 @@
|
|||
#include <asm/irq_cpu.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */
|
||||
do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */
|
||||
do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
|
||||
else if (pending & STATUSF_IP3)
|
||||
do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */
|
||||
do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -94,26 +94,26 @@ void __init arch_init_irq(void)
|
|||
change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
|
||||
}
|
||||
|
||||
static void loc_call(unsigned int irq, struct pt_regs *regs, unsigned int mask)
|
||||
static void loc_call(unsigned int irq, unsigned int mask)
|
||||
{
|
||||
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
|
||||
r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask);
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
|
||||
r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask);
|
||||
}
|
||||
|
||||
static void ll_local_dev(struct pt_regs *regs)
|
||||
static void ll_local_dev(void)
|
||||
{
|
||||
switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) {
|
||||
case 0:
|
||||
panic("Unimplemented loc_no_irq handler");
|
||||
break;
|
||||
case 4:
|
||||
loc_call(JAZZ_PARALLEL_IRQ, regs, JAZZ_IE_PARALLEL);
|
||||
loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL);
|
||||
break;
|
||||
case 8:
|
||||
loc_call(JAZZ_PARALLEL_IRQ, regs, JAZZ_IE_FLOPPY);
|
||||
loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY);
|
||||
break;
|
||||
case 12:
|
||||
panic("Unimplemented loc_sound handler");
|
||||
|
@ -122,27 +122,27 @@ static void ll_local_dev(struct pt_regs *regs)
|
|||
panic("Unimplemented loc_video handler");
|
||||
break;
|
||||
case 20:
|
||||
loc_call(JAZZ_ETHERNET_IRQ, regs, JAZZ_IE_ETHERNET);
|
||||
loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET);
|
||||
break;
|
||||
case 24:
|
||||
loc_call(JAZZ_SCSI_IRQ, regs, JAZZ_IE_SCSI);
|
||||
loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI);
|
||||
break;
|
||||
case 28:
|
||||
loc_call(JAZZ_KEYBOARD_IRQ, regs, JAZZ_IE_KEYBOARD);
|
||||
loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD);
|
||||
break;
|
||||
case 32:
|
||||
loc_call(JAZZ_MOUSE_IRQ, regs, JAZZ_IE_MOUSE);
|
||||
loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE);
|
||||
break;
|
||||
case 36:
|
||||
loc_call(JAZZ_SERIAL1_IRQ, regs, JAZZ_IE_SERIAL1);
|
||||
loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1);
|
||||
break;
|
||||
case 40:
|
||||
loc_call(JAZZ_SERIAL2_IRQ, regs, JAZZ_IE_SERIAL2);
|
||||
loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
|
||||
|
@ -150,13 +150,13 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
write_c0_compare(0);
|
||||
else if (pending & IE_IRQ4) {
|
||||
r4030_read_reg32(JAZZ_TIMER_REGISTER);
|
||||
do_IRQ(JAZZ_TIMER_IRQ, regs);
|
||||
do_IRQ(JAZZ_TIMER_IRQ);
|
||||
} else if (pending & IE_IRQ3)
|
||||
panic("Unimplemented ISA NMI handler");
|
||||
else if (pending & IE_IRQ2)
|
||||
do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK), regs);
|
||||
do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK));
|
||||
else if (pending & IE_IRQ1) {
|
||||
ll_local_dev(regs);
|
||||
ll_local_dev();
|
||||
} else if (unlikely(pending & IE_IRQ0))
|
||||
panic("Unimplemented local_dma handler");
|
||||
else if (pending & IE_SW1) {
|
||||
|
|
|
@ -46,6 +46,7 @@
|
|||
#include <linux/smp_lock.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
@ -239,45 +240,80 @@ struct tb_irq_space jmr3927_ioc_irqspace = {
|
|||
.space_id = 0,
|
||||
can_share : 1
|
||||
};
|
||||
|
||||
struct tb_irq_space jmr3927_irc_irqspace = {
|
||||
.next = NULL,
|
||||
.start_irqno = JMR3927_IRQ_IRC,
|
||||
nr_irqs : JMR3927_NR_IRQ_IRC,
|
||||
.mask_func = mask_irq_irc,
|
||||
.unmask_func = unmask_irq_irc,
|
||||
.name = "on-chip",
|
||||
.space_id = 0,
|
||||
can_share : 0
|
||||
.next = NULL,
|
||||
.start_irqno = JMR3927_IRQ_IRC,
|
||||
.nr_irqs = JMR3927_NR_IRQ_IRC,
|
||||
.mask_func = mask_irq_irc,
|
||||
.unmask_func = unmask_irq_irc,
|
||||
.name = "on-chip",
|
||||
.space_id = 0,
|
||||
.can_share = 0
|
||||
};
|
||||
|
||||
void jmr3927_spurious(struct pt_regs *regs)
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
static int tx_branch_likely_bug_count = 0;
|
||||
static int have_tx_branch_likely_bug = 0;
|
||||
|
||||
static void tx_branch_likely_bug_fixup(void)
|
||||
{
|
||||
struct pt_regs *regs = get_irq_regs();
|
||||
|
||||
/* TX39/49-BUG: Under this condition, the insn in delay slot
|
||||
of the branch likely insn is executed (not nullified) even
|
||||
the branch condition is false. */
|
||||
if (!have_tx_branch_likely_bug)
|
||||
return;
|
||||
if ((regs->cp0_epc & 0xfff) == 0xffc &&
|
||||
KSEGX(regs->cp0_epc) != KSEG0 &&
|
||||
KSEGX(regs->cp0_epc) != KSEG1) {
|
||||
unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
|
||||
/* beql,bnel,blezl,bgtzl */
|
||||
/* bltzl,bgezl,blezall,bgezall */
|
||||
/* bczfl, bcztl */
|
||||
if ((insn & 0xf0000000) == 0x50000000 ||
|
||||
(insn & 0xfc0e0000) == 0x04020000 ||
|
||||
(insn & 0xf3fe0000) == 0x41020000) {
|
||||
regs->cp0_epc -= 4;
|
||||
tx_branch_likely_bug_count++;
|
||||
printk(KERN_INFO
|
||||
"fix branch-likery bug in %s (insn %08x)\n",
|
||||
current->comm, insn);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void jmr3927_spurious(void)
|
||||
{
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
tx_branch_likely_bug_fixup(regs);
|
||||
tx_branch_likely_bug_fixup();
|
||||
#endif
|
||||
printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
|
||||
regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
tx_branch_likely_bug_fixup(regs);
|
||||
tx_branch_likely_bug_fixup();
|
||||
#endif
|
||||
if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
|
||||
#if 0
|
||||
jmr3927_spurious(regs);
|
||||
jmr3927_spurious();
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
|
||||
|
||||
do_IRQ(irq + JMR3927_IRQ_IRC, regs);
|
||||
do_IRQ(irq + JMR3927_IRQ_IRC);
|
||||
}
|
||||
|
||||
static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
|
||||
int i;
|
||||
|
@ -285,7 +321,7 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *
|
|||
for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
|
||||
if (istat & (1 << i)) {
|
||||
irq = JMR3927_IRQ_IOC + i;
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
|
@ -295,7 +331,7 @@ static struct irqaction ioc_action = {
|
|||
jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
|
||||
};
|
||||
|
||||
static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
|
||||
int i;
|
||||
|
@ -303,7 +339,7 @@ static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs
|
|||
for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
|
||||
if (istat & (1 << i)) {
|
||||
irq = JMR3927_IRQ_ISAC + i;
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
|
@ -314,7 +350,7 @@ static struct irqaction isac_action = {
|
|||
};
|
||||
|
||||
|
||||
static irqreturn_t jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
|
||||
static irqreturn_t jmr3927_isaerr_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
|
||||
|
||||
|
@ -324,7 +360,7 @@ static struct irqaction isaerr_action = {
|
|||
jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
|
||||
};
|
||||
|
||||
static irqreturn_t jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
|
||||
static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
|
||||
printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
|
||||
|
@ -439,33 +475,3 @@ void jmr3927_irq_init(u32 irq_base)
|
|||
|
||||
jmr3927_irq_base = irq_base;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
static int tx_branch_likely_bug_count = 0;
|
||||
static int have_tx_branch_likely_bug = 0;
|
||||
void tx_branch_likely_bug_fixup(struct pt_regs *regs)
|
||||
{
|
||||
/* TX39/49-BUG: Under this condition, the insn in delay slot
|
||||
of the branch likely insn is executed (not nullified) even
|
||||
the branch condition is false. */
|
||||
if (!have_tx_branch_likely_bug)
|
||||
return;
|
||||
if ((regs->cp0_epc & 0xfff) == 0xffc &&
|
||||
KSEGX(regs->cp0_epc) != KSEG0 &&
|
||||
KSEGX(regs->cp0_epc) != KSEG1) {
|
||||
unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
|
||||
/* beql,bnel,blezl,bgtzl */
|
||||
/* bltzl,bgezl,blezall,bgezall */
|
||||
/* bczfl, bcztl */
|
||||
if ((insn & 0xf0000000) == 0x50000000 ||
|
||||
(insn & 0xfc0e0000) == 0x04020000 ||
|
||||
(insn & 0xf3fe0000) == 0x41020000) {
|
||||
regs->cp0_epc -= 4;
|
||||
tx_branch_likely_bug_count++;
|
||||
printk(KERN_INFO
|
||||
"fix branch-likery bug in %s (insn %08x)\n",
|
||||
current->comm, insn);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -93,11 +93,12 @@ void output_thread_info_defines(void)
|
|||
offset("#define TI_TASK ", struct thread_info, task);
|
||||
offset("#define TI_EXEC_DOMAIN ", struct thread_info, exec_domain);
|
||||
offset("#define TI_FLAGS ", struct thread_info, flags);
|
||||
offset("#define TI_TP_VALUE ", struct thread_info, tp_value);
|
||||
offset("#define TI_CPU ", struct thread_info, cpu);
|
||||
offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count);
|
||||
offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit);
|
||||
offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block);
|
||||
offset("#define TI_TP_VALUE ", struct thread_info, tp_value);
|
||||
offset("#define TI_REGS ", struct thread_info, regs);
|
||||
constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER);
|
||||
constant("#define _THREAD_SIZE ", THREAD_SIZE);
|
||||
constant("#define _THREAD_MASK ", THREAD_MASK);
|
||||
|
|
|
@ -79,7 +79,6 @@ FEXPORT(syscall_exit)
|
|||
FEXPORT(restore_all) # restore full frame
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
/* Detect and execute deferred IPI "interrupts" */
|
||||
move a0,sp
|
||||
jal deferred_smtc_ipi
|
||||
/* Re-arm any temporarily masked interrupts not explicitly "acked" */
|
||||
mfc0 v0, CP0_TCSTATUS
|
||||
|
|
|
@ -131,9 +131,11 @@ NESTED(handle_int, PT_SIZE, sp)
|
|||
CLI
|
||||
TRACE_IRQS_OFF
|
||||
|
||||
PTR_LA ra, ret_from_irq
|
||||
move a0, sp
|
||||
j plat_irq_dispatch
|
||||
LONG_L s0, TI_REGS($28)
|
||||
LONG_S sp, TI_REGS($28)
|
||||
jal plat_irq_dispatch
|
||||
LONG_S s0, TI_REGS($28)
|
||||
j ret_from_irq
|
||||
END(handle_int)
|
||||
|
||||
__INIT
|
||||
|
@ -219,9 +221,12 @@ NESTED(except_vec_vi_handler, 0, sp)
|
|||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
CLI
|
||||
TRACE_IRQS_OFF
|
||||
move a0, sp
|
||||
|
||||
LONG_L s0, TI_REGS($28)
|
||||
LONG_S sp, TI_REGS($28)
|
||||
jalr v0
|
||||
LONG_S s0, TI_REGS($28)
|
||||
PTR_LA ra, ret_from_irq
|
||||
jr v0
|
||||
END(except_vec_vi_handler)
|
||||
|
||||
/*
|
||||
|
|
|
@ -115,14 +115,14 @@ static void end_msc_irq(unsigned int irq)
|
|||
/*
|
||||
* Interrupt handler for interrupts coming from SOC-it.
|
||||
*/
|
||||
void ll_msc_irq(struct pt_regs *regs)
|
||||
void ll_msc_irq(void)
|
||||
{
|
||||
unsigned int irq;
|
||||
|
||||
/* read the interrupt vector register */
|
||||
MSCIC_READ(MSC01_IC_VEC, irq);
|
||||
if (irq < 64)
|
||||
do_IRQ(irq + irq_base, regs);
|
||||
do_IRQ(irq + irq_base);
|
||||
else {
|
||||
/* Ignore spurious interrupt */
|
||||
}
|
||||
|
|
|
@ -113,7 +113,7 @@ static void end_mv64340_irq(unsigned int irq)
|
|||
* Interrupt handler for interrupts coming from the Marvell chip.
|
||||
* It could be built in ethernet ports etc...
|
||||
*/
|
||||
void ll_mv64340_irq(struct pt_regs *regs)
|
||||
void ll_mv64340_irq(void)
|
||||
{
|
||||
unsigned int irq_src_low, irq_src_high;
|
||||
unsigned int irq_mask_low, irq_mask_high;
|
||||
|
@ -129,9 +129,9 @@ void ll_mv64340_irq(struct pt_regs *regs)
|
|||
irq_src_high &= irq_mask_high;
|
||||
|
||||
if (irq_src_low)
|
||||
do_IRQ(ls1bit32(irq_src_low) + irq_base, regs);
|
||||
do_IRQ(ls1bit32(irq_src_low) + irq_base);
|
||||
else
|
||||
do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs);
|
||||
do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
|
||||
}
|
||||
|
||||
#define shutdown_mv64340_irq disable_mv64340_irq
|
||||
|
|
|
@ -53,9 +53,8 @@ unsigned long irq_hwmask[NR_IRQS];
|
|||
* SMP cross-CPU interrupts have their own specific
|
||||
* handlers).
|
||||
*/
|
||||
asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs)
|
||||
asmlinkage unsigned int do_IRQ(unsigned int irq)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
irq_enter();
|
||||
|
||||
__DO_IRQ_SMTC_HOOK();
|
||||
|
@ -63,7 +62,6 @@ asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs)
|
|||
|
||||
irq_exit();
|
||||
|
||||
set_irq_regs(old_regs);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
@ -112,7 +110,7 @@ skip:
|
|||
return 0;
|
||||
}
|
||||
|
||||
asmlinkage void spurious_interrupt(struct pt_regs *regs)
|
||||
asmlinkage void spurious_interrupt(void)
|
||||
{
|
||||
atomic_inc(&irq_err_count);
|
||||
}
|
||||
|
|
|
@ -61,16 +61,16 @@ static int sp_stopping = 0;
|
|||
|
||||
extern void *vpe_get_shared(int index);
|
||||
|
||||
static void rtlx_dispatch(struct pt_regs *regs)
|
||||
static void rtlx_dispatch(void)
|
||||
{
|
||||
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ);
|
||||
}
|
||||
|
||||
|
||||
/* Interrupt handler may be called before rtlx_init has otherwise had
|
||||
a chance to run.
|
||||
*/
|
||||
static irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
@ -106,22 +106,22 @@ void __init sanitize_tlb_entries(void)
|
|||
clear_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
}
|
||||
|
||||
static void ipi_resched_dispatch (struct pt_regs *regs)
|
||||
static void ipi_resched_dispatch(void)
|
||||
{
|
||||
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
|
||||
}
|
||||
|
||||
static void ipi_call_dispatch (struct pt_regs *regs)
|
||||
static void ipi_call_dispatch(void)
|
||||
{
|
||||
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ);
|
||||
}
|
||||
|
||||
irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
|
||||
|
@ -250,8 +250,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
|
|||
{
|
||||
/* set up ipi interrupts */
|
||||
if (cpu_has_vint) {
|
||||
set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
|
||||
set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
|
||||
set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
|
||||
set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
|
||||
}
|
||||
|
||||
cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
|
||||
|
|
|
@ -82,7 +82,7 @@ struct smtc_ipi_q freeIPIq;
|
|||
|
||||
/* Forward declarations */
|
||||
|
||||
void ipi_decode(struct pt_regs *, struct smtc_ipi *);
|
||||
void ipi_decode(struct smtc_ipi *);
|
||||
void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
|
||||
void setup_cross_vpe_interrupts(void);
|
||||
void init_smtc_stats(void);
|
||||
|
@ -820,19 +820,19 @@ void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
|
|||
write_tc_c0_tcrestart(__smtc_ipi_vector);
|
||||
}
|
||||
|
||||
void ipi_resched_interrupt(struct pt_regs *regs)
|
||||
static void ipi_resched_interrupt(void)
|
||||
{
|
||||
/* Return from interrupt should be enough to cause scheduler check */
|
||||
}
|
||||
|
||||
|
||||
void ipi_call_interrupt(struct pt_regs *regs)
|
||||
static void ipi_call_interrupt(void)
|
||||
{
|
||||
/* Invoke generic function invocation code in smp.c */
|
||||
smp_call_function_interrupt();
|
||||
}
|
||||
|
||||
void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi)
|
||||
void ipi_decode(struct smtc_ipi *pipi)
|
||||
{
|
||||
void *arg_copy = pipi->arg;
|
||||
int type_copy = pipi->type;
|
||||
|
@ -846,15 +846,15 @@ void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi)
|
|||
#ifdef SMTC_IDLE_HOOK_DEBUG
|
||||
clock_hang_reported[dest_copy] = 0;
|
||||
#endif /* SMTC_IDLE_HOOK_DEBUG */
|
||||
local_timer_interrupt(0, NULL, regs);
|
||||
local_timer_interrupt(0, NULL);
|
||||
break;
|
||||
case LINUX_SMP_IPI:
|
||||
switch ((int)arg_copy) {
|
||||
case SMP_RESCHEDULE_YOURSELF:
|
||||
ipi_resched_interrupt(regs);
|
||||
ipi_resched_interrupt();
|
||||
break;
|
||||
case SMP_CALL_FUNCTION:
|
||||
ipi_call_interrupt(regs);
|
||||
ipi_call_interrupt();
|
||||
break;
|
||||
default:
|
||||
printk("Impossible SMTC IPI Argument 0x%x\n",
|
||||
|
@ -868,7 +868,7 @@ void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi)
|
|||
}
|
||||
}
|
||||
|
||||
void deferred_smtc_ipi(struct pt_regs *regs)
|
||||
void deferred_smtc_ipi(void)
|
||||
{
|
||||
struct smtc_ipi *pipi;
|
||||
unsigned long flags;
|
||||
|
@ -883,7 +883,7 @@ void deferred_smtc_ipi(struct pt_regs *regs)
|
|||
while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
|
||||
/* ipi_decode() should be called with interrupts off */
|
||||
local_irq_save(flags);
|
||||
ipi_decode(regs, pipi);
|
||||
ipi_decode(pipi);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
}
|
||||
|
@ -917,7 +917,7 @@ void smtc_timer_broadcast(int vpe)
|
|||
|
||||
static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ;
|
||||
|
||||
static irqreturn_t ipi_interrupt(int irq, void *dev_idm, struct pt_regs *regs)
|
||||
static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
|
||||
{
|
||||
int my_vpe = cpu_data[smp_processor_id()].vpe_id;
|
||||
int my_tc = cpu_data[smp_processor_id()].tc_id;
|
||||
|
@ -978,7 +978,7 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm, struct pt_regs *regs)
|
|||
* with interrupts off
|
||||
*/
|
||||
local_irq_save(flags);
|
||||
ipi_decode(regs, pipi);
|
||||
ipi_decode(pipi);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
}
|
||||
|
@ -987,9 +987,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm, struct pt_regs *regs)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void ipi_irq_dispatch(struct pt_regs *regs)
|
||||
static void ipi_irq_dispatch(void)
|
||||
{
|
||||
do_IRQ(cpu_ipi_irq, regs);
|
||||
do_IRQ(cpu_ipi_irq);
|
||||
}
|
||||
|
||||
static struct irqaction irq_ipi;
|
||||
|
|
|
@ -324,8 +324,7 @@ static long last_rtc_update;
|
|||
*/
|
||||
void local_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
if (current->pid)
|
||||
profile_tick(CPU_PROFILING);
|
||||
profile_tick(CPU_PROFILING);
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
}
|
||||
|
||||
|
@ -434,9 +433,8 @@ int (*perf_irq)(void) = null_perf_irq;
|
|||
EXPORT_SYMBOL(null_perf_irq);
|
||||
EXPORT_SYMBOL(perf_irq);
|
||||
|
||||
asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
|
||||
asmlinkage void ll_timer_interrupt(int irq)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
int r2 = cpu_has_mips_r2;
|
||||
|
||||
irq_enter();
|
||||
|
@ -458,12 +456,10 @@ asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
|
|||
|
||||
out:
|
||||
irq_exit();
|
||||
set_irq_regs(old_regs);
|
||||
}
|
||||
|
||||
asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs)
|
||||
asmlinkage void ll_local_timer_interrupt(int irq)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
irq_enter();
|
||||
if (smp_processor_id() != 0)
|
||||
kstat_this_cpu.irqs[irq]++;
|
||||
|
@ -472,7 +468,6 @@ asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs)
|
|||
local_timer_interrupt(irq, NULL);
|
||||
|
||||
irq_exit();
|
||||
set_irq_regs(old_regs);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -108,14 +108,14 @@ static unsigned long get_int_status_200(void)
|
|||
return int_status;
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned long int_status;
|
||||
unsigned int cause = read_c0_cause();
|
||||
int irq;
|
||||
|
||||
if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
|
||||
ll_timer_interrupt(7, regs);
|
||||
ll_timer_interrupt(7);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -125,7 +125,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
if (int_status) {
|
||||
irq = ls1bit32(int_status);
|
||||
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -101,7 +101,7 @@ static inline int ls1bit32(unsigned int x)
|
|||
return b;
|
||||
}
|
||||
|
||||
static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
|
||||
static inline void atlas_hw0_irqdispatch(void)
|
||||
{
|
||||
unsigned long int_status;
|
||||
int irq;
|
||||
|
@ -116,7 +116,7 @@ static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
|
|||
|
||||
DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
|
||||
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
static inline int clz(unsigned long x)
|
||||
|
@ -188,7 +188,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
|
|||
* then we just return, if multiple IRQs are pending then we will just take
|
||||
* another exception, big deal.
|
||||
*/
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
int irq;
|
||||
|
@ -196,11 +196,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
irq = irq_ffs(pending);
|
||||
|
||||
if (irq == MIPSCPU_INT_ATLAS)
|
||||
atlas_hw0_irqdispatch(regs);
|
||||
atlas_hw0_irqdispatch();
|
||||
else if (irq >= 0)
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
static inline void init_atlas_irqs (int base)
|
||||
|
|
|
@ -82,19 +82,19 @@ static inline void scroll_display_message(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void mips_timer_dispatch (struct pt_regs *regs)
|
||||
static void mips_timer_dispatch(void)
|
||||
{
|
||||
do_IRQ (mips_cpu_timer_irq, regs);
|
||||
do_IRQ(mips_cpu_timer_irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Redeclare until I get around mopping the timer code insanity on MIPS.
|
||||
*/
|
||||
extern int null_perf_irq(struct pt_regs *regs);
|
||||
extern int null_perf_irq(void);
|
||||
|
||||
extern int (*perf_irq)(struct pt_regs *regs);
|
||||
extern int (*perf_irq)(void);
|
||||
|
||||
irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
|
@ -119,7 +119,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
* perf counter overflow, or both.
|
||||
*/
|
||||
if (read_c0_cause() & (1 << 26))
|
||||
perf_irq(regs);
|
||||
perf_irq();
|
||||
|
||||
if (read_c0_cause() & (1 << 30)) {
|
||||
/* If timer interrupt, make it de-assert */
|
||||
|
@ -139,13 +139,13 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
* the tick on VPE 0 to run the full timer_interrupt().
|
||||
*/
|
||||
if (cpu_data[cpu].vpe_id == 0) {
|
||||
timer_interrupt(irq, NULL, regs);
|
||||
timer_interrupt(irq, NULL);
|
||||
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
|
||||
scroll_display_message();
|
||||
} else {
|
||||
write_c0_compare(read_c0_count() +
|
||||
(mips_hpt_frequency/HZ));
|
||||
local_timer_interrupt(irq, dev_id, regs);
|
||||
local_timer_interrupt(irq, dev_id);
|
||||
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
|
||||
}
|
||||
}
|
||||
|
@ -159,12 +159,12 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
* timer int.
|
||||
*/
|
||||
if (!r2 || (read_c0_cause() & (1 << 26)))
|
||||
if (perf_irq(regs))
|
||||
if (perf_irq())
|
||||
goto out;
|
||||
|
||||
/* we keep interrupt disabled all the time */
|
||||
if (!r2 || (read_c0_cause() & (1 << 30)))
|
||||
timer_interrupt(irq, NULL, regs);
|
||||
timer_interrupt(irq, NULL);
|
||||
|
||||
scroll_display_message();
|
||||
} else {
|
||||
|
@ -180,7 +180,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
/*
|
||||
* Other CPUs should do profiling and process accounting
|
||||
*/
|
||||
local_timer_interrupt(irq, dev_id, regs);
|
||||
local_timer_interrupt(irq, dev_id);
|
||||
}
|
||||
out:
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
|
|
|
@ -114,7 +114,7 @@ static inline int get_int(void)
|
|||
return irq;
|
||||
}
|
||||
|
||||
static void malta_hw0_irqdispatch(struct pt_regs *regs)
|
||||
static void malta_hw0_irqdispatch(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
|
@ -123,17 +123,21 @@ static void malta_hw0_irqdispatch(struct pt_regs *regs)
|
|||
return; /* interrupt has already been cleared */
|
||||
}
|
||||
|
||||
do_IRQ(MALTA_INT_BASE+irq, regs);
|
||||
do_IRQ(MALTA_INT_BASE + irq);
|
||||
}
|
||||
|
||||
void corehi_irqdispatch(struct pt_regs *regs)
|
||||
static void corehi_irqdispatch(void)
|
||||
{
|
||||
unsigned int intedge, intsteer, pcicmd, pcibadaddr;
|
||||
unsigned int pcimstat, intisr, inten, intpol;
|
||||
unsigned int intrcause,datalo,datahi;
|
||||
unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
|
||||
struct pt_regs *regs;
|
||||
|
||||
printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
|
||||
printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
|
||||
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
|
||||
printk("epc : %08lx\nStatus: %08lx\n"
|
||||
"Cause : %08lx\nbadVaddr : %08lx\n",
|
||||
regs->cp0_epc, regs->cp0_status,
|
||||
regs->cp0_cause, regs->cp0_badvaddr);
|
||||
|
||||
/* Read all the registers and then print them as there is a
|
||||
problem with interspersed printk's upsetting the Bonito controller.
|
||||
|
@ -146,7 +150,7 @@ void corehi_irqdispatch(struct pt_regs *regs)
|
|||
case MIPS_REVISION_CORID_CORE_FPGA3:
|
||||
case MIPS_REVISION_CORID_CORE_24K:
|
||||
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
|
||||
ll_msc_irq(regs);
|
||||
ll_msc_irq();
|
||||
break;
|
||||
case MIPS_REVISION_CORID_QED_RM5261:
|
||||
case MIPS_REVISION_CORID_CORE_LV:
|
||||
|
@ -255,7 +259,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
|
|||
* another exception, big deal.
|
||||
*/
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
int irq;
|
||||
|
@ -263,11 +267,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
irq = irq_ffs(pending);
|
||||
|
||||
if (irq == MIPSCPU_INT_I8259A)
|
||||
malta_hw0_irqdispatch(regs);
|
||||
malta_hw0_irqdispatch();
|
||||
else if (irq > 0)
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
static struct irqaction i8259irq = {
|
||||
|
|
|
@ -98,7 +98,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
|
|||
* then we just return, if multiple IRQs are pending then we will just take
|
||||
* another exception, big deal.
|
||||
*/
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
int irq;
|
||||
|
@ -106,7 +106,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
irq = irq_ffs(pending);
|
||||
|
||||
if (irq >= 0)
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
}
|
||||
|
|
|
@ -71,12 +71,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
|
|||
#endif
|
||||
}
|
||||
|
||||
static inline void sim_hw0_irqdispatch(struct pt_regs *regs)
|
||||
{
|
||||
do_IRQ(2, regs);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
int irq;
|
||||
|
@ -84,9 +79,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
irq = irq_ffs(pending);
|
||||
|
||||
if (irq > 0)
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq, regs);
|
||||
do_IRQ(MIPSCPU_INT_BASE + irq);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
|
||||
unsigned long cpu_khz;
|
||||
|
||||
irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int cpu = smp_processor_id();
|
||||
|
@ -44,7 +44,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
*/
|
||||
#ifndef CONFIG_MIPS_MT_SMTC
|
||||
if (cpu == 0) {
|
||||
timer_interrupt(irq, dev_id, regs);
|
||||
timer_interrupt(irq, dev_id);
|
||||
}
|
||||
else {
|
||||
/* Everyone else needs to reset the timer int here as
|
||||
|
@ -84,7 +84,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
irq_enable_hazard();
|
||||
evpe(vpflags);
|
||||
|
||||
if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs);
|
||||
if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id);
|
||||
else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
|
||||
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
|
||||
|
||||
|
@ -93,10 +93,10 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
/*
|
||||
* every CPU should do profiling and process accounting
|
||||
*/
|
||||
local_timer_interrupt (irq, dev_id, regs);
|
||||
local_timer_interrupt (irq, dev_id);
|
||||
return IRQ_HANDLED;
|
||||
#else
|
||||
return timer_interrupt (irq, dev_id, regs);
|
||||
return timer_interrupt (irq, dev_id);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -177,9 +177,9 @@ void __init sim_time_init(void)
|
|||
|
||||
static int mips_cpu_timer_irq;
|
||||
|
||||
static void mips_timer_dispatch (struct pt_regs *regs)
|
||||
static void mips_timer_dispatch(void)
|
||||
{
|
||||
do_IRQ (mips_cpu_timer_irq, regs);
|
||||
do_IRQ(mips_cpu_timer_irq);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -40,33 +40,33 @@
|
|||
#include <asm/mipsregs.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP0)
|
||||
do_IRQ(0, regs);
|
||||
do_IRQ(0);
|
||||
else if (pending & STATUSF_IP1)
|
||||
do_IRQ(1, regs);
|
||||
do_IRQ(1);
|
||||
else if (pending & STATUSF_IP2)
|
||||
do_IRQ(2, regs);
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3)
|
||||
do_IRQ(3, regs);
|
||||
do_IRQ(3);
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(5, regs);
|
||||
do_IRQ(5);
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(6, regs);
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7)
|
||||
ll_timer_interrupt(7, regs);
|
||||
ll_timer_interrupt(7);
|
||||
else {
|
||||
/*
|
||||
* Now look at the extended interrupts
|
||||
*/
|
||||
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
|
||||
if (pending & STATUSF_IP8)
|
||||
ll_mv64340_irq(regs);
|
||||
ll_mv64340_irq();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -75,26 +75,26 @@ void __init arch_init_irq(void)
|
|||
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP0)
|
||||
do_IRQ(0, regs);
|
||||
do_IRQ(0);
|
||||
else if (pending & STATUSF_IP1)
|
||||
do_IRQ(1, regs);
|
||||
do_IRQ(1);
|
||||
else if (pending & STATUSF_IP2)
|
||||
do_IRQ(2, regs);
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3)
|
||||
do_IRQ(3, regs);
|
||||
do_IRQ(3);
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(5, regs);
|
||||
do_IRQ(5);
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(6, regs);
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7)
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
else {
|
||||
/*
|
||||
* Now look at the extended interrupts
|
||||
|
@ -102,8 +102,8 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
|
||||
|
||||
if (pending & STATUSF_IP8)
|
||||
ll_mv64340_irq(regs);
|
||||
ll_mv64340_irq();
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -112,7 +112,7 @@ static void end_cpci_irq(unsigned int irq)
|
|||
* Interrupt handler for interrupts coming from the FPGA chip.
|
||||
* It could be built in ethernet ports etc...
|
||||
*/
|
||||
void ll_cpci_irq(struct pt_regs *regs)
|
||||
void ll_cpci_irq(void)
|
||||
{
|
||||
unsigned int irq_src, irq_mask;
|
||||
|
||||
|
@ -123,7 +123,7 @@ void ll_cpci_irq(struct pt_regs *regs)
|
|||
/* mask for just the interrupts we want */
|
||||
irq_src &= ~irq_mask;
|
||||
|
||||
do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
|
||||
do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
|
||||
}
|
||||
|
||||
#define shutdown_cpci_irq disable_cpci_irq
|
||||
|
|
|
@ -59,31 +59,31 @@ static struct irqaction cascade_mv64340 = {
|
|||
no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
|
||||
};
|
||||
|
||||
extern void ll_uart_irq(struct pt_regs *regs);
|
||||
extern void ll_cpci_irq(struct pt_regs *regs);
|
||||
extern void ll_uart_irq(void);
|
||||
extern void ll_cpci_irq(void);
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP0)
|
||||
do_IRQ(0, regs);
|
||||
do_IRQ(0);
|
||||
else if (pending & STATUSF_IP1)
|
||||
do_IRQ(1, regs);
|
||||
do_IRQ(1);
|
||||
else if (pending & STATUSF_IP2)
|
||||
do_IRQ(2, regs);
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3)
|
||||
ll_uart_irq(regs);
|
||||
ll_uart_irq();
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5)
|
||||
ll_cpci_irq(regs);
|
||||
ll_cpci_irq();
|
||||
else if (pending & STATUSF_IP6)
|
||||
ll_mv64340_irq(regs);
|
||||
else if (pending & STATUSF_IP7)
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -105,7 +105,7 @@ static void end_uart_irq(unsigned int irq)
|
|||
/*
|
||||
* Interrupt handler for interrupts coming from the FPGA chip.
|
||||
*/
|
||||
void ll_uart_irq(struct pt_regs *regs)
|
||||
void ll_uart_irq(void)
|
||||
{
|
||||
unsigned int irq_src, irq_mask;
|
||||
|
||||
|
@ -116,7 +116,7 @@ void ll_uart_irq(struct pt_regs *regs)
|
|||
/* mask for just the interrupts we want */
|
||||
irq_src &= ~irq_mask;
|
||||
|
||||
do_IRQ(ls1bit8(irq_src) + 74, regs);
|
||||
do_IRQ(ls1bit8(irq_src) + 74);
|
||||
}
|
||||
|
||||
#define shutdown_uart_irq disable_uart_irq
|
||||
|
|
|
@ -108,7 +108,7 @@ int disable_galileo_irq(int int_cause, int bit_num)
|
|||
* we keep this particular structure in the function.
|
||||
*/
|
||||
|
||||
static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs)
|
||||
static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
|
||||
{
|
||||
uint32_t irq_src, irq_src_mask;
|
||||
int handled;
|
||||
|
@ -135,7 +135,7 @@ static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs)
|
|||
/* handle the timer call */
|
||||
do_timer(1);
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(regs));
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -48,22 +48,22 @@
|
|||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP2)
|
||||
do_IRQ(2, regs);
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3)
|
||||
do_IRQ(3, regs);
|
||||
do_IRQ(3);
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(5, regs);
|
||||
do_IRQ(5);
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(6, regs);
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7)
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
else {
|
||||
/*
|
||||
* Now look at the extended interrupts
|
||||
|
@ -71,15 +71,15 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
|
||||
|
||||
if (pending & STATUSF_IP8)
|
||||
do_IRQ(8, regs);
|
||||
do_IRQ(8);
|
||||
else if (pending & STATUSF_IP9)
|
||||
do_IRQ(9, regs);
|
||||
do_IRQ(9);
|
||||
else if (pending & STATUSF_IP10)
|
||||
do_IRQ(10, regs);
|
||||
do_IRQ(10);
|
||||
else if (pending & STATUSF_IP11)
|
||||
do_IRQ(11, regs);
|
||||
do_IRQ(11);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -12,8 +12,8 @@
|
|||
|
||||
struct pt_regs;
|
||||
|
||||
extern int null_perf_irq(struct pt_regs *regs);
|
||||
extern int (*perf_irq)(struct pt_regs *regs);
|
||||
extern int null_perf_irq(void);
|
||||
extern int (*perf_irq)(void);
|
||||
|
||||
/* Per-counter configuration as set via oprofilefs. */
|
||||
struct op_counter_config {
|
||||
|
|
|
@ -3,12 +3,13 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2004, 2005 by Ralf Baechle
|
||||
* Copyright (C) 2004, 05, 06 by Ralf Baechle
|
||||
* Copyright (C) 2005 by MIPS Technologies, Inc.
|
||||
*/
|
||||
#include <linux/oprofile.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/irq_regs.h>
|
||||
|
||||
#include "op_impl.h"
|
||||
|
||||
|
@ -170,7 +171,7 @@ static void mipsxx_cpu_stop(void *args)
|
|||
}
|
||||
}
|
||||
|
||||
static int mipsxx_perfcount_handler(struct pt_regs *regs)
|
||||
static int mipsxx_perfcount_handler(void)
|
||||
{
|
||||
unsigned int counters = op_model_mipsxx_ops.num_counters;
|
||||
unsigned int control;
|
||||
|
@ -184,7 +185,7 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs)
|
|||
counter = r_c0_perfcntr ## n(); \
|
||||
if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
|
||||
(counter & M_COUNTER_OVERFLOW)) { \
|
||||
oprofile_add_sample(regs, n); \
|
||||
oprofile_add_sample(get_irq_regs(), n); \
|
||||
w_c0_perfcntr ## n(reg.counter[n]); \
|
||||
handled = 1; \
|
||||
}
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
* registered on the bridge error irq. It's conceivable that some of these
|
||||
* conditions warrant a panic. Anybody care to say which ones?
|
||||
*/
|
||||
static irqreturn_t macepci_error(int irq, void *dev, struct pt_regs *regs)
|
||||
static irqreturn_t macepci_error(int irq, void *dev)
|
||||
{
|
||||
char s;
|
||||
unsigned int flags = mace->pci.error;
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/sched.h>
|
||||
|
@ -52,7 +53,7 @@ static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
|
|||
1 // 70
|
||||
};
|
||||
|
||||
static void hw0_irqdispatch(int irq, struct pt_regs *regs)
|
||||
static void hw0_irqdispatch(int irq)
|
||||
{
|
||||
/* find out which interrupt */
|
||||
irq = PNX8550_GIC_VECTOR_0 >> 3;
|
||||
|
@ -61,42 +62,39 @@ static void hw0_irqdispatch(int irq, struct pt_regs *regs)
|
|||
printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
|
||||
return;
|
||||
}
|
||||
do_IRQ(PNX8550_INT_GIC_MIN + irq, regs);
|
||||
do_IRQ(PNX8550_INT_GIC_MIN + irq);
|
||||
}
|
||||
|
||||
|
||||
static void timer_irqdispatch(int irq, struct pt_regs *regs)
|
||||
static void timer_irqdispatch(int irq)
|
||||
{
|
||||
irq = (0x01c0 & read_c0_config7()) >> 6;
|
||||
|
||||
if (irq == 0) {
|
||||
if (unlikely(irq == 0)) {
|
||||
printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (irq & 0x1) {
|
||||
do_IRQ(PNX8550_INT_TIMER1, regs);
|
||||
}
|
||||
if (irq & 0x2) {
|
||||
do_IRQ(PNX8550_INT_TIMER2, regs);
|
||||
}
|
||||
if (irq & 0x4) {
|
||||
do_IRQ(PNX8550_INT_TIMER3, regs);
|
||||
}
|
||||
if (irq & 0x1)
|
||||
do_IRQ(PNX8550_INT_TIMER1);
|
||||
if (irq & 0x2)
|
||||
do_IRQ(PNX8550_INT_TIMER2);
|
||||
if (irq & 0x4)
|
||||
do_IRQ(PNX8550_INT_TIMER3);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & STATUSF_IP2)
|
||||
hw0_irqdispatch(2, regs);
|
||||
hw0_irqdispatch(2);
|
||||
else if (pending & STATUSF_IP7) {
|
||||
if (read_c0_config7() & 0x01c0)
|
||||
timer_irqdispatch(7, regs);
|
||||
timer_irqdispatch(7);
|
||||
}
|
||||
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
|
||||
|
|
|
@ -56,15 +56,13 @@
|
|||
#define HYPERTRANSPORT_INTC 0x7a /* INTC# */
|
||||
#define HYPERTRANSPORT_INTD 0x7b /* INTD# */
|
||||
|
||||
extern void jaguar_mailbox_irq(struct pt_regs *);
|
||||
|
||||
/*
|
||||
* Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
|
||||
* For interprocessor interrupts, the best thing to do is to use the INTMSG
|
||||
* register. We use the same external interrupt line, i.e. INTB3 and monitor
|
||||
* another status bit
|
||||
*/
|
||||
asmlinkage void ll_ht_smp_irq_handler(int irq, struct pt_regs *regs)
|
||||
static void ll_ht_smp_irq_handler(int irq)
|
||||
{
|
||||
u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
|
||||
|
||||
|
@ -107,50 +105,35 @@ asmlinkage void ll_ht_smp_irq_handler(int irq, struct pt_regs *regs)
|
|||
}
|
||||
#endif /* CONFIG_HT_LEVEL_TRIGGER */
|
||||
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
asmlinkage void do_extended_irq(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int intcontrol = read_c0_intcontrol();
|
||||
unsigned int cause = read_c0_cause();
|
||||
unsigned int status = read_c0_status();
|
||||
unsigned int pending_sr, pending_ic;
|
||||
|
||||
pending_sr = status & cause & 0xff00;
|
||||
pending_ic = (cause >> 8) & intcontrol & 0xff00;
|
||||
|
||||
if (pending_ic & (1 << 13))
|
||||
do_IRQ(13, regs);
|
||||
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int cause = read_c0_cause();
|
||||
unsigned int status = read_c0_status();
|
||||
unsigned int pending = cause & status;
|
||||
|
||||
if (pending & STATUSF_IP7) {
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
} else if (pending & STATUSF_IP2) {
|
||||
#ifdef CONFIG_HYPERTRANSPORT
|
||||
ll_ht_smp_irq_handler(2, regs);
|
||||
ll_ht_smp_irq_handler(2);
|
||||
#else
|
||||
do_IRQ(2, regs);
|
||||
do_IRQ(2);
|
||||
#endif
|
||||
} else if (pending & STATUSF_IP3) {
|
||||
do_IRQ(3, regs);
|
||||
do_IRQ(3);
|
||||
} else if (pending & STATUSF_IP4) {
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
} else if (pending & STATUSF_IP5) {
|
||||
#ifdef CONFIG_SMP
|
||||
titan_mailbox_irq(regs);
|
||||
titan_mailbox_irq();
|
||||
#else
|
||||
do_IRQ(5, regs);
|
||||
do_IRQ(5);
|
||||
#endif
|
||||
} else if (pending & STATUSF_IP6) {
|
||||
do_IRQ(4, regs);
|
||||
do_IRQ(4);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -178,18 +161,3 @@ void __init arch_init_irq(void)
|
|||
register_gdb_console();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
/*
|
||||
* The 16550 DUART has two ports, but is allocated one IRQ
|
||||
* for the serial console. Hence, a generic framework for
|
||||
* serial IRQ routing in place. Currently, just calls the
|
||||
* do_IRQ fuction. But, going in the future, need to check
|
||||
* DUART registers for channel A and B, then decide the
|
||||
* appropriate action
|
||||
*/
|
||||
asmlinkage void yosemite_kgdb_irq(int irq, struct pt_regs *regs)
|
||||
{
|
||||
do_IRQ(irq, regs);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -110,7 +110,7 @@ void prom_smp_finish(void)
|
|||
{
|
||||
}
|
||||
|
||||
asmlinkage void titan_mailbox_irq(struct pt_regs *regs)
|
||||
asmlinkage void titan_mailbox_irq(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
unsigned long status;
|
||||
|
|
|
@ -9,19 +9,19 @@
|
|||
|
||||
extern asmlinkage void qemu_handle_int(void);
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & 0x8000) {
|
||||
ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs);
|
||||
ll_timer_interrupt(Q_COUNT_COMPARE_IRQ);
|
||||
return;
|
||||
}
|
||||
if (pending & 0x0400) {
|
||||
int irq = i8259_irq();
|
||||
|
||||
if (likely(irq >= 0))
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#include <asm/system.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/branch.h>
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/sgi/mc.h>
|
||||
#include <asm/sgi/hpc3.h>
|
||||
#include <asm/sgi/ioc.h>
|
||||
|
@ -85,9 +86,10 @@ static void print_buserr(void)
|
|||
* and then clear the interrupt when this happens.
|
||||
*/
|
||||
|
||||
void ip22_be_interrupt(int irq, struct pt_regs *regs)
|
||||
void ip22_be_interrupt(int irq)
|
||||
{
|
||||
const int field = 2 * sizeof(unsigned long);
|
||||
const struct pt_regs *regs = get_irq_regs();
|
||||
|
||||
save_and_clear_buserr();
|
||||
print_buserr();
|
||||
|
|
|
@ -70,7 +70,7 @@ static char __init *decode_eisa_sig(unsigned long addr)
|
|||
return sig_str;
|
||||
}
|
||||
|
||||
static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
|
||||
static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
|
||||
{
|
||||
u8 eisa_irq;
|
||||
u8 dma1, dma2;
|
||||
|
@ -80,7 +80,7 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
|
|||
dma2 = inb(EISA_DMA2_STATUS);
|
||||
|
||||
if (eisa_irq < EISA_MAX_IRQ) {
|
||||
do_IRQ(eisa_irq, regs);
|
||||
do_IRQ(eisa_irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -89,6 +89,7 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
|
|||
|
||||
outb(0x20, EISA_INT2_CTRL);
|
||||
outb(0x20, EISA_INT1_CTRL);
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
|
|
|
@ -222,7 +222,7 @@ static struct irq_chip ip22_local3_irq_type = {
|
|||
.end = end_local3_irq,
|
||||
};
|
||||
|
||||
static void indy_local0_irqdispatch(struct pt_regs *regs)
|
||||
static void indy_local0_irqdispatch(void)
|
||||
{
|
||||
u8 mask = sgint->istat0 & sgint->imask0;
|
||||
u8 mask2;
|
||||
|
@ -236,11 +236,10 @@ static void indy_local0_irqdispatch(struct pt_regs *regs)
|
|||
|
||||
/* if irq == 0, then the interrupt has already been cleared */
|
||||
if (irq)
|
||||
do_IRQ(irq, regs);
|
||||
return;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
static void indy_local1_irqdispatch(struct pt_regs *regs)
|
||||
static void indy_local1_irqdispatch(void)
|
||||
{
|
||||
u8 mask = sgint->istat1 & sgint->imask1;
|
||||
u8 mask2;
|
||||
|
@ -254,19 +253,18 @@ static void indy_local1_irqdispatch(struct pt_regs *regs)
|
|||
|
||||
/* if irq == 0, then the interrupt has already been cleared */
|
||||
if (irq)
|
||||
do_IRQ(irq, regs);
|
||||
return;
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
extern void ip22_be_interrupt(int irq, struct pt_regs *regs);
|
||||
extern void ip22_be_interrupt(int irq);
|
||||
|
||||
static void indy_buserror_irq(struct pt_regs *regs)
|
||||
static void indy_buserror_irq(void)
|
||||
{
|
||||
int irq = SGI_BUSERR_IRQ;
|
||||
|
||||
irq_enter();
|
||||
kstat_this_cpu.irqs[irq]++;
|
||||
ip22_be_interrupt(irq, regs);
|
||||
ip22_be_interrupt(irq);
|
||||
irq_exit();
|
||||
}
|
||||
|
||||
|
@ -305,8 +303,8 @@ static struct irqaction map1_cascade = {
|
|||
#define SGI_INTERRUPTS SGINT_LOCAL3
|
||||
#endif
|
||||
|
||||
extern void indy_r4k_timer_interrupt(struct pt_regs *regs);
|
||||
extern void indy_8254timer_irq(struct pt_regs *regs);
|
||||
extern void indy_r4k_timer_interrupt(void);
|
||||
extern void indy_8254timer_irq(void);
|
||||
|
||||
/*
|
||||
* IRQs on the INDY look basically (barring software IRQs which we don't use
|
||||
|
@ -336,7 +334,7 @@ extern void indy_8254timer_irq(struct pt_regs *regs);
|
|||
* another exception, big deal.
|
||||
*/
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause();
|
||||
|
||||
|
@ -344,15 +342,15 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
* First we check for r4k counter/timer IRQ.
|
||||
*/
|
||||
if (pending & CAUSEF_IP7)
|
||||
indy_r4k_timer_interrupt(regs);
|
||||
indy_r4k_timer_interrupt();
|
||||
else if (pending & CAUSEF_IP2)
|
||||
indy_local0_irqdispatch(regs);
|
||||
indy_local0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP3)
|
||||
indy_local1_irqdispatch(regs);
|
||||
indy_local1_irqdispatch();
|
||||
else if (pending & CAUSEF_IP6)
|
||||
indy_buserror_irq(regs);
|
||||
indy_buserror_irq();
|
||||
else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
|
||||
indy_8254timer_irq(regs);
|
||||
indy_8254timer_irq();
|
||||
}
|
||||
|
||||
extern void mips_cpu_irq_init(unsigned int irq_base);
|
||||
|
|
|
@ -175,7 +175,7 @@ static __init void indy_time_init(void)
|
|||
}
|
||||
|
||||
/* Generic SGI handler for (spurious) 8254 interrupts */
|
||||
void indy_8254timer_irq(struct pt_regs *regs)
|
||||
void indy_8254timer_irq(void)
|
||||
{
|
||||
int irq = SGI_8254_0_IRQ;
|
||||
ULONG cnt;
|
||||
|
@ -189,16 +189,14 @@ void indy_8254timer_irq(struct pt_regs *regs)
|
|||
irq_exit();
|
||||
}
|
||||
|
||||
void indy_r4k_timer_interrupt(struct pt_regs *regs)
|
||||
void indy_r4k_timer_interrupt(void)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
int irq = SGI_TIMER_IRQ;
|
||||
|
||||
irq_enter();
|
||||
kstat_this_cpu.irqs[irq]++;
|
||||
timer_interrupt(irq, NULL);
|
||||
irq_exit();
|
||||
set_irq_regs(old_regs);
|
||||
}
|
||||
|
||||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
|
|
|
@ -129,7 +129,7 @@ static int ms1bit(unsigned long x)
|
|||
* Kanoj 05.13.00
|
||||
*/
|
||||
|
||||
static void ip27_do_irq_mask0(struct pt_regs *regs)
|
||||
static void ip27_do_irq_mask0(void)
|
||||
{
|
||||
int irq, swlevel;
|
||||
hubreg_t pend0, mask0;
|
||||
|
@ -164,13 +164,13 @@ static void ip27_do_irq_mask0(struct pt_regs *regs)
|
|||
struct slice_data *si = cpu_data[cpu].data;
|
||||
|
||||
irq = si->level_to_irq[swlevel];
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
LOCAL_HUB_L(PI_INT_PEND0);
|
||||
}
|
||||
|
||||
static void ip27_do_irq_mask1(struct pt_regs *regs)
|
||||
static void ip27_do_irq_mask1(void)
|
||||
{
|
||||
int irq, swlevel;
|
||||
hubreg_t pend1, mask1;
|
||||
|
@ -190,17 +190,17 @@ static void ip27_do_irq_mask1(struct pt_regs *regs)
|
|||
/* "map" swlevel to irq */
|
||||
irq = si->level_to_irq[swlevel];
|
||||
LOCAL_HUB_CLR_INTR(swlevel);
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
|
||||
LOCAL_HUB_L(PI_INT_PEND1);
|
||||
}
|
||||
|
||||
static void ip27_prof_timer(struct pt_regs *regs)
|
||||
static void ip27_prof_timer(void)
|
||||
{
|
||||
panic("CPU %d got a profiling interrupt", smp_processor_id());
|
||||
}
|
||||
|
||||
static void ip27_hub_error(struct pt_regs *regs)
|
||||
static void ip27_hub_error(void)
|
||||
{
|
||||
panic("CPU %d got a hub error interrupt", smp_processor_id());
|
||||
}
|
||||
|
@ -418,22 +418,22 @@ int __devinit request_bridge_irq(struct bridge_controller *bc)
|
|||
return irq;
|
||||
}
|
||||
|
||||
extern void ip27_rt_timer_interrupt(struct pt_regs *regs);
|
||||
extern void ip27_rt_timer_interrupt(void);
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned long pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & CAUSEF_IP4)
|
||||
ip27_rt_timer_interrupt(regs);
|
||||
ip27_rt_timer_interrupt();
|
||||
else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */
|
||||
ip27_do_irq_mask0(regs);
|
||||
ip27_do_irq_mask0();
|
||||
else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */
|
||||
ip27_do_irq_mask1(regs);
|
||||
ip27_do_irq_mask1();
|
||||
else if (pending & CAUSEF_IP5)
|
||||
ip27_prof_timer(regs);
|
||||
ip27_prof_timer();
|
||||
else if (pending & CAUSEF_IP6)
|
||||
ip27_hub_error(regs);
|
||||
ip27_hub_error();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -89,7 +89,7 @@ static int set_rtc_mmss(unsigned long nowtime)
|
|||
|
||||
static unsigned int rt_timer_irq;
|
||||
|
||||
void ip27_rt_timer_interrupt(struct pt_regs *regs)
|
||||
void ip27_rt_timer_interrupt(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
int cpuA = cputoslice(cpu) == 0;
|
||||
|
@ -111,7 +111,7 @@ again:
|
|||
if (cpu == 0)
|
||||
do_timer(1);
|
||||
|
||||
update_process_times(user_mode(regs));
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
|
||||
/*
|
||||
* If we have an externally synchronized Linux clock, then update
|
||||
|
|
|
@ -40,8 +40,7 @@ void __init crime_init(void)
|
|||
id, rev, field, (unsigned long) CRIME_BASE);
|
||||
}
|
||||
|
||||
irqreturn_t
|
||||
crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
|
||||
irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
|
||||
{
|
||||
unsigned long stat, addr;
|
||||
int fatal = 0;
|
||||
|
@ -92,8 +91,7 @@ crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
irqreturn_t
|
||||
crime_cpuerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
|
||||
irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
|
||||
{
|
||||
unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
|
||||
unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
|
||||
|
|
|
@ -120,10 +120,8 @@ static void inline flush_mace_bus(void)
|
|||
static DEFINE_SPINLOCK(ip32_irq_lock);
|
||||
|
||||
/* Some initial interrupts to set up */
|
||||
extern irqreturn_t crime_memerr_intr (int irq, void *dev_id,
|
||||
struct pt_regs *regs);
|
||||
extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id,
|
||||
struct pt_regs *regs);
|
||||
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
|
||||
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
|
||||
|
||||
struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
|
||||
CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
|
||||
|
@ -479,7 +477,7 @@ static struct irq_chip ip32_mace_interrupt = {
|
|||
.end = end_mace_irq,
|
||||
};
|
||||
|
||||
static void ip32_unknown_interrupt(struct pt_regs *regs)
|
||||
static void ip32_unknown_interrupt(void)
|
||||
{
|
||||
printk ("Unknown interrupt occurred!\n");
|
||||
printk ("cp0_status: %08x\n", read_c0_status());
|
||||
|
@ -492,7 +490,7 @@ static void ip32_unknown_interrupt(struct pt_regs *regs)
|
|||
printk ("MACE PCI control register: %08x\n", mace->pci.control);
|
||||
|
||||
printk("Register dump:\n");
|
||||
show_regs(regs);
|
||||
show_regs(get_irq_regs());
|
||||
|
||||
printk("Please mail this report to linux-mips@linux-mips.org\n");
|
||||
printk("Spinning...");
|
||||
|
@ -501,7 +499,7 @@ static void ip32_unknown_interrupt(struct pt_regs *regs)
|
|||
|
||||
/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
|
||||
/* change this to loop over all edge-triggered irqs, exception masked out ones */
|
||||
static void ip32_irq0(struct pt_regs *regs)
|
||||
static void ip32_irq0(void)
|
||||
{
|
||||
uint64_t crime_int;
|
||||
int irq = 0;
|
||||
|
@ -516,50 +514,50 @@ static void ip32_irq0(struct pt_regs *regs)
|
|||
}
|
||||
irq++;
|
||||
DBG("*irq %u*\n", irq);
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
static void ip32_irq1(struct pt_regs *regs)
|
||||
static void ip32_irq1(void)
|
||||
{
|
||||
ip32_unknown_interrupt(regs);
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq2(struct pt_regs *regs)
|
||||
static void ip32_irq2(void)
|
||||
{
|
||||
ip32_unknown_interrupt(regs);
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq3(struct pt_regs *regs)
|
||||
static void ip32_irq3(void)
|
||||
{
|
||||
ip32_unknown_interrupt(regs);
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq4(struct pt_regs *regs)
|
||||
static void ip32_irq4(void)
|
||||
{
|
||||
ip32_unknown_interrupt(regs);
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq5(struct pt_regs *regs)
|
||||
static void ip32_irq5(void)
|
||||
{
|
||||
ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs);
|
||||
ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause();
|
||||
|
||||
if (likely(pending & IE_IRQ0))
|
||||
ip32_irq0(regs);
|
||||
ip32_irq0();
|
||||
else if (unlikely(pending & IE_IRQ1))
|
||||
ip32_irq1(regs);
|
||||
ip32_irq1();
|
||||
else if (unlikely(pending & IE_IRQ2))
|
||||
ip32_irq2(regs);
|
||||
ip32_irq2();
|
||||
else if (unlikely(pending & IE_IRQ3))
|
||||
ip32_irq3(regs);
|
||||
ip32_irq3();
|
||||
else if (unlikely(pending & IE_IRQ4))
|
||||
ip32_irq4(regs);
|
||||
ip32_irq4();
|
||||
else if (likely(pending & IE_IRQ5))
|
||||
ip32_irq5(regs);
|
||||
ip32_irq5();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/kernel_stat.h>
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/signal.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
@ -284,8 +285,7 @@ void __init init_bcm1480_irqs(void)
|
|||
}
|
||||
|
||||
|
||||
static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id)
|
||||
{
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
@ -453,7 +453,7 @@ void __init arch_init_irq(void)
|
|||
#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
|
||||
#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
|
||||
|
||||
void bcm1480_kgdb_interrupt(struct pt_regs *regs)
|
||||
static void bcm1480_kgdb_interrupt(void)
|
||||
{
|
||||
/*
|
||||
* Clear break-change status (allow some time for the remote
|
||||
|
@ -464,16 +464,15 @@ void bcm1480_kgdb_interrupt(struct pt_regs *regs)
|
|||
mdelay(500);
|
||||
duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
|
||||
M_DUART_RX_EN | M_DUART_TX_EN);
|
||||
set_async_breakpoint(®s->cp0_epc);
|
||||
set_async_breakpoint(&get_irq_regs()->cp0_epc);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_KGDB */
|
||||
|
||||
extern void bcm1480_timer_interrupt(struct pt_regs *regs);
|
||||
extern void bcm1480_mailbox_interrupt(struct pt_regs *regs);
|
||||
extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
|
||||
extern void bcm1480_timer_interrupt(void);
|
||||
extern void bcm1480_mailbox_interrupt(void);
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending;
|
||||
|
||||
|
@ -486,21 +485,21 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
#ifdef CONFIG_SIBYTE_BCM1480_PROF
|
||||
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
|
||||
sbprof_cpu_intr(exception_epc(regs));
|
||||
sbprof_cpu_intr();
|
||||
else
|
||||
#endif
|
||||
|
||||
if (pending & CAUSEF_IP4)
|
||||
bcm1480_timer_interrupt(regs);
|
||||
bcm1480_timer_interrupt();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
else if (pending & CAUSEF_IP3)
|
||||
bcm1480_mailbox_interrupt(regs);
|
||||
bcm1480_mailbox_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
else if (pending & CAUSEF_IP6)
|
||||
bcm1480_kgdb_interrupt(regs); /* KGDB (uart 1) */
|
||||
bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
|
||||
#endif
|
||||
|
||||
else if (pending & CAUSEF_IP2) {
|
||||
|
@ -521,9 +520,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
if (mask_h) {
|
||||
if (mask_h ^ 1)
|
||||
do_IRQ(fls64(mask_h) - 1, regs);
|
||||
do_IRQ(fls64(mask_h) - 1);
|
||||
else
|
||||
do_IRQ(63 + fls64(mask_l), regs);
|
||||
do_IRQ(63 + fls64(mask_l));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -88,7 +88,7 @@ void core_send_ipi(int cpu, unsigned int action)
|
|||
__raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
|
||||
}
|
||||
|
||||
void bcm1480_mailbox_interrupt(struct pt_regs *regs)
|
||||
void bcm1480_mailbox_interrupt(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
unsigned int action;
|
||||
|
|
|
@ -100,10 +100,10 @@ void bcm1480_time_init(void)
|
|||
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
|
||||
void bcm1480_timer_interrupt(struct pt_regs *regs)
|
||||
void bcm1480_timer_interrupt(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
int irq = K_BCM1480_INT_TIMER_0+cpu;
|
||||
int irq = K_BCM1480_INT_TIMER_0 + cpu;
|
||||
|
||||
/* Reset the timer */
|
||||
__raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
|
||||
|
@ -113,13 +113,13 @@ void bcm1480_timer_interrupt(struct pt_regs *regs)
|
|||
/*
|
||||
* CPU 0 handles the global timer interrupt job
|
||||
*/
|
||||
ll_timer_interrupt(irq, regs);
|
||||
ll_timer_interrupt(irq);
|
||||
}
|
||||
else {
|
||||
/*
|
||||
* other CPUs should just do profiling and process accounting
|
||||
*/
|
||||
ll_local_timer_interrupt(irq, regs);
|
||||
ll_local_timer_interrupt(irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -254,8 +254,7 @@ void __init init_sb1250_irqs(void)
|
|||
}
|
||||
|
||||
|
||||
static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id)
|
||||
{
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
@ -403,7 +402,7 @@ void __init arch_init_irq(void)
|
|||
#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
|
||||
#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
|
||||
|
||||
static void sb1250_kgdb_interrupt(struct pt_regs *regs)
|
||||
static void sb1250_kgdb_interrupt(void)
|
||||
{
|
||||
/*
|
||||
* Clear break-change status (allow some time for the remote
|
||||
|
@ -414,16 +413,15 @@ static void sb1250_kgdb_interrupt(struct pt_regs *regs)
|
|||
mdelay(500);
|
||||
duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
|
||||
M_DUART_RX_EN | M_DUART_TX_EN);
|
||||
set_async_breakpoint(®s->cp0_epc);
|
||||
set_async_breakpoint(&get_irq_regs()->cp0_epc);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_KGDB */
|
||||
|
||||
extern void sb1250_timer_interrupt(struct pt_regs *regs);
|
||||
extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
|
||||
extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
|
||||
extern void sb1250_timer_interrupt(void);
|
||||
extern void sb1250_mailbox_interrupt(void);
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending;
|
||||
|
||||
|
@ -446,21 +444,21 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
#ifdef CONFIG_SIBYTE_SB1250_PROF
|
||||
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
|
||||
sbprof_cpu_intr(exception_epc(regs));
|
||||
sbprof_cpu_intr();
|
||||
else
|
||||
#endif
|
||||
|
||||
if (pending & CAUSEF_IP4)
|
||||
sb1250_timer_interrupt(regs);
|
||||
sb1250_timer_interrupt();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
else if (pending & CAUSEF_IP3)
|
||||
sb1250_mailbox_interrupt(regs);
|
||||
sb1250_mailbox_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
|
||||
sb1250_kgdb_interrupt(regs);
|
||||
sb1250_kgdb_interrupt();
|
||||
#endif
|
||||
|
||||
else if (pending & CAUSEF_IP2) {
|
||||
|
@ -475,9 +473,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
|
||||
R_IMR_INTERRUPT_STATUS_BASE)));
|
||||
if (mask)
|
||||
do_IRQ(fls64(mask) - 1, regs);
|
||||
do_IRQ(fls64(mask) - 1);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
} else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
|
|
@ -76,7 +76,7 @@ void core_send_ipi(int cpu, unsigned int action)
|
|||
__raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
|
||||
}
|
||||
|
||||
void sb1250_mailbox_interrupt(struct pt_regs *regs)
|
||||
void sb1250_mailbox_interrupt(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
unsigned int action;
|
||||
|
|
|
@ -125,7 +125,7 @@ void sb1250_time_init(void)
|
|||
*/
|
||||
}
|
||||
|
||||
void sb1250_timer_interrupt(struct pt_regs *regs)
|
||||
void sb1250_timer_interrupt(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
int irq = K_INT_TIMER_0 + cpu;
|
||||
|
@ -138,13 +138,13 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
|
|||
/*
|
||||
* CPU 0 handles the global timer interrupt job
|
||||
*/
|
||||
ll_timer_interrupt(irq, regs);
|
||||
ll_timer_interrupt(irq);
|
||||
}
|
||||
else {
|
||||
/*
|
||||
* other CPUs should just do profiling and process accounting
|
||||
*/
|
||||
ll_local_timer_interrupt(irq, regs);
|
||||
ll_local_timer_interrupt(irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -69,20 +69,20 @@ static struct irq_chip pciasic_irq_type = {
|
|||
* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
|
||||
* button interrupts. Later ...
|
||||
*/
|
||||
static void pciasic_hwint0(struct pt_regs *regs)
|
||||
static void pciasic_hwint0(void)
|
||||
{
|
||||
panic("Received int0 but no handler yet ...");
|
||||
}
|
||||
|
||||
/* This interrupt was used for the com1 console on the first prototypes. */
|
||||
static void pciasic_hwint2(struct pt_regs *regs)
|
||||
static void pciasic_hwint2(void)
|
||||
{
|
||||
/* I think this shouldn't happen on production machines. */
|
||||
panic("hwint2 and no handler yet");
|
||||
}
|
||||
|
||||
/* hwint5 is the r4k count / compare interrupt */
|
||||
static void pciasic_hwint5(struct pt_regs *regs)
|
||||
static void pciasic_hwint5(void)
|
||||
{
|
||||
panic("hwint5 and no handler yet");
|
||||
}
|
||||
|
@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
|
|||
*
|
||||
* The EISA_INT bit in CSITPEND is high active, all others are low active.
|
||||
*/
|
||||
static void pciasic_hwint1(struct pt_regs *regs)
|
||||
static void pciasic_hwint1(void)
|
||||
{
|
||||
u8 pend = *(volatile char *)PCIMT_CSITPEND;
|
||||
unsigned long flags;
|
||||
|
@ -119,13 +119,13 @@ static void pciasic_hwint1(struct pt_regs *regs)
|
|||
if (unlikely(irq < 0))
|
||||
return;
|
||||
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
if (!(pend & IT_SCSI)) {
|
||||
flags = read_c0_status();
|
||||
clear_c0_status(ST0_IM);
|
||||
do_IRQ(PCIMT_IRQ_SCSI, regs);
|
||||
do_IRQ(PCIMT_IRQ_SCSI);
|
||||
write_c0_status(flags);
|
||||
}
|
||||
}
|
||||
|
@ -133,7 +133,7 @@ static void pciasic_hwint1(struct pt_regs *regs)
|
|||
/*
|
||||
* hwint 3 should deal with the PCI A - D interrupts,
|
||||
*/
|
||||
static void pciasic_hwint3(struct pt_regs *regs)
|
||||
static void pciasic_hwint3(void)
|
||||
{
|
||||
u8 pend = *(volatile char *)PCIMT_CSITPEND;
|
||||
int irq;
|
||||
|
@ -141,21 +141,21 @@ static void pciasic_hwint3(struct pt_regs *regs)
|
|||
pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
|
||||
clear_c0_status(IE_IRQ3);
|
||||
irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
set_c0_status(IE_IRQ3);
|
||||
}
|
||||
|
||||
/*
|
||||
* hwint 4 is used for only the onboard PCnet 32.
|
||||
*/
|
||||
static void pciasic_hwint4(struct pt_regs *regs)
|
||||
static void pciasic_hwint4(void)
|
||||
{
|
||||
clear_c0_status(IE_IRQ4);
|
||||
do_IRQ(PCIMT_IRQ_ETHERNET, regs);
|
||||
do_IRQ(PCIMT_IRQ_ETHERNET);
|
||||
set_c0_status(IE_IRQ4);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
static unsigned char led_cache;
|
||||
|
@ -163,17 +163,17 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
*(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
|
||||
|
||||
if (pending & 0x0800)
|
||||
pciasic_hwint1(regs);
|
||||
pciasic_hwint1();
|
||||
else if (pending & 0x4000)
|
||||
pciasic_hwint4(regs);
|
||||
pciasic_hwint4();
|
||||
else if (pending & 0x2000)
|
||||
pciasic_hwint3(regs);
|
||||
pciasic_hwint3();
|
||||
else if (pending & 0x1000)
|
||||
pciasic_hwint2(regs);
|
||||
pciasic_hwint2();
|
||||
else if (pending & 0x8000)
|
||||
pciasic_hwint5(regs);
|
||||
pciasic_hwint5();
|
||||
else if (pending & 0x0400)
|
||||
pciasic_hwint0(regs);
|
||||
pciasic_hwint0();
|
||||
}
|
||||
|
||||
void __init init_pciasic(void)
|
||||
|
|
|
@ -576,24 +576,24 @@ static int tx4927_irq_nested(void)
|
|||
return (sw_irq);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & STATUSF_IP7) /* cpu timer */
|
||||
do_IRQ(TX4927_IRQ_CPU_TIMER, regs);
|
||||
do_IRQ(TX4927_IRQ_CPU_TIMER);
|
||||
else if (pending & STATUSF_IP2) { /* tx4927 pic */
|
||||
unsigned int irq = tx4927_irq_nested();
|
||||
|
||||
if (unlikely(irq == 0)) {
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
return;
|
||||
}
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
} else if (pending & STATUSF_IP0) /* user line 0 */
|
||||
do_IRQ(TX4927_IRQ_USER0, regs);
|
||||
do_IRQ(TX4927_IRQ_USER0);
|
||||
else if (pending & STATUSF_IP1) /* user line 1 */
|
||||
do_IRQ(TX4927_IRQ_USER1, regs);
|
||||
do_IRQ(TX4927_IRQ_USER1);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
|
|
@ -58,6 +58,7 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/reboot.h>
|
||||
|
@ -160,8 +161,7 @@ int tx4927_pci66 = 0; /* 0:auto */
|
|||
char *toshiba_name = "";
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static void tx4927_pcierr_interrupt(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
static void tx4927_pcierr_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
#ifdef CONFIG_BLK_DEV_IDEPCI
|
||||
/* ignore MasterAbort for ide probing... */
|
||||
|
@ -185,7 +185,7 @@ static void tx4927_pcierr_interrupt(int irq, void *dev_id,
|
|||
(unsigned long) tx4927_ccfgptr->ccfg,
|
||||
(unsigned long) (tx4927_ccfgptr->tear >> 32),
|
||||
(unsigned long) tx4927_ccfgptr->tear);
|
||||
show_regs(regs);
|
||||
show_regs(get_irq_regs());
|
||||
}
|
||||
|
||||
void __init toshiba_rbtx4927_pci_irq_init(void)
|
||||
|
|
|
@ -104,8 +104,6 @@ tx4938_irq_cp0_init(void)
|
|||
irq_desc[i].depth = 1;
|
||||
irq_desc[i].chip = &tx4938_irq_cp0_type;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
|
@ -113,7 +111,7 @@ tx4938_irq_cp0_startup(unsigned int irq)
|
|||
{
|
||||
tx4938_irq_cp0_enable(irq);
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -144,16 +142,12 @@ tx4938_irq_cp0_disable(unsigned int irq)
|
|||
clear_c0_status(tx4938_irq_cp0_mask(irq));
|
||||
|
||||
spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
tx4938_irq_cp0_mask_and_ack(unsigned int irq)
|
||||
{
|
||||
tx4938_irq_cp0_disable(irq);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -162,8 +156,6 @@ tx4938_irq_cp0_end(unsigned int irq)
|
|||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
|
||||
tx4938_irq_cp0_enable(irq);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**********************************************************************************/
|
||||
|
@ -227,7 +219,7 @@ tx4938_irq_pic_addr(int irq)
|
|||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32
|
||||
|
@ -278,7 +270,7 @@ tx4938_irq_pic_mask(int irq)
|
|||
return (0x00000007);
|
||||
}
|
||||
}
|
||||
return (0x00000000);
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -292,8 +284,6 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
|
|||
TX4938_WR(pic_reg, val);
|
||||
mmiowb();
|
||||
TX4938_RD(pic_reg);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void __init
|
||||
|
@ -317,8 +307,6 @@ tx4938_irq_pic_init(void)
|
|||
TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
|
||||
|
||||
spin_unlock_irqrestore(&tx4938_pic_lock, flags);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
|
@ -326,15 +314,13 @@ tx4938_irq_pic_startup(unsigned int irq)
|
|||
{
|
||||
tx4938_irq_pic_enable(irq);
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
tx4938_irq_pic_shutdown(unsigned int irq)
|
||||
{
|
||||
tx4938_irq_pic_disable(irq);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -348,8 +334,6 @@ tx4938_irq_pic_enable(unsigned int irq)
|
|||
tx4938_irq_pic_mask(irq));
|
||||
|
||||
spin_unlock_irqrestore(&tx4938_pic_lock, flags);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -363,16 +347,12 @@ tx4938_irq_pic_disable(unsigned int irq)
|
|||
tx4938_irq_pic_mask(irq), 0);
|
||||
|
||||
spin_unlock_irqrestore(&tx4938_pic_lock, flags);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
tx4938_irq_pic_mask_and_ack(unsigned int irq)
|
||||
{
|
||||
tx4938_irq_pic_disable(irq);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -381,8 +361,6 @@ tx4938_irq_pic_end(unsigned int irq)
|
|||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
|
||||
tx4938_irq_pic_enable(irq);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**********************************************************************************/
|
||||
|
@ -394,8 +372,6 @@ tx4938_irq_init(void)
|
|||
{
|
||||
tx4938_irq_cp0_init();
|
||||
tx4938_irq_pic_init();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int
|
||||
|
@ -417,23 +393,23 @@ tx4938_irq_nested(void)
|
|||
}
|
||||
|
||||
wbflush();
|
||||
return (sw_irq);
|
||||
return sw_irq;
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(TX4938_IRQ_CPU_TIMER, regs);
|
||||
do_IRQ(TX4938_IRQ_CPU_TIMER);
|
||||
else if (pending & STATUSF_IP2) {
|
||||
int irq = tx4938_irq_nested();
|
||||
if (irq)
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
} else if (pending & STATUSF_IP1)
|
||||
do_IRQ(TX4938_IRQ_USER1, regs);
|
||||
do_IRQ(TX4938_IRQ_USER1);
|
||||
else if (pending & STATUSF_IP0)
|
||||
do_IRQ(TX4938_IRQ_USER0, regs);
|
||||
do_IRQ(TX4938_IRQ_USER0);
|
||||
}
|
||||
|
|
|
@ -35,7 +35,8 @@ void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)
|
|||
}
|
||||
|
||||
static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
|
||||
static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
|
||||
static void txx9_spi_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
/* disable rx intr */
|
||||
tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
|
||||
|
|
|
@ -635,7 +635,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
|
|||
|
||||
EXPORT_SYMBOL(vr41xx_set_intassign);
|
||||
|
||||
static int icu_get_irq(unsigned int irq, struct pt_regs *regs)
|
||||
static int icu_get_irq(unsigned int irq)
|
||||
{
|
||||
uint16_t pend1, pend2;
|
||||
uint16_t mask1, mask2;
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
#include <asm/vr41xx/irq.h>
|
||||
|
||||
typedef struct irq_cascade {
|
||||
int (*get_irq)(unsigned int, struct pt_regs *);
|
||||
int (*get_irq)(unsigned int);
|
||||
} irq_cascade_t;
|
||||
|
||||
static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
|
||||
|
@ -36,7 +36,7 @@ static struct irqaction cascade_irqaction = {
|
|||
.name = "cascade",
|
||||
};
|
||||
|
||||
int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *))
|
||||
int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
|
||||
{
|
||||
int retval = 0;
|
||||
|
||||
|
@ -59,7 +59,7 @@ int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)
|
|||
|
||||
EXPORT_SYMBOL_GPL(cascade_irq);
|
||||
|
||||
static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
|
||||
static void irq_dispatch(unsigned int irq)
|
||||
{
|
||||
irq_cascade_t *cascade;
|
||||
struct irq_desc *desc;
|
||||
|
@ -74,39 +74,39 @@ static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
|
|||
unsigned int source_irq = irq;
|
||||
desc = irq_desc + source_irq;
|
||||
desc->chip->ack(source_irq);
|
||||
irq = cascade->get_irq(irq, regs);
|
||||
irq = cascade->get_irq(irq);
|
||||
if (irq < 0)
|
||||
atomic_inc(&irq_err_count);
|
||||
else
|
||||
irq_dispatch(irq, regs);
|
||||
irq_dispatch(irq);
|
||||
desc->chip->end(source_irq);
|
||||
} else
|
||||
do_IRQ(irq, regs);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
do_IRQ(7, regs);
|
||||
do_IRQ(7);
|
||||
else if (pending & 0x7800) {
|
||||
if (pending & CAUSEF_IP3)
|
||||
irq_dispatch(3, regs);
|
||||
irq_dispatch(3);
|
||||
else if (pending & CAUSEF_IP4)
|
||||
irq_dispatch(4, regs);
|
||||
irq_dispatch(4);
|
||||
else if (pending & CAUSEF_IP5)
|
||||
irq_dispatch(5, regs);
|
||||
irq_dispatch(5);
|
||||
else if (pending & CAUSEF_IP6)
|
||||
irq_dispatch(6, regs);
|
||||
irq_dispatch(6);
|
||||
} else if (pending & CAUSEF_IP2)
|
||||
irq_dispatch(2, regs);
|
||||
irq_dispatch(2);
|
||||
else if (pending & CAUSEF_IP0)
|
||||
do_IRQ(0, regs);
|
||||
do_IRQ(0);
|
||||
else if (pending & CAUSEF_IP1)
|
||||
do_IRQ(1, regs);
|
||||
do_IRQ(1);
|
||||
else
|
||||
spurious_interrupt(regs);
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -26,7 +26,7 @@ static inline int irq_canonicalize(int irq)
|
|||
|
||||
struct pt_regs;
|
||||
|
||||
extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
|
||||
extern asmlinkage unsigned int do_IRQ(unsigned int irq);
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
/*
|
||||
|
@ -55,18 +55,18 @@ do { \
|
|||
* Ideally there should be away to get this into kernel/irq/handle.c to
|
||||
* avoid the overhead of a call for just a tiny function ...
|
||||
*/
|
||||
#define do_IRQ(irq, regs) \
|
||||
#define do_IRQ(irq) \
|
||||
do { \
|
||||
irq_enter(); \
|
||||
__DO_IRQ_SMTC_HOOK(); \
|
||||
__do_IRQ((irq), (regs)); \
|
||||
__do_IRQ((irq)); \
|
||||
irq_exit(); \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
extern void arch_init_irq(void);
|
||||
extern void spurious_interrupt(struct pt_regs *regs);
|
||||
extern void spurious_interrupt(void);
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
struct irqaction;
|
||||
|
|
|
@ -1 +1,21 @@
|
|||
#include <asm-generic/irq_regs.h>
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#ifndef __ASM_IRQ_REGS_H
|
||||
#define __ASM_IRQ_REGS_H
|
||||
|
||||
#define ARCH_HAS_OWN_IRQ_REGS
|
||||
|
||||
#include <linux/thread_info.h>
|
||||
|
||||
static inline struct pt_regs *get_irq_regs(void)
|
||||
{
|
||||
return current_thread_info()->regs;
|
||||
}
|
||||
|
||||
#endif /* __ASM_IRQ_REGS_H */
|
||||
|
|
|
@ -45,10 +45,6 @@ extern int
|
|||
toshibaboards_setup_irq(int irq, struct irqaction * new);
|
||||
|
||||
|
||||
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
|
||||
extern void tx_branch_likely_bug_fixup(struct pt_regs *regs);
|
||||
#endif
|
||||
|
||||
extern int (*toshibaboards_gen_iack)(void);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
|
|
@ -123,8 +123,7 @@ struct dma_chan {
|
|||
extern struct dma_chan au1000_dma_table[];
|
||||
extern int request_au1000_dma(int dev_id,
|
||||
const char *dev_str,
|
||||
irqreturn_t (*irqhandler)(int, void *,
|
||||
struct pt_regs *),
|
||||
irqreturn_t (*irqhandler)(int, void *),
|
||||
unsigned long irqflags,
|
||||
void *irq_dev_id);
|
||||
extern void free_au1000_dma(unsigned int dmanr);
|
||||
|
|
|
@ -53,6 +53,6 @@ struct mv_pci_controller {
|
|||
unsigned long config_vreg;
|
||||
};
|
||||
|
||||
extern void ll_mv64340_irq(struct pt_regs *regs);
|
||||
extern void ll_mv64340_irq(void);
|
||||
|
||||
#endif /* __ASM_MIPS_MARVELL_H */
|
||||
|
|
|
@ -145,7 +145,7 @@ typedef struct msc_irqmap {
|
|||
#define MSC01_IRQ_EDGE 1
|
||||
|
||||
extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
|
||||
extern void ll_msc_irq(struct pt_regs *regs);
|
||||
extern void ll_msc_irq(void);
|
||||
|
||||
#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
|
||||
|
||||
|
|
|
@ -34,6 +34,7 @@ struct thread_info {
|
|||
0-0xFFFFFFFF for kernel-thread
|
||||
*/
|
||||
struct restart_block restart_block;
|
||||
struct pt_regs *regs;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -72,13 +72,13 @@ extern irqreturn_t timer_interrupt(int irq, void *dev_id);
|
|||
/*
|
||||
* the corresponding low-level timer interrupt routine.
|
||||
*/
|
||||
extern asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs);
|
||||
extern asmlinkage void ll_timer_interrupt(int irq);
|
||||
|
||||
/*
|
||||
* profiling and process accouting is done separately in local_timer_interrupt
|
||||
*/
|
||||
extern void local_timer_interrupt(int irq, void *dev_id);
|
||||
extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
|
||||
extern asmlinkage void ll_local_timer_interrupt(int irq);
|
||||
|
||||
/*
|
||||
* board specific routines required by time_init().
|
||||
|
|
Загрузка…
Ссылка в новой задаче