Allwinner clock additions for 4.4
- Support for the Audio PLL and child clocks - Support for the A33 AHB gates - New clk-multiplier generic driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWJ+3uAAoJEBx+YmzsjxAgx8UP/2QOntzRCUQYZGaI/aG2Pcag lWeoWRkHpEdjM288OxOgoqody6UU/5gecI2UgDLtziaXV5DfIFhP0Klq1gIYc7h0 WDts2IlGht+fIObL87mD0Pm9StFNAtxFe5tKoHpU5oS6NP+lowSWAQlZSgUWdQky VEvXDcOtaEQ3UQgcuMsaqfzgRPJC9zz28MDF28EtPhnCeseb/LKdmvaGzxHHehSl 016mQ4DvNC92PeLXUdy3LLOkcHTfYnH1OUBPrv7u8bFU09zPKSimymDyL87D7FFM vPGKtlD/cQb21z2OVK9GKNmd9dQ+8tnBn9Gbdem95LFHlhP/m+SJbW2P64dNVq0A QK5Ria2H6ccRMpfjNQ4zCHjIJQ6+z9xRzIlHXeAT7PcBf9XNwn1/N7qSBJTRy+y/ uq9Wvgfuletk9lIiFstbJWT6Axu+w/QVWJwJSkOa63elkFSyz+9Dk88MDYd156or R79fc9EMQFcCg7k5IeiePLV8G1XVHc/3+ZoRON2ZJYk0L3z5uv/klizkCwtWN5cN 55nzfQ8Mn69yG9vrR7DSbVY4eyXkr345Tqv0OFaDZlrpb9/oHjK6MNDWzmXY2Y+N ZcdNXwWu8DOqEf2iPWXETp0R0wV3kuEaKOvkS4KpvK2UjdQUeEvGUbpxm7Omo583 5RN+z/gjJSZQx9AoGwBJ =WtVW -----END PGP SIGNATURE----- Merge tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock additions for 4.4 from Maxime Ripard: - Support for the Audio PLL and child clocks - Support for the A33 AHB gates - New clk-multiplier generic driver * tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: mod1 clock support clk: sunxi: codec clock support clk: sunxi: pll2: Add A13 support clk: sunxi: Add a driver for the PLL2 clk: Add a basic multiplier clock clk: sunxi: Add A33 gates support
This commit is contained in:
Stephen Boyd
Коммит
938ce30e29
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@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-divider.o
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obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
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obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
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obj-$(CONFIG_COMMON_CLK) += clk-gate.o
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obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
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obj-$(CONFIG_COMMON_CLK) += clk-mux.o
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obj-$(CONFIG_COMMON_CLK) += clk-composite.o
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obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
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@ -0,0 +1,181 @@
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/*
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* Copyright (C) 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
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static unsigned long __get_mult(struct clk_multiplier *mult,
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unsigned long rate,
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unsigned long parent_rate)
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{
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if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST)
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return DIV_ROUND_CLOSEST(rate, parent_rate);
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return rate / parent_rate;
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}
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static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_multiplier *mult = to_clk_multiplier(hw);
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unsigned long val;
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val = clk_readl(mult->reg) >> mult->shift;
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val &= GENMASK(mult->width - 1, 0);
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if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
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val = 1;
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return parent_rate * val;
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}
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static bool __is_best_rate(unsigned long rate, unsigned long new,
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unsigned long best, unsigned long flags)
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{
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if (flags & CLK_MULTIPLIER_ROUND_CLOSEST)
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return abs(rate - new) < abs(rate - best);
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return new >= rate && new < best;
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}
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static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate,
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u8 width, unsigned long flags)
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{
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unsigned long orig_parent_rate = *best_parent_rate;
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unsigned long parent_rate, current_rate, best_rate = ~0;
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unsigned int i, bestmult = 0;
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))
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return rate / *best_parent_rate;
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for (i = 1; i < ((1 << width) - 1); i++) {
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if (rate == orig_parent_rate * i) {
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/*
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* This is the best case for us if we have a
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* perfect match without changing the parent
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* rate.
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*/
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*best_parent_rate = orig_parent_rate;
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return i;
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}
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parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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rate / i);
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current_rate = parent_rate * i;
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if (__is_best_rate(rate, current_rate, best_rate, flags)) {
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bestmult = i;
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best_rate = current_rate;
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*best_parent_rate = parent_rate;
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}
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}
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return bestmult;
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}
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static long clk_multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_multiplier *mult = to_clk_multiplier(hw);
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unsigned long factor = __bestmult(hw, rate, parent_rate,
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mult->width, mult->flags);
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return *parent_rate * factor;
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}
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static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_multiplier *mult = to_clk_multiplier(hw);
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unsigned long factor = __get_mult(mult, rate, parent_rate);
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unsigned long flags = 0;
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unsigned long val;
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if (mult->lock)
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spin_lock_irqsave(mult->lock, flags);
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else
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__acquire(mult->lock);
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val = clk_readl(mult->reg);
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val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);
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val |= factor << mult->shift;
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clk_writel(val, mult->reg);
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if (mult->lock)
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spin_unlock_irqrestore(mult->lock, flags);
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else
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__release(mult->lock);
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return 0;
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}
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const struct clk_ops clk_multiplier_ops = {
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.recalc_rate = clk_multiplier_recalc_rate,
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.round_rate = clk_multiplier_round_rate,
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.set_rate = clk_multiplier_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_multiplier_ops);
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struct clk *clk_register_multiplier(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mult_flags, spinlock_t *lock)
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{
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struct clk_init_data init;
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struct clk_multiplier *mult;
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struct clk *clk;
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mult = kmalloc(sizeof(*mult), GFP_KERNEL);
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if (!mult)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_multiplier_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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mult->reg = reg;
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mult->shift = shift;
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mult->width = width;
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mult->flags = clk_mult_flags;
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mult->lock = lock;
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mult->hw.init = &init;
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clk = clk_register(dev, &mult->hw);
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if (IS_ERR(clk))
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kfree(mult);
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return clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_multiplier);
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void clk_unregister_multiplier(struct clk *clk)
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{
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struct clk_multiplier *mult;
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struct clk_hw *hw;
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hw = __clk_get_hw(clk);
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if (!hw)
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return;
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mult = to_clk_multiplier(hw);
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clk_unregister(clk);
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kfree(mult);
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}
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EXPORT_SYMBOL_GPL(clk_unregister_multiplier);
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@ -3,7 +3,10 @@
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#
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-codec.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a10-mod1.o
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obj-y += clk-a10-pll2.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-simple-gates.o
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@ -0,0 +1,44 @@
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/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define SUN4I_CODEC_GATE 31
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static void __init sun4i_codec_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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const char *clk_name = node->name, *parent_name;
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent_name = of_clk_get_parent_name(node, 0);
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clk = clk_register_gate(NULL, clk_name, parent_name,
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CLK_SET_RATE_PARENT, reg,
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SUN4I_CODEC_GATE, 0, NULL);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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CLK_OF_DECLARE(sun4i_codec, "allwinner,sun4i-a10-codec-clk",
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sun4i_codec_clk_setup);
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@ -0,0 +1,81 @@
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/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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static DEFINE_SPINLOCK(mod1_lock);
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#define SUN4I_MOD1_ENABLE 31
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#define SUN4I_MOD1_MUX 16
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#define SUN4I_MOD1_MUX_WIDTH 2
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#define SUN4I_MOD1_MAX_PARENTS 4
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static void __init sun4i_mod1_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_mux *mux;
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struct clk_gate *gate;
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const char *parents[4];
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const char *clk_name = node->name;
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void __iomem *reg;
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int i;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto err_unmap;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto err_free_mux;
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of_property_read_string(node, "clock-output-names", &clk_name);
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i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
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gate->reg = reg;
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gate->bit_idx = SUN4I_MOD1_ENABLE;
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gate->lock = &mod1_lock;
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mux->reg = reg;
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mux->shift = SUN4I_MOD1_MUX;
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mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
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mux->lock = &mod1_lock;
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clk = clk_register_composite(NULL, clk_name, parents, i,
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&mux->hw, &clk_mux_ops,
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NULL, NULL,
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&gate->hw, &clk_gate_ops, 0);
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if (IS_ERR(clk))
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goto err_free_gate;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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err_free_gate:
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kfree(gate);
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err_free_mux:
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kfree(mux);
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err_unmap:
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iounmap(reg);
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}
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CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",
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sun4i_mod1_clk_setup);
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|
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@ -0,0 +1,216 @@
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/*
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* Copyright 2013 Emilio López
|
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* Emilio López <emilio@elopez.com.ar>
|
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*
|
||||
* Copyright 2015 Maxime Ripard
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
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#include <linux/slab.h>
|
||||
|
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#include <dt-bindings/clock/sun4i-a10-pll2.h>
|
||||
|
||||
#define SUN4I_PLL2_ENABLE 31
|
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|
||||
#define SUN4I_PLL2_PRE_DIV_SHIFT 0
|
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#define SUN4I_PLL2_PRE_DIV_WIDTH 5
|
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#define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
|
||||
|
||||
#define SUN4I_PLL2_N_SHIFT 8
|
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#define SUN4I_PLL2_N_WIDTH 7
|
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#define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
|
||||
|
||||
#define SUN4I_PLL2_POST_DIV_SHIFT 26
|
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#define SUN4I_PLL2_POST_DIV_WIDTH 4
|
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#define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
|
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|
||||
#define SUN4I_PLL2_POST_DIV_VALUE 4
|
||||
|
||||
#define SUN4I_PLL2_OUTPUTS 4
|
||||
|
||||
struct sun4i_pll2_data {
|
||||
u32 post_div_offset;
|
||||
u32 pre_div_flags;
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
|
||||
|
||||
static void __init sun4i_pll2_setup(struct device_node *node,
|
||||
struct sun4i_pll2_data *data)
|
||||
{
|
||||
const char *clk_name = node->name, *parent;
|
||||
struct clk **clks, *base_clk, *prediv_clk;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_multiplier *mult;
|
||||
struct clk_gate *gate;
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
||||
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(reg))
|
||||
return;
|
||||
|
||||
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
goto err_unmap;
|
||||
|
||||
clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clks)
|
||||
goto err_free_data;
|
||||
|
||||
parent = of_clk_get_parent_name(node, 0);
|
||||
prediv_clk = clk_register_divider(NULL, "pll2-prediv",
|
||||
parent, 0, reg,
|
||||
SUN4I_PLL2_PRE_DIV_SHIFT,
|
||||
SUN4I_PLL2_PRE_DIV_WIDTH,
|
||||
data->pre_div_flags,
|
||||
&sun4i_a10_pll2_lock);
|
||||
if (!prediv_clk) {
|
||||
pr_err("Couldn't register the prediv clock\n");
|
||||
goto err_free_array;
|
||||
}
|
||||
|
||||
/* Setup the gate part of the PLL2 */
|
||||
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
goto err_unregister_prediv;
|
||||
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = SUN4I_PLL2_ENABLE;
|
||||
gate->lock = &sun4i_a10_pll2_lock;
|
||||
|
||||
/* Setup the multiplier part of the PLL2 */
|
||||
mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
|
||||
if (!mult)
|
||||
goto err_free_gate;
|
||||
|
||||
mult->reg = reg;
|
||||
mult->shift = SUN4I_PLL2_N_SHIFT;
|
||||
mult->width = 7;
|
||||
mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
|
||||
CLK_MULTIPLIER_ROUND_CLOSEST;
|
||||
mult->lock = &sun4i_a10_pll2_lock;
|
||||
|
||||
parent = __clk_get_name(prediv_clk);
|
||||
base_clk = clk_register_composite(NULL, "pll2-base",
|
||||
&parent, 1,
|
||||
NULL, NULL,
|
||||
&mult->hw, &clk_multiplier_ops,
|
||||
&gate->hw, &clk_gate_ops,
|
||||
CLK_SET_RATE_PARENT);
|
||||
if (!base_clk) {
|
||||
pr_err("Couldn't register the base multiplier clock\n");
|
||||
goto err_free_multiplier;
|
||||
}
|
||||
|
||||
parent = __clk_get_name(base_clk);
|
||||
|
||||
/*
|
||||
* PLL2-1x
|
||||
*
|
||||
* This is supposed to have a post divider, but we won't need
|
||||
* to use it, we just need to initialise it to 4, and use a
|
||||
* fixed divider.
|
||||
*/
|
||||
val = readl(reg);
|
||||
val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
|
||||
val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
|
||||
writel(val, reg);
|
||||
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
SUN4I_A10_PLL2_1X, &clk_name);
|
||||
clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
|
||||
parent,
|
||||
CLK_SET_RATE_PARENT,
|
||||
1,
|
||||
SUN4I_PLL2_POST_DIV_VALUE);
|
||||
WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
|
||||
|
||||
/*
|
||||
* PLL2-2x
|
||||
*
|
||||
* This clock doesn't use the post divider, and really is just
|
||||
* a fixed divider from the PLL2 base clock.
|
||||
*/
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
SUN4I_A10_PLL2_2X, &clk_name);
|
||||
clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
|
||||
parent,
|
||||
CLK_SET_RATE_PARENT,
|
||||
1, 2);
|
||||
WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
|
||||
|
||||
/* PLL2-4x */
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
SUN4I_A10_PLL2_4X, &clk_name);
|
||||
clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
|
||||
parent,
|
||||
CLK_SET_RATE_PARENT,
|
||||
1, 1);
|
||||
WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
|
||||
|
||||
/* PLL2-8x */
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
SUN4I_A10_PLL2_8X, &clk_name);
|
||||
clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
|
||||
parent,
|
||||
CLK_SET_RATE_PARENT,
|
||||
2, 1);
|
||||
WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
|
||||
|
||||
clk_data->clks = clks;
|
||||
clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
|
||||
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
return;
|
||||
|
||||
err_free_multiplier:
|
||||
kfree(mult);
|
||||
err_free_gate:
|
||||
kfree(gate);
|
||||
err_unregister_prediv:
|
||||
clk_unregister_divider(prediv_clk);
|
||||
err_free_array:
|
||||
kfree(clks);
|
||||
err_free_data:
|
||||
kfree(clk_data);
|
||||
err_unmap:
|
||||
iounmap(reg);
|
||||
}
|
||||
|
||||
static struct sun4i_pll2_data sun4i_a10_pll2_data = {
|
||||
.pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||
};
|
||||
|
||||
static void __init sun4i_a10_pll2_setup(struct device_node *node)
|
||||
{
|
||||
sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
|
||||
sun4i_a10_pll2_setup);
|
||||
|
||||
static struct sun4i_pll2_data sun5i_a13_pll2_data = {
|
||||
.post_div_offset = 1,
|
||||
};
|
||||
|
||||
static void __init sun5i_a13_pll2_setup(struct device_node *node)
|
||||
{
|
||||
sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
|
||||
sun5i_a13_pll2_setup);
|
||||
|
|
@ -128,6 +128,8 @@ CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
|
|||
sunxi_simple_gates_init);
|
||||
CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
|
||||
sunxi_simple_gates_init);
|
||||
CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
|
||||
sunxi_simple_gates_init);
|
||||
CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
|
||||
sunxi_simple_gates_init);
|
||||
CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2015 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
|
||||
#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
|
||||
|
||||
#define SUN4I_A10_PLL2_1X 0
|
||||
#define SUN4I_A10_PLL2_2X 1
|
||||
#define SUN4I_A10_PLL2_4X 2
|
||||
#define SUN4I_A10_PLL2_8X 3
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
|
||||
|
|
@ -519,6 +519,48 @@ struct clk *clk_register_fractional_divider(struct device *dev,
|
|||
void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
|
||||
u8 clk_divider_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct clk_multiplier - adjustable multiplier clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register containing the multiplier
|
||||
* @shift: shift to the multiplier bit field
|
||||
* @width: width of the multiplier bit field
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock with an adjustable multiplier affecting its output frequency.
|
||||
* Implements .recalc_rate, .set_rate and .round_rate
|
||||
*
|
||||
* Flags:
|
||||
* CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
|
||||
* from the register, with 0 being a valid value effectively
|
||||
* zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
|
||||
* set, then a null multiplier will be considered as a bypass,
|
||||
* leaving the parent rate unmodified.
|
||||
* CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
|
||||
* rounded to the closest integer instead of the down one.
|
||||
*/
|
||||
struct clk_multiplier {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
|
||||
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
|
||||
|
||||
extern const struct clk_ops clk_multiplier_ops;
|
||||
|
||||
struct clk *clk_register_multiplier(struct device *dev, const char *name,
|
||||
const char *parent_name,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mult_flags, spinlock_t *lock);
|
||||
void clk_unregister_multiplier(struct clk *clk);
|
||||
|
||||
/***
|
||||
* struct clk_composite - aggregate clock of mux, divider and gate clocks
|
||||
*
|
||||
|
|
|
|||
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