drm/radeon/kms: define TMDS/LVTM HDMI enabling bits
The names has been taken from free M76 specs. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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93a4ed878a
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@ -573,6 +573,7 @@
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#define AVIVO_TMDSA_CNTL 0x7880
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# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
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# define AVIVO_TMDSA_CNTL_HDMI_EN (1 << 2)
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# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
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# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
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# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
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@ -633,6 +634,7 @@
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#define AVIVO_LVTMA_CNTL 0x7a80
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# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
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# define AVIVO_LVTMA_CNTL_HDMI_EN (1 << 2)
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# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
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# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
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# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
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@ -533,11 +533,13 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
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} else if (rdev->family >= CHIP_R600) {
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);
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WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
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~AVIVO_TMDSA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0x101);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4);
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WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
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~AVIVO_LVTMA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0x105);
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break;
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default:
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@ -603,11 +605,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
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} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4);
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WREG32_P(AVIVO_TMDSA_CNTL, 0,
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~AVIVO_TMDSA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4);
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WREG32_P(AVIVO_LVTMA_CNTL, 0,
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~AVIVO_LVTMA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0);
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break;
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default:
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