ixgbe: Remove non-inclusive language
Remove non-inclusive language from the driver. Additionally correct the duplication "from from" reported by checkpatch after the changes above. Signed-off-by: Piotr Skajewski <piotrx.skajewski@intel.com> Tested-by: Dave Switzer <david.switzer@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Piotr Skajewski
Tony Nguyen
Родитель
c6fbfdcbce
Коммит
93b067f154
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@ -30,7 +30,7 @@ static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
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u16 offset);
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static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
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static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw);
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/* Base table for registers values that change by MAC */
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const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
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@ -746,10 +746,10 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
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usleep_range(1000, 2000);
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/*
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* Prevent the PCI-E bus from from hanging by disabling PCI-E master
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* Prevent the PCI-E bus from hanging by disabling PCI-E primary
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* access and verify no pending requests
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*/
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return ixgbe_disable_pcie_master(hw);
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return ixgbe_disable_pcie_primary(hw);
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}
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/**
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@ -2506,15 +2506,15 @@ static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
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}
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/**
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* ixgbe_disable_pcie_master - Disable PCI-express master access
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* ixgbe_disable_pcie_primary - Disable PCI-express primary access
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* @hw: pointer to hardware structure
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*
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* Disables PCI-Express master access and verifies there are no pending
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* requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
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* bit hasn't caused the master requests to be disabled, else 0
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* is returned signifying master requests disabled.
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* Disables PCI-Express primary access and verifies there are no pending
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* requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable
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* bit hasn't caused the primary requests to be disabled, else 0
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* is returned signifying primary requests disabled.
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**/
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static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
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static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw)
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{
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u32 i, poll;
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u16 value;
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@ -2523,23 +2523,23 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
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IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
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/* Poll for bit to read as set */
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for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
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for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
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if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
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break;
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usleep_range(100, 120);
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}
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if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) {
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if (i >= IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT) {
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hw_dbg(hw, "GIO disable did not set - requesting resets\n");
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goto gio_disable_fail;
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}
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/* Exit if master requests are blocked */
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/* Exit if primary requests are blocked */
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if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
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ixgbe_removed(hw->hw_addr))
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return 0;
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/* Poll for master request bit to clear */
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for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
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/* Poll for primary request bit to clear */
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for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
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udelay(100);
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if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
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return 0;
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@ -2547,13 +2547,13 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
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/*
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* Two consecutive resets are required via CTRL.RST per datasheet
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* 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
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* of this need. The first reset prevents new master requests from
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* 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine
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* of this need. The first reset prevents new primary requests from
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* being issued by our device. We then must wait 1usec or more for any
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* remaining completions from the PCIe bus to trickle in, and then reset
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* again to clear out any effects they may have had on our device.
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*/
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hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
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hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n");
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gio_disable_fail:
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hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
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@ -2575,7 +2575,7 @@ gio_disable_fail:
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}
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hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
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return IXGBE_ERR_MASTER_REQUESTS_PENDING;
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return IXGBE_ERR_PRIMARY_REQUESTS_PENDING;
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}
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/**
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@ -5948,8 +5948,8 @@ void ixgbe_reset(struct ixgbe_adapter *adapter)
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case IXGBE_ERR_SFP_NOT_PRESENT:
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case IXGBE_ERR_SFP_NOT_SUPPORTED:
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break;
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case IXGBE_ERR_MASTER_REQUESTS_PENDING:
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e_dev_err("master disable timed out\n");
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case IXGBE_ERR_PRIMARY_REQUESTS_PENDING:
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e_dev_err("primary disable timed out\n");
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break;
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case IXGBE_ERR_EEPROM_VERSION:
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/* We are running on a pre-production device, log a warning */
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@ -1247,7 +1247,7 @@ struct ixgbe_nvm_version {
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#define IXGBE_PSRTYPE_RQPL_SHIFT 29
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/* CTRL Bit Masks */
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#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
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#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Primary Disable bit */
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#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
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#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
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#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
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@ -1811,7 +1811,7 @@ enum {
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/* STATUS Bit Masks */
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#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
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#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
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#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
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#define IXGBE_STATUS_GIO 0x00080000 /* GIO Primary Enable Status */
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#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
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#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
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@ -2193,8 +2193,8 @@ enum {
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#define IXGBE_PCIDEVCTRL2_4_8s 0xd
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#define IXGBE_PCIDEVCTRL2_17_34s 0xe
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/* Number of 100 microseconds we wait for PCI Express master disable */
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#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
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/* Number of 100 microseconds we wait for PCI Express primary disable */
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#define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT 800
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/* RAH */
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#define IXGBE_RAH_VIND_MASK 0x003C0000
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@ -3671,7 +3671,7 @@ struct ixgbe_info {
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#define IXGBE_ERR_ADAPTER_STOPPED -9
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#define IXGBE_ERR_INVALID_MAC_ADDR -10
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#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
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#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
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#define IXGBE_ERR_PRIMARY_REQUESTS_PENDING -12
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#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
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#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
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#define IXGBE_ERR_RESET_FAILED -15
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