pinctrl: tegra: consistency cleanup
Fix Tegra30/114/124 pinmux drivers consistency issues. * Sort all lists of the same object type (e.g. #defines for pins, and the array that defines their names) in the same order. * Whitespace fixes. * Consistency in layout between the 3 drivers. These driver files were also auto-generated, which should allow us to make e.g. the U-Boot drivers completely consistent with the kernel in the future:-) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Stephen Warren
Linus Walleij
Родитель
ce43625466
Коммит
93cfb2d862
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@ -1,10 +1,8 @@
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/*
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* Pinctrl data and driver for the NVIDIA Tegra114 pinmux
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* Pinctrl data for the NVIDIA Tegra114 pinmux
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*
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Pritesh Raithatha <praithatha@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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@ -13,9 +11,6 @@
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/module.h>
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@ -203,8 +198,8 @@
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#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
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/* All non-GPIO pins follow */
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#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
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#define _PIN(offset) (NUM_GPIOS + (offset))
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#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
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#define _PIN(offset) (NUM_GPIOS + (offset))
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/* Non-GPIO pins */
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#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
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@ -213,7 +208,7 @@
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#define TEGRA_PIN_RESET_OUT_N _PIN(3)
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#define TEGRA_PIN_OWR _PIN(4)
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static const struct pinctrl_pin_desc tegra114_pins[] = {
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static const struct pinctrl_pin_desc tegra114_pins[] = {
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PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
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PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
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PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
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@ -385,9 +380,9 @@ static const struct pinctrl_pin_desc tegra114_pins[] = {
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PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
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PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
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PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
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PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
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PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
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PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
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PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
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};
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static const unsigned clk_32k_out_pa0_pins[] = {
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@ -1074,10 +1069,6 @@ static const unsigned cpu_pwr_req_pins[] = {
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TEGRA_PIN_CPU_PWR_REQ,
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};
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static const unsigned owr_pins[] = {
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TEGRA_PIN_OWR,
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};
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static const unsigned pwr_int_n_pins[] = {
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TEGRA_PIN_PWR_INT_N,
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};
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@ -1086,6 +1077,10 @@ static const unsigned reset_out_n_pins[] = {
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TEGRA_PIN_RESET_OUT_N,
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};
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static const unsigned owr_pins[] = {
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TEGRA_PIN_OWR,
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};
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static const unsigned drive_ao1_pins[] = {
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TEGRA_PIN_KB_ROW0_PR0,
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TEGRA_PIN_KB_ROW1_PR1,
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@ -1127,7 +1122,6 @@ static const unsigned drive_at1_pins[] = {
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TEGRA_PIN_GMI_AD13_PH5,
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TEGRA_PIN_GMI_AD14_PH6,
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TEGRA_PIN_GMI_AD15_PH7,
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TEGRA_PIN_GMI_IORDY_PI5,
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TEGRA_PIN_GMI_CS7_N_PI6,
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};
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@ -1141,15 +1135,12 @@ static const unsigned drive_at2_pins[] = {
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TEGRA_PIN_GMI_AD5_PG5,
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TEGRA_PIN_GMI_AD6_PG6,
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TEGRA_PIN_GMI_AD7_PG7,
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TEGRA_PIN_GMI_WR_N_PI0,
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TEGRA_PIN_GMI_OE_N_PI1,
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TEGRA_PIN_GMI_CS6_N_PI3,
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TEGRA_PIN_GMI_RST_N_PI4,
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TEGRA_PIN_GMI_WAIT_PI7,
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TEGRA_PIN_GMI_DQS_P_PJ3,
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TEGRA_PIN_GMI_ADV_N_PK0,
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TEGRA_PIN_GMI_CLK_PK1,
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TEGRA_PIN_GMI_CS4_N_PK2,
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@ -1425,7 +1416,7 @@ enum tegra_mux {
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.name = #fname, \
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}
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static struct tegra_function tegra114_functions[] = {
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static struct tegra_function tegra114_functions[] = {
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FUNCTION(blink),
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FUNCTION(cec),
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FUNCTION(cldvfs),
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@ -1504,11 +1495,11 @@ static struct tegra_function tegra114_functions[] = {
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FUNCTION(vi_alt3),
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};
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#define DRV_PINGROUP_REG_START 0x868 /* bank 0 */
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#define PINGROUP_REG_START 0x3000 /* bank 1 */
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_START)
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#define PINGROUP_REG_N(r) -1
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#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_REG_N(r) -1
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#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
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{ \
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@ -1550,13 +1541,14 @@ static struct tegra_function tegra114_functions[] = {
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.drvtype_reg = -1, \
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}
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#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_START)
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#define DRV_PINGROUP_DVRTYPE_N(r) -1
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#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
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#define DRV_PINGROUP_REG_N(r) -1
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
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drvdn_b, drvdn_w, drvup_b, drvup_w, \
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slwr_b, slwr_w, slwf_b, slwf_w, \
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drvtype) \
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drvdn_b, drvdn_w, drvup_b, drvup_w, \
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slwr_b, slwr_w, slwf_b, slwf_w, \
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drvtype) \
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{ \
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.name = "drive_" #pg_name, \
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.pins = drive_##pg_name##_pins, \
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@ -1569,7 +1561,7 @@ static struct tegra_function tegra114_functions[] = {
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.lock_reg = -1, \
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.ioreset_reg = -1, \
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.rcv_sel_reg = -1, \
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.drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \
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.drv_reg = DRV_PINGROUP_REG_Y(r), \
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.drv_bank = 0, \
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.hsm_bit = hsm_b, \
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.schmitt_bit = schmitt_b, \
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@ -1582,14 +1574,13 @@ static struct tegra_function tegra114_functions[] = {
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.slwr_width = slwr_w, \
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.slwf_bit = slwf_b, \
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.slwf_width = slwf_w, \
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.drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \
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.drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \
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.drvtype_bank = 0, \
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.drvtype_bit = 6, \
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}
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static const struct tegra_pingroup tegra114_groups[] = {
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/* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
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/* FIXME: Fill in correct data in safe column */
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PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N),
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PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N),
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PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N),
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@ -212,8 +212,8 @@
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#define TEGRA_PIN_PFF2 _GPIO(250)
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/* All non-GPIO pins follow */
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#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
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#define _PIN(offset) (NUM_GPIOS + (offset))
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#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
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#define _PIN(offset) (NUM_GPIOS + (offset))
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/* Non-GPIO pins */
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#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
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@ -406,16 +406,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
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PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
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PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
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PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
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PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
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PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
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PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
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PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
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PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
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PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
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PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
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PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
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PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
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PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
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PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
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PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
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PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
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PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
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PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
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PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
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PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
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};
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@ -1138,6 +1138,7 @@ static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
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static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
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TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
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};
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static const unsigned dp_hpd_pff0_pins[] = {
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TEGRA_PIN_DP_HPD_PFF0,
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};
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@ -1158,24 +1159,24 @@ static const unsigned cpu_pwr_req_pins[] = {
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TEGRA_PIN_CPU_PWR_REQ,
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};
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static const unsigned owr_pins[] = {
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TEGRA_PIN_OWR,
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};
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static const unsigned pwr_int_n_pins[] = {
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TEGRA_PIN_PWR_INT_N,
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};
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static const unsigned gmi_clk_lb_pins[] = {
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TEGRA_PIN_GMI_CLK_LB,
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};
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static const unsigned reset_out_n_pins[] = {
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TEGRA_PIN_RESET_OUT_N,
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};
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static const unsigned clk_32k_in_pins[] = {
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TEGRA_PIN_CLK_32K_IN,
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static const unsigned owr_pins[] = {
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TEGRA_PIN_OWR,
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};
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static const unsigned gmi_clk_lb_pins[] = {
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TEGRA_PIN_GMI_CLK_LB,
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static const unsigned clk_32k_in_pins[] = {
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TEGRA_PIN_CLK_32K_IN,
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};
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static const unsigned jtag_rtck_pins[] = {
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@ -1441,15 +1442,15 @@ static const unsigned drive_gpv_pins[] = {
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TEGRA_PIN_PFF2,
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};
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static const unsigned drive_cec_pins[] = {
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TEGRA_PIN_HDMI_CEC_PEE3,
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};
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static const unsigned drive_dev3_pins[] = {
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TEGRA_PIN_CLK3_OUT_PEE0,
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TEGRA_PIN_CLK3_REQ_PEE1,
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};
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static const unsigned drive_cec_pins[] = {
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TEGRA_PIN_HDMI_CEC_PEE3,
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};
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static const unsigned drive_at6_pins[] = {
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TEGRA_PIN_PK1,
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TEGRA_PIN_PK3,
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@ -1496,8 +1497,10 @@ static const unsigned drive_ao4_pins[] = {
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enum tegra_mux {
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TEGRA_MUX_BLINK,
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TEGRA_MUX_CCLA,
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TEGRA_MUX_CEC,
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TEGRA_MUX_CLDVFS,
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TEGRA_MUX_CLK,
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TEGRA_MUX_CLK12,
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TEGRA_MUX_CPU,
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TEGRA_MUX_DAP,
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@ -1507,6 +1510,7 @@ enum tegra_mux {
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TEGRA_MUX_DISPLAYA,
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TEGRA_MUX_DISPLAYA_ALT,
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TEGRA_MUX_DISPLAYB,
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TEGRA_MUX_DP,
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TEGRA_MUX_DTV,
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TEGRA_MUX_EXTPERIPH1,
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TEGRA_MUX_EXTPERIPH2,
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@ -1528,6 +1532,9 @@ enum tegra_mux {
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TEGRA_MUX_IRDA,
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TEGRA_MUX_KBC,
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TEGRA_MUX_OWR,
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TEGRA_MUX_PE,
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TEGRA_MUX_PE0,
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TEGRA_MUX_PE1,
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TEGRA_MUX_PMI,
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TEGRA_MUX_PWM0,
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TEGRA_MUX_PWM1,
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@ -1539,6 +1546,8 @@ enum tegra_mux {
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TEGRA_MUX_RSVD2,
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TEGRA_MUX_RSVD3,
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TEGRA_MUX_RSVD4,
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TEGRA_MUX_RTCK,
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TEGRA_MUX_SATA,
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TEGRA_MUX_SDMMC1,
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TEGRA_MUX_SDMMC2,
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TEGRA_MUX_SDMMC3,
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@ -1551,6 +1560,8 @@ enum tegra_mux {
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TEGRA_MUX_SPI4,
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TEGRA_MUX_SPI5,
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TEGRA_MUX_SPI6,
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TEGRA_MUX_SYS,
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TEGRA_MUX_TMDS,
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TEGRA_MUX_TRACE,
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TEGRA_MUX_UARTA,
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TEGRA_MUX_UARTB,
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@ -1569,16 +1580,6 @@ enum tegra_mux {
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TEGRA_MUX_VI_ALT3,
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TEGRA_MUX_VIMCLK2,
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TEGRA_MUX_VIMCLK2_ALT,
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TEGRA_MUX_SATA,
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TEGRA_MUX_CCLA,
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TEGRA_MUX_PE0,
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TEGRA_MUX_PE,
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TEGRA_MUX_PE1,
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TEGRA_MUX_DP,
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TEGRA_MUX_RTCK,
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TEGRA_MUX_SYS,
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TEGRA_MUX_CLK,
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TEGRA_MUX_TMDS,
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};
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#define FUNCTION(fname) \
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@ -1588,8 +1589,10 @@ enum tegra_mux {
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static struct tegra_function tegra124_functions[] = {
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FUNCTION(blink),
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FUNCTION(ccla),
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FUNCTION(cec),
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FUNCTION(cldvfs),
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FUNCTION(clk),
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FUNCTION(clk12),
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FUNCTION(cpu),
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FUNCTION(dap),
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@ -1599,6 +1602,7 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(displaya),
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FUNCTION(displaya_alt),
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FUNCTION(displayb),
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FUNCTION(dp),
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FUNCTION(dtv),
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FUNCTION(extperiph1),
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FUNCTION(extperiph2),
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@ -1620,6 +1624,9 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(irda),
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FUNCTION(kbc),
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FUNCTION(owr),
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FUNCTION(pe),
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FUNCTION(pe0),
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FUNCTION(pe1),
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FUNCTION(pmi),
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FUNCTION(pwm0),
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FUNCTION(pwm1),
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@ -1631,6 +1638,8 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(rsvd2),
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FUNCTION(rsvd3),
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FUNCTION(rsvd4),
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FUNCTION(rtck),
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FUNCTION(sata),
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FUNCTION(sdmmc1),
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FUNCTION(sdmmc2),
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FUNCTION(sdmmc3),
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@ -1643,6 +1652,8 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(spi4),
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FUNCTION(spi5),
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FUNCTION(spi6),
|
||||
FUNCTION(sys),
|
||||
FUNCTION(tmds),
|
||||
FUNCTION(trace),
|
||||
FUNCTION(uarta),
|
||||
FUNCTION(uartb),
|
||||
|
|
@ -1661,23 +1672,13 @@ static struct tegra_function tegra124_functions[] = {
|
|||
FUNCTION(vi_alt3),
|
||||
FUNCTION(vimclk2),
|
||||
FUNCTION(vimclk2_alt),
|
||||
FUNCTION(sata),
|
||||
FUNCTION(ccla),
|
||||
FUNCTION(pe0),
|
||||
FUNCTION(pe),
|
||||
FUNCTION(pe1),
|
||||
FUNCTION(dp),
|
||||
FUNCTION(rtck),
|
||||
FUNCTION(sys),
|
||||
FUNCTION(clk),
|
||||
FUNCTION(tmds),
|
||||
};
|
||||
|
||||
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
|
||||
#define PINGROUP_REG_A 0x3000 /* bank 1 */
|
||||
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
|
||||
#define PINGROUP_REG_A 0x3000 /* bank 1 */
|
||||
|
||||
#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
|
||||
#define PINGROUP_REG_N(r) -1
|
||||
#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
|
||||
#define PINGROUP_REG_N(r) -1
|
||||
|
||||
#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
|
||||
{ \
|
||||
|
|
@ -1685,12 +1686,12 @@ static struct tegra_function tegra124_functions[] = {
|
|||
.pins = pg_name##_pins, \
|
||||
.npins = ARRAY_SIZE(pg_name##_pins), \
|
||||
.funcs = { \
|
||||
TEGRA_MUX_ ## f0, \
|
||||
TEGRA_MUX_ ## f1, \
|
||||
TEGRA_MUX_ ## f2, \
|
||||
TEGRA_MUX_ ## f3, \
|
||||
TEGRA_MUX_##f0, \
|
||||
TEGRA_MUX_##f1, \
|
||||
TEGRA_MUX_##f2, \
|
||||
TEGRA_MUX_##f3, \
|
||||
}, \
|
||||
.func_safe = TEGRA_MUX_ ## f_safe, \
|
||||
.func_safe = TEGRA_MUX_##f_safe, \
|
||||
.mux_reg = PINGROUP_REG_Y(r), \
|
||||
.mux_bank = 1, \
|
||||
.mux_bit = 0, \
|
||||
|
|
@ -1719,8 +1720,9 @@ static struct tegra_function tegra124_functions[] = {
|
|||
.drvtype_reg = -1, \
|
||||
}
|
||||
|
||||
#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A)
|
||||
#define DRV_PINGROUP_DVRTYPE_N(r) -1
|
||||
#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
|
||||
#define DRV_PINGROUP_REG_N(r) -1
|
||||
|
||||
|
||||
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
|
||||
drvdn_b, drvdn_w, drvup_b, drvup_w, \
|
||||
|
|
@ -1738,7 +1740,7 @@ static struct tegra_function tegra124_functions[] = {
|
|||
.lock_reg = -1, \
|
||||
.ioreset_reg = -1, \
|
||||
.rcv_sel_reg = -1, \
|
||||
.drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \
|
||||
.drv_reg = DRV_PINGROUP_REG_Y(r), \
|
||||
.drv_bank = 0, \
|
||||
.hsm_bit = hsm_b, \
|
||||
.schmitt_bit = schmitt_b, \
|
||||
|
|
@ -1751,7 +1753,7 @@ static struct tegra_function tegra124_functions[] = {
|
|||
.slwr_width = slwr_w, \
|
||||
.slwf_bit = slwf_b, \
|
||||
.slwf_width = slwf_w, \
|
||||
.drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \
|
||||
.drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \
|
||||
.drvtype_bank = 0, \
|
||||
.drvtype_bit = 6, \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
* Most pins affected by the pinmux can also be GPIOs. Define these first.
|
||||
* These must match how the GPIO driver names/numbers its pins.
|
||||
*/
|
||||
#define _GPIO(offset) (offset)
|
||||
#define _GPIO(offset) (offset)
|
||||
|
||||
#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
|
||||
#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
|
||||
|
|
@ -277,8 +277,8 @@
|
|||
#define TEGRA_PIN_PEE7 _GPIO(247)
|
||||
|
||||
/* All non-GPIO pins follow */
|
||||
#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
|
||||
#define _PIN(offset) (NUM_GPIOS + (offset))
|
||||
#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
|
||||
#define _PIN(offset) (NUM_GPIOS + (offset))
|
||||
|
||||
/* Non-GPIO pins */
|
||||
#define TEGRA_PIN_CLK_32K_IN _PIN(0)
|
||||
|
|
@ -2105,11 +2105,11 @@ static struct tegra_function tegra30_functions[] = {
|
|||
FUNCTION(vi_alt3),
|
||||
};
|
||||
|
||||
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
|
||||
#define PINGROUP_REG_A 0x3000 /* bank 1 */
|
||||
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
|
||||
#define PINGROUP_REG_A 0x3000 /* bank 1 */
|
||||
|
||||
#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
|
||||
#define PINGROUP_REG_N(r) -1
|
||||
#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
|
||||
#define PINGROUP_REG_N(r) -1
|
||||
|
||||
#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \
|
||||
{ \
|
||||
|
|
@ -2117,12 +2117,12 @@ static struct tegra_function tegra30_functions[] = {
|
|||
.pins = pg_name##_pins, \
|
||||
.npins = ARRAY_SIZE(pg_name##_pins), \
|
||||
.funcs = { \
|
||||
TEGRA_MUX_ ## f0, \
|
||||
TEGRA_MUX_ ## f1, \
|
||||
TEGRA_MUX_ ## f2, \
|
||||
TEGRA_MUX_ ## f3, \
|
||||
TEGRA_MUX_##f0, \
|
||||
TEGRA_MUX_##f1, \
|
||||
TEGRA_MUX_##f2, \
|
||||
TEGRA_MUX_##f3, \
|
||||
}, \
|
||||
.func_safe = TEGRA_MUX_ ## f_safe, \
|
||||
.func_safe = TEGRA_MUX_##f_safe, \
|
||||
.mux_reg = PINGROUP_REG_Y(r), \
|
||||
.mux_bank = 1, \
|
||||
.mux_bit = 0, \
|
||||
|
|
@ -2149,6 +2149,9 @@ static struct tegra_function tegra30_functions[] = {
|
|||
.drvtype_reg = -1, \
|
||||
}
|
||||
|
||||
#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
|
||||
#define DRV_PINGROUP_REG_N(r) -1
|
||||
|
||||
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
|
||||
drvdn_b, drvdn_w, drvup_b, drvup_w, \
|
||||
slwr_b, slwr_w, slwf_b, slwf_w) \
|
||||
|
|
@ -2164,7 +2167,7 @@ static struct tegra_function tegra30_functions[] = {
|
|||
.lock_reg = -1, \
|
||||
.ioreset_reg = -1, \
|
||||
.rcv_sel_reg = -1, \
|
||||
.drv_reg = ((r) - DRV_PINGROUP_REG_A), \
|
||||
.drv_reg = DRV_PINGROUP_REG_Y(r), \
|
||||
.drv_bank = 0, \
|
||||
.hsm_bit = hsm_b, \
|
||||
.schmitt_bit = schmitt_b, \
|
||||
|
|
@ -2182,7 +2185,6 @@ static struct tegra_function tegra30_functions[] = {
|
|||
|
||||
static const struct tegra_pingroup tegra30_groups[] = {
|
||||
/* pg_name, f0, f1, f2, f3, safe, r, od, ior */
|
||||
/* FIXME: Fill in correct data in safe column */
|
||||
PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N),
|
||||
PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N),
|
||||
PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N),
|
||||
|
|
@ -2495,6 +2497,7 @@ static struct of_device_id tegra30_pinctrl_of_match[] = {
|
|||
{ .compatible = "nvidia,tegra30-pinmux", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver tegra30_pinctrl_driver = {
|
||||
.driver = {
|
||||
|
|
@ -2510,4 +2513,3 @@ module_platform_driver(tegra30_pinctrl_driver);
|
|||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
|
||||
|
|
|
|||
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