Pin control fixes for the v6.3 kernel cycle:
- Fix up the Kconfig options for MediaTek MT7981. - Fix the irq domain name in the AT91-PIO4 driver. - Fix some alternative muxing modes in the Ocelot driver. - Allocate the GPIO numbers dynamically in the STM32 driver. - Disable and mask interrupts on resume in the AMD driver. - Fix a typo in the Qualcomm SM8550 pin control device tree bindings. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmQoWq8ACgkQQRCzN7AZ XXOwVA/+NQmVnGB7otNkfmqk+ZB/Wyksapv5z8+skEqLMatWuDZ77AaaX/f1d+Cm M3yTSk5A/qhzC0iJCtjujz+flgc6zARWFnnzyYnp+zHk/CECGQuqcw6rWw/9Ci9n UN9+8QhT8HkT+/4iRrBlSyFCkQmuKEFFSdCMrQIJoKEyCSlW0ihwoSzTeaBhNIIP JJkk1Nc/iPaqS4KmuGYbDZl8YfHgIjlh8im1WHQIAPNZG7Mw45iqkcv3W4yr5thf y6MflFdQa1EuPML2yYApmlI6DyWDgYpIGcwGo7svnRNQiKQ0+f3Weqzf/0943Jd/ sj94RKN2ejeKdl3cdZ5pmbO72rzeM1YQrpQFsSM3WJoV50Y3Xse1gR+xupOKngjU DeimMMsKFgUhoyoqVKlsdy3SiT1/ilS0zW5srcqOHkr4tseHENaJhEjl0s9LBn0m uwEwbGqjEMb9Sov0F7WpIBRnIFmuq/lndls7u+xbbJromQ2C26EEht2ABomcGP4G bmFuESoMdcDvuifMdmsiInS239Wb15tCKWz14D1l5mL0xm0VUCnGVgq0DLOHGvQO XvqjL+FwHFm3fY8ML2CtTWnAmvFIK/tUZevG8t0HrSwkVb555PKso86bV9xU73Ay kZaV9VD6fQFZWtIVsz4ejtIe82yB2egxkoJBaSNTT/SP5qrhgeg= =/F9m -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "Some pin control fixes for the v6.3 series. The most notable and urgent one is probably the AMD fix which affects AMD laptops, found by the Chromium people. Summary: - Fix up the Kconfig options for MediaTek MT7981 - Fix the irq domain name in the AT91-PIO4 driver - Fix some alternative muxing modes in the Ocelot driver - Allocate the GPIO numbers dynamically in the STM32 driver - Disable and mask interrupts on resume in the AMD driver - Fix a typo in the Qualcomm SM8550 pin control device tree bindings" * tag 'pinctrl-v6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: dt-bindings: pinctrl: qcom,sm8550-lpass-lpi: allow input-enabled and bias-bus-hold pinctrl: amd: Disable and mask interrupts on resume pinctrl: stm32: use dynamic allocation of GPIO base pinctrl: ocelot: Fix alt mode for ocelot pinctrl: at91-pio4: fix domain name assignment pinctrl: mediatek: fix naming inconsistency pinctrl: mediatek: add missing options to PINCTRL_MT7981
This commit is contained in:
Linus Torvalds
Коммит
93e2b01740
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@ -96,9 +96,11 @@ $defs:
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2: Lower Slew rate (slower edges)
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3: Reserved (No adjustments)
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bias-bus-hold: true
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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input-enable: true
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output-high: true
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output-low: true
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@ -45,35 +45,35 @@ config PINCTRL_MTK_PARIS
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# For ARMv7 SoCs
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config PINCTRL_MT2701
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bool "Mediatek MT2701 pin control"
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bool "MediaTek MT2701 pin control"
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depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST
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depends on OF
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default MACH_MT2701
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select PINCTRL_MTK
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config PINCTRL_MT7623
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bool "Mediatek MT7623 pin control with generic binding"
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bool "MediaTek MT7623 pin control with generic binding"
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depends on MACH_MT7623 || COMPILE_TEST
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depends on OF
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default MACH_MT7623
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select PINCTRL_MTK_MOORE
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config PINCTRL_MT7629
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bool "Mediatek MT7629 pin control"
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bool "MediaTek MT7629 pin control"
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depends on MACH_MT7629 || COMPILE_TEST
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depends on OF
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default MACH_MT7629
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select PINCTRL_MTK_MOORE
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config PINCTRL_MT8135
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bool "Mediatek MT8135 pin control"
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bool "MediaTek MT8135 pin control"
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depends on MACH_MT8135 || COMPILE_TEST
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depends on OF
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default MACH_MT8135
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select PINCTRL_MTK
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config PINCTRL_MT8127
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bool "Mediatek MT8127 pin control"
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bool "MediaTek MT8127 pin control"
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depends on MACH_MT8127 || COMPILE_TEST
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depends on OF
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default MACH_MT8127
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@ -88,33 +88,33 @@ config PINCTRL_MT2712
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select PINCTRL_MTK
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config PINCTRL_MT6765
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tristate "Mediatek MT6765 pin control"
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tristate "MediaTek MT6765 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_PARIS
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config PINCTRL_MT6779
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tristate "Mediatek MT6779 pin control"
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tristate "MediaTek MT6779 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_PARIS
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help
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Say yes here to support pin controller and gpio driver
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on Mediatek MT6779 SoC.
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on MediaTek MT6779 SoC.
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In MTK platform, we support virtual gpio and use it to
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map specific eint which doesn't have real gpio pin.
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config PINCTRL_MT6795
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bool "Mediatek MT6795 pin control"
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bool "MediaTek MT6795 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_PARIS
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config PINCTRL_MT6797
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bool "Mediatek MT6797 pin control"
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bool "MediaTek MT6797 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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@ -128,40 +128,42 @@ config PINCTRL_MT7622
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select PINCTRL_MTK_MOORE
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config PINCTRL_MT7981
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bool "Mediatek MT7981 pin control"
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bool "MediaTek MT7981 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_MOORE
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config PINCTRL_MT7986
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bool "Mediatek MT7986 pin control"
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bool "MediaTek MT7986 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_MOORE
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config PINCTRL_MT8167
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bool "Mediatek MT8167 pin control"
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bool "MediaTek MT8167 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK
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config PINCTRL_MT8173
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bool "Mediatek MT8173 pin control"
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bool "MediaTek MT8173 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK
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config PINCTRL_MT8183
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bool "Mediatek MT8183 pin control"
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bool "MediaTek MT8183 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_PARIS
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config PINCTRL_MT8186
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bool "Mediatek MT8186 pin control"
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bool "MediaTek MT8186 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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@ -180,28 +182,28 @@ config PINCTRL_MT8188
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map specific eint which doesn't have real gpio pin.
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config PINCTRL_MT8192
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bool "Mediatek MT8192 pin control"
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bool "MediaTek MT8192 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_PARIS
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config PINCTRL_MT8195
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bool "Mediatek MT8195 pin control"
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bool "MediaTek MT8195 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_PARIS
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config PINCTRL_MT8365
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bool "Mediatek MT8365 pin control"
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bool "MediaTek MT8365 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK
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config PINCTRL_MT8516
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bool "Mediatek MT8516 pin control"
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bool "MediaTek MT8516 pin control"
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depends on OF
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depends on ARM64 || COMPILE_TEST
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default ARM64 && ARCH_MEDIATEK
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@ -209,7 +211,7 @@ config PINCTRL_MT8516
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# For PMIC
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config PINCTRL_MT6397
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bool "Mediatek MT6397 pin control"
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bool "MediaTek MT6397 pin control"
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depends on MFD_MT6397 || COMPILE_TEST
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depends on OF
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default MFD_MT6397
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@ -872,32 +872,34 @@ static const struct pinconf_ops amd_pinconf_ops = {
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.pin_config_group_set = amd_pinconf_group_set,
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};
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static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
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static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin)
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{
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struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
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const struct pin_desc *pd;
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unsigned long flags;
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u32 pin_reg, mask;
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int i;
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mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
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BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
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BIT(WAKE_CNTRL_OFF_S4);
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for (i = 0; i < desc->npins; i++) {
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int pin = desc->pins[i].number;
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const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
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pd = pin_desc_get(gpio_dev->pctrl, pin);
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if (!pd)
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return;
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if (!pd)
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continue;
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raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + pin * 4);
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pin_reg &= ~mask;
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writel(pin_reg, gpio_dev->base + pin * 4);
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
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{
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struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
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int i;
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pin_reg = readl(gpio_dev->base + i * 4);
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pin_reg &= ~mask;
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writel(pin_reg, gpio_dev->base + i * 4);
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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for (i = 0; i < desc->npins; i++)
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amd_gpio_irq_init_pin(gpio_dev, i);
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}
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#ifdef CONFIG_PM_SLEEP
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@ -950,8 +952,10 @@ static int amd_gpio_resume(struct device *dev)
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for (i = 0; i < desc->npins; i++) {
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int pin = desc->pins[i].number;
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if (!amd_gpio_should_save(gpio_dev, pin))
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if (!amd_gpio_should_save(gpio_dev, pin)) {
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amd_gpio_irq_init_pin(gpio_dev, pin);
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continue;
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}
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raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
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@ -1206,7 +1206,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
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dev_err(dev, "can't add the irq domain\n");
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return -ENODEV;
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}
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atmel_pioctrl->irq_domain->name = "atmel gpio";
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for (i = 0; i < atmel_pioctrl->npins; i++) {
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int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
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@ -1204,7 +1204,7 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
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BIT(p), f << p);
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regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
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BIT(p), f << (p - 1));
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BIT(p), (f >> 1) << p);
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return 0;
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}
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@ -1330,7 +1330,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
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if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
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bank_ioport_nr = bank_nr;
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bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
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bank->gpio_chip.base = -1;
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bank->gpio_chip.ngpio = npins;
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bank->gpio_chip.fwnode = fwnode;
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