arch: Clean up asm/barrier.h implementations using asm-generic/barrier.h
We're going to be adding a few new barrier primitives, and in order to avoid endless duplication make more agressive use of asm-generic/barrier.h. Change the asm-generic/barrier.h such that it allows partial barrier definitions and fills out the rest with defaults. There are a few architectures (m32r, m68k) that could probably do away with their barrier.h file entirely but are kept for now due to their unconventional nop() implementation. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Michael Neuling <mikey@neuling.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Victor Kaplansky <VICTORK@il.ibm.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Link: http://lkml.kernel.org/r/20131213150640.846368594@infradead.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Peter Zijlstra
Ingo Molnar
Родитель
1de7da377b
Коммит
93ea02bb84
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@ -3,33 +3,18 @@
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#include <asm/compiler.h>
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#define mb() \
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__asm__ __volatile__("mb": : :"memory")
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#define mb() __asm__ __volatile__("mb": : :"memory")
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#define rmb() __asm__ __volatile__("mb": : :"memory")
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#define wmb() __asm__ __volatile__("wmb": : :"memory")
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#define rmb() \
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__asm__ __volatile__("mb": : :"memory")
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#define wmb() \
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__asm__ __volatile__("wmb": : :"memory")
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#define read_barrier_depends() \
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__asm__ __volatile__("mb": : :"memory")
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#define read_barrier_depends() __asm__ __volatile__("mb": : :"memory")
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#ifdef CONFIG_SMP
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#define __ASM_SMP_MB "\tmb\n"
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define __ASM_SMP_MB
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#endif
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#define set_mb(var, value) \
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do { var = value; mb(); } while (0)
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#include <asm-generic/barrier.h>
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#endif /* __BARRIER_H */
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@ -47,3 +47,4 @@ generic-y += user.h
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generic-y += vga.h
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generic-y += xor.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -8,22 +8,15 @@
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#ifndef __ASM_AVR32_BARRIER_H
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#define __ASM_AVR32_BARRIER_H
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#define nop() asm volatile("nop")
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#define mb() asm volatile("" : : : "memory")
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#define rmb() mb()
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#define wmb() asm volatile("sync 0" : : : "memory")
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while(0)
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/*
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* Weirdest thing ever.. no full barrier, but it has a write barrier!
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*/
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#define wmb() asm volatile("sync 0" : : : "memory")
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#ifdef CONFIG_SMP
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# error "The AVR32 port does not support SMP"
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#else
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# define smp_mb() barrier()
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# define smp_rmb() barrier()
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# define smp_wmb() barrier()
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# define smp_read_barrier_depends() do { } while(0)
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#endif
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#include <asm-generic/barrier.h>
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#endif /* __ASM_AVR32_BARRIER_H */
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@ -23,26 +23,10 @@
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# define rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
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# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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#else
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# define mb() barrier()
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# define rmb() barrier()
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# define wmb() barrier()
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# define read_barrier_depends() do { } while (0)
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#endif
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#else /* !CONFIG_SMP */
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while (0)
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#endif /* !CONFIG_SMP */
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_read_barrier_depends() read_barrier_depends()
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#include <asm-generic/barrier.h>
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#endif /* _BLACKFIN_BARRIER_H */
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@ -12,3 +12,4 @@ generic-y += trace_clock.h
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generic-y += vga.h
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generic-y += xor.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -1,25 +0,0 @@
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#ifndef __ASM_CRIS_BARRIER_H
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#define __ASM_CRIS_BARRIER_H
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#define nop() __asm__ __volatile__ ("nop");
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#define barrier() __asm__ __volatile__("": : :"memory")
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#endif /* __ASM_CRIS_BARRIER_H */
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@ -17,13 +17,7 @@
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#define mb() asm volatile ("membar" : : :"memory")
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#define rmb() asm volatile ("membar" : : :"memory")
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#define wmb() asm volatile ("membar" : : :"memory")
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#define read_barrier_depends() do { } while (0)
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do {} while(0)
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#define set_mb(var, value) \
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do { var = (value); barrier(); } while (0)
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#include <asm-generic/barrier.h>
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#endif /* _ASM_BARRIER_H */
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@ -54,3 +54,4 @@ generic-y += ucontext.h
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generic-y += unaligned.h
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generic-y += xor.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -11,84 +11,6 @@
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#define nop() __asm__ __volatile__ ("nop" : : )
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/*
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* Memory barrier.
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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*/
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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**/
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#define read_barrier_depends() do { } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif
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#include <asm-generic/barrier.h>
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#endif /* _ASM_M32R_BARRIER_H */
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@ -1,20 +1,8 @@
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#ifndef _M68K_BARRIER_H
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#define _M68K_BARRIER_H
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/*
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* Force strict CPU ordering.
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* Not really required on m68k...
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*/
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#define nop() do { asm volatile ("nop"); barrier(); } while (0)
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() ((void)0)
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#define set_mb(var, value) ({ (var) = (value); wmb(); })
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() ((void)0)
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#include <asm-generic/barrier.h>
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#endif /* _M68K_BARRIER_H */
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@ -4,3 +4,4 @@ generic-y += exec.h
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generic-y += trace_clock.h
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generic-y += syscalls.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -1,27 +0,0 @@
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/*
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef _ASM_MICROBLAZE_BARRIER_H
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#define _ASM_MICROBLAZE_BARRIER_H
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#define nop() asm volatile ("nop")
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#define smp_read_barrier_depends() do {} while (0)
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#define read_barrier_depends() do {} while (0)
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#endif /* _ASM_MICROBLAZE_BARRIER_H */
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@ -3,3 +3,4 @@ generic-y += clkdev.h
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generic-y += exec.h
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generic-y += trace_clock.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -1,37 +0,0 @@
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/* MN10300 memory barrier definitions
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_BARRIER_H
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#define _ASM_BARRIER_H
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#define nop() asm volatile ("nop")
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#define mb() asm volatile ("": : :"memory")
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#define rmb() mb()
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#define wmb() asm volatile ("": : :"memory")
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#else /* CONFIG_SMP */
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#endif /* CONFIG_SMP */
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define read_barrier_depends() do {} while (0)
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#define smp_read_barrier_depends() do {} while (0)
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#endif /* _ASM_BARRIER_H */
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@ -5,3 +5,4 @@ generic-y += word-at-a-time.h auxvec.h user.h cputime.h emergency-restart.h \
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poll.h xor.h clkdev.h exec.h
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generic-y += trace_clock.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -1,35 +0,0 @@
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#ifndef __PARISC_BARRIER_H
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#define __PARISC_BARRIER_H
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/*
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** This is simply the barrier() macro from linux/kernel.h but when serial.c
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** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
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** hasn't yet been included yet so it fails, thus repeating the macro here.
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**
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** PA-RISC architecture allows for weakly ordered memory accesses although
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** none of the processors use it. There is a strong ordered bit that is
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** set in the O-bit of the page directory entry. Operating systems that
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** can not tolerate out of order accesses should set this bit when mapping
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** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
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** of the processor implemented the PSW O-bit). The PCX-W ERS states that
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** the TLB O-bit is not implemented so the page directory does not need to
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** have the O-bit set when mapping pages (section 3.1). This section also
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** states that the PSW Y, Z, G, and O bits are not implemented.
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** So it looks like nothing needs to be done for parisc-linux (yet).
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** (thanks to chada for the above comment -ggg)
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**
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** The __asm__ op below simple prevents gcc/ld from reordering
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** instructions across the mb() "call".
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*/
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#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
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#define rmb() mb()
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#define wmb() mb()
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#define smp_mb() mb()
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#define smp_rmb() mb()
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#define smp_wmb() mb()
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#define smp_read_barrier_depends() do { } while(0)
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#endif /* __PARISC_BARRIER_H */
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@ -5,3 +5,4 @@ generic-y += clkdev.h
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generic-y += trace_clock.h
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generic-y += xor.h
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generic-y += preempt.h
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generic-y += barrier.h
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@ -1,16 +0,0 @@
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#ifndef _ASM_SCORE_BARRIER_H
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#define _ASM_SCORE_BARRIER_H
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define read_barrier_depends() do {} while (0)
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#define smp_read_barrier_depends() do {} while (0)
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#define set_mb(var, value) do {var = value; wmb(); } while (0)
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#endif /* _ASM_SCORE_BARRIER_H */
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|
|
@ -26,29 +26,14 @@
|
|||
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
|
||||
#define mb() __asm__ __volatile__ ("synco": : :"memory")
|
||||
#define rmb() mb()
|
||||
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
|
||||
#define wmb() mb()
|
||||
#define ctrl_barrier() __icbi(PAGE_OFFSET)
|
||||
#define read_barrier_depends() do { } while(0)
|
||||
#else
|
||||
#define mb() __asm__ __volatile__ ("": : :"memory")
|
||||
#define rmb() mb()
|
||||
#define wmb() __asm__ __volatile__ ("": : :"memory")
|
||||
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
|
||||
#define read_barrier_depends() do { } while(0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define smp_mb() mb()
|
||||
#define smp_rmb() rmb()
|
||||
#define smp_wmb() wmb()
|
||||
#define smp_read_barrier_depends() read_barrier_depends()
|
||||
#else
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
#define smp_read_barrier_depends() do { } while(0)
|
||||
#endif
|
||||
|
||||
#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
|
||||
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* __ASM_SH_BARRIER_H */
|
||||
|
|
|
|||
|
|
@ -1,15 +1,7 @@
|
|||
#ifndef __SPARC_BARRIER_H
|
||||
#define __SPARC_BARRIER_H
|
||||
|
||||
/* XXX Change this if we ever use a PSO mode kernel. */
|
||||
#define mb() __asm__ __volatile__ ("" : : : "memory")
|
||||
#define rmb() mb()
|
||||
#define wmb() mb()
|
||||
#define read_barrier_depends() do { } while(0)
|
||||
#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
|
||||
#define smp_mb() __asm__ __volatile__("":::"memory")
|
||||
#define smp_rmb() __asm__ __volatile__("":::"memory")
|
||||
#define smp_wmb() __asm__ __volatile__("":::"memory")
|
||||
#define smp_read_barrier_depends() do { } while(0)
|
||||
#include <asm/processor.h> /* for nop() */
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* !(__SPARC_BARRIER_H) */
|
||||
|
|
|
|||
|
|
@ -22,59 +22,6 @@
|
|||
#include <arch/spr_def.h>
|
||||
#include <asm/timex.h>
|
||||
|
||||
/*
|
||||
* read_barrier_depends - Flush all pending reads that subsequents reads
|
||||
* depend on.
|
||||
*
|
||||
* No data-dependent reads from memory-like regions are ever reordered
|
||||
* over this barrier. All reads preceding this primitive are guaranteed
|
||||
* to access memory (but not necessarily other CPUs' caches) before any
|
||||
* reads following this primitive that depend on the data return by
|
||||
* any of the preceding reads. This primitive is much lighter weight than
|
||||
* rmb() on most CPUs, and is never heavier weight than is
|
||||
* rmb().
|
||||
*
|
||||
* These ordering constraints are respected by both the local CPU
|
||||
* and the compiler.
|
||||
*
|
||||
* Ordering is not guaranteed by anything other than these primitives,
|
||||
* not even by data dependencies. See the documentation for
|
||||
* memory_barrier() for examples and URLs to more information.
|
||||
*
|
||||
* For example, the following code would force ordering (the initial
|
||||
* value of "a" is zero, "b" is one, and "p" is "&a"):
|
||||
*
|
||||
* <programlisting>
|
||||
* CPU 0 CPU 1
|
||||
*
|
||||
* b = 2;
|
||||
* memory_barrier();
|
||||
* p = &b; q = p;
|
||||
* read_barrier_depends();
|
||||
* d = *q;
|
||||
* </programlisting>
|
||||
*
|
||||
* because the read of "*q" depends on the read of "p" and these
|
||||
* two reads are separated by a read_barrier_depends(). However,
|
||||
* the following code, with the same initial values for "a" and "b":
|
||||
*
|
||||
* <programlisting>
|
||||
* CPU 0 CPU 1
|
||||
*
|
||||
* a = 2;
|
||||
* memory_barrier();
|
||||
* b = 3; y = b;
|
||||
* read_barrier_depends();
|
||||
* x = a;
|
||||
* </programlisting>
|
||||
*
|
||||
* does not enforce ordering, since there is no data dependency between
|
||||
* the read of "a" and the read of "b". Therefore, on some CPUs, such
|
||||
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
|
||||
* in cases like this where there are no data dependencies.
|
||||
*/
|
||||
#define read_barrier_depends() do { } while (0)
|
||||
|
||||
#define __sync() __insn_mf()
|
||||
|
||||
#include <hv/syscall_public.h>
|
||||
|
|
@ -125,20 +72,7 @@ mb_incoherent(void)
|
|||
#define mb() fast_mb()
|
||||
#define iob() fast_iob()
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define smp_mb() mb()
|
||||
#define smp_rmb() rmb()
|
||||
#define smp_wmb() wmb()
|
||||
#define smp_read_barrier_depends() read_barrier_depends()
|
||||
#else
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
#define smp_read_barrier_depends() do { } while (0)
|
||||
#endif
|
||||
|
||||
#define set_mb(var, value) \
|
||||
do { var = value; mb(); } while (0)
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* _ASM_TILE_BARRIER_H */
|
||||
|
|
|
|||
|
|
@ -14,15 +14,6 @@
|
|||
#define dsb() __asm__ __volatile__ ("" : : : "memory")
|
||||
#define dmb() __asm__ __volatile__ ("" : : : "memory")
|
||||
|
||||
#define mb() barrier()
|
||||
#define rmb() barrier()
|
||||
#define wmb() barrier()
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
#define read_barrier_depends() do { } while (0)
|
||||
#define smp_read_barrier_depends() do { } while (0)
|
||||
|
||||
#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* __UNICORE_BARRIER_H__ */
|
||||
|
|
|
|||
|
|
@ -9,21 +9,14 @@
|
|||
#ifndef _XTENSA_SYSTEM_H
|
||||
#define _XTENSA_SYSTEM_H
|
||||
|
||||
#define smp_read_barrier_depends() do { } while(0)
|
||||
#define read_barrier_depends() do { } while(0)
|
||||
|
||||
#define mb() ({ __asm__ __volatile__("memw" : : : "memory"); })
|
||||
#define rmb() barrier()
|
||||
#define wmb() mb()
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#error smp_* not defined
|
||||
#else
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
#endif
|
||||
|
||||
#define set_mb(var, value) do { var = value; mb(); } while (0)
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* _XTENSA_SYSTEM_H */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/* Generic barrier definitions, based on MN10300 definitions.
|
||||
/*
|
||||
* Generic barrier definitions, originally based on MN10300 definitions.
|
||||
*
|
||||
* It should be possible to use these on really simple architectures,
|
||||
* but it serves more as a starting point for new ports.
|
||||
|
|
@ -16,35 +17,50 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define nop() asm volatile ("nop")
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#ifndef nop
|
||||
#define nop() asm volatile ("nop")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Force strict CPU ordering.
|
||||
* And yes, this is required on UP too when we're talking
|
||||
* to devices.
|
||||
* Force strict CPU ordering. And yes, this is required on UP too when we're
|
||||
* talking to devices.
|
||||
*
|
||||
* This implementation only contains a compiler barrier.
|
||||
* Fall back to compiler barriers if nothing better is provided.
|
||||
*/
|
||||
|
||||
#define mb() asm volatile ("": : :"memory")
|
||||
#ifndef mb
|
||||
#define mb() barrier()
|
||||
#endif
|
||||
|
||||
#ifndef rmb
|
||||
#define rmb() mb()
|
||||
#define wmb() asm volatile ("": : :"memory")
|
||||
#endif
|
||||
|
||||
#ifndef wmb
|
||||
#define wmb() mb()
|
||||
#endif
|
||||
|
||||
#ifndef read_barrier_depends
|
||||
#define read_barrier_depends() do { } while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define smp_mb() mb()
|
||||
#define smp_rmb() rmb()
|
||||
#define smp_wmb() wmb()
|
||||
#define smp_read_barrier_depends() read_barrier_depends()
|
||||
#else
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
#define smp_read_barrier_depends() do { } while (0)
|
||||
#endif
|
||||
|
||||
#define set_mb(var, value) do { var = value; mb(); } while (0)
|
||||
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
|
||||
|
||||
#define read_barrier_depends() do {} while (0)
|
||||
#define smp_read_barrier_depends() do {} while (0)
|
||||
#ifndef set_mb
|
||||
#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* __ASM_GENERIC_BARRIER_H */
|
||||
|
|
|
|||
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