pwm: atmel: add Timer Counter Block PWM driver
This patch adds a PWM driver based on Atmel Timer Counter Block. The Timer Counter Block is used in Waveform generator mode. A Timer Counter Block provides up to 6 PWM devices grouped by 2: * group 0 = PWM 0 and 1 * group 1 = PWM 2 and 3 * group 2 = PMW 4 and 5 PWM devices in a given group must be configured with the same period value. If a PWM device in a group tries to change the period value and the other device is already configured with a different value an error will be returned. This driver requires device tree support. The Timer Counter Block number used to create a PWM chip is given by the tc-block field in an "atmel,tcb-pwm" compatible node. This patch was tested on kizbox board (at91sam9g20 SoC) with pwm-leds. Signed-off-by: Boris BREZILLON <linux-arm@overkiz.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
This commit is contained in:
Boris BREZILLON
Thierry Reding
Родитель
d1c3ed669a
Коммит
9421bade07
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@ -0,0 +1,18 @@
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Atmel TCB PWM controller
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Required properties:
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- compatible: should be "atmel,tcb-pwm"
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- #pwm-cells: Should be 3. The first cell specifies the per-chip index
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of the PWM to use, the second cell is the period in nanoseconds and
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bit 0 in the third cell is used to encode the polarity of PWM output.
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Set bit 0 of the third cell in PWM specifier to 1 for inverse polarity &
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set to 0 for normal polarity.
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- tc-block: The Timer Counter block to use as a PWM chip.
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Example:
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pwm {
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compatible = "atmel,tcb-pwm";
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#pwm-cells = <3>;
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tc-block = <1>;
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};
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@ -37,6 +37,18 @@ config PWM_AB8500
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To compile this driver as a module, choose M here: the module
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will be called pwm-ab8500.
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config PWM_ATMEL_TCB
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tristate "TC Block PWM"
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depends on ATMEL_TCLIB && OF
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help
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Generic PWM framework driver for Atmel Timer Counter Block.
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A Timer Counter Block provides 6 PWM devices grouped by 2.
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Devices in a given group must have the same period.
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To compile this driver as a module, choose M here: the module
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will be called pwm-atmel-tcb.
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config PWM_BFIN
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tristate "Blackfin PWM support"
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depends on BFIN_GPTIMERS
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@ -1,5 +1,6 @@
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obj-$(CONFIG_PWM) += core.o
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obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
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obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
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obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
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obj-$(CONFIG_PWM_IMX) += pwm-imx.o
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obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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@ -0,0 +1,445 @@
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/*
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* Copyright (C) Overkiz SAS 2012
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*
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* Author: Boris BREZILLON <b.brezillon@overkiz.com>
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/atmel_tc.h>
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#include <linux/pwm.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#define NPWM 6
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#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
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ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
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#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
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ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
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struct atmel_tcb_pwm_device {
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enum pwm_polarity polarity; /* PWM polarity */
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unsigned div; /* PWM clock divider */
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unsigned duty; /* PWM duty expressed in clk cycles */
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unsigned period; /* PWM period expressed in clk cycles */
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};
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struct atmel_tcb_pwm_chip {
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struct pwm_chip chip;
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spinlock_t lock;
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struct atmel_tc *tc;
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struct atmel_tcb_pwm_device *pwms[NPWM];
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};
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static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct atmel_tcb_pwm_chip, chip);
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}
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static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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tcbpwm->polarity = polarity;
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return 0;
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}
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static int atmel_tcb_pwm_request(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm;
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struct atmel_tc *tc = tcbpwmc->tc;
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void __iomem *regs = tc->regs;
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unsigned group = pwm->hwpwm / 2;
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unsigned index = pwm->hwpwm % 2;
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unsigned cmr;
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int ret;
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tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
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if (!tcbpwm)
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return -ENOMEM;
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ret = clk_enable(tc->clk[group]);
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if (ret) {
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devm_kfree(chip->dev, tcbpwm);
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return ret;
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}
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pwm_set_chip_data(pwm, tcbpwm);
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tcbpwm->polarity = PWM_POLARITY_NORMAL;
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tcbpwm->duty = 0;
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tcbpwm->period = 0;
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tcbpwm->div = 0;
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spin_lock(&tcbpwmc->lock);
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cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
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/*
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* Get init config from Timer Counter registers if
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* Timer Counter is already configured as a PWM generator.
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*/
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if (cmr & ATMEL_TC_WAVE) {
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if (index == 0)
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tcbpwm->duty =
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__raw_readl(regs + ATMEL_TC_REG(group, RA));
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else
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tcbpwm->duty =
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__raw_readl(regs + ATMEL_TC_REG(group, RB));
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tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
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tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC));
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cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
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ATMEL_TC_BCMR_MASK);
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} else
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cmr = 0;
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cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
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__raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
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spin_unlock(&tcbpwmc->lock);
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tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
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return 0;
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}
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static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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struct atmel_tc *tc = tcbpwmc->tc;
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clk_disable(tc->clk[pwm->hwpwm / 2]);
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tcbpwmc->pwms[pwm->hwpwm] = NULL;
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devm_kfree(chip->dev, tcbpwm);
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}
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static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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struct atmel_tc *tc = tcbpwmc->tc;
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void __iomem *regs = tc->regs;
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unsigned group = pwm->hwpwm / 2;
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unsigned index = pwm->hwpwm % 2;
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unsigned cmr;
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enum pwm_polarity polarity = tcbpwm->polarity;
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/*
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* If duty is 0 the timer will be stopped and we have to
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* configure the output correctly on software trigger:
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* - set output to high if PWM_POLARITY_INVERSED
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* - set output to low if PWM_POLARITY_NORMAL
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*
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* This is why we're reverting polarity in this case.
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*/
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if (tcbpwm->duty == 0)
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polarity = !polarity;
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spin_lock(&tcbpwmc->lock);
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cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
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/* flush old setting and set the new one */
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if (index == 0) {
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cmr &= ~ATMEL_TC_ACMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ASWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_ASWTRG_SET;
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} else {
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cmr &= ~ATMEL_TC_BCMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BSWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_BSWTRG_SET;
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}
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__raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
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/*
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* Use software trigger to apply the new setting.
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* If both PWM devices in this group are disabled we stop the clock.
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*/
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if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC)))
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__raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS,
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regs + ATMEL_TC_REG(group, CCR));
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else
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__raw_writel(ATMEL_TC_SWTRG, regs +
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ATMEL_TC_REG(group, CCR));
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spin_unlock(&tcbpwmc->lock);
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}
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static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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struct atmel_tc *tc = tcbpwmc->tc;
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void __iomem *regs = tc->regs;
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unsigned group = pwm->hwpwm / 2;
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unsigned index = pwm->hwpwm % 2;
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u32 cmr;
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enum pwm_polarity polarity = tcbpwm->polarity;
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/*
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* If duty is 0 the timer will be stopped and we have to
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* configure the output correctly on software trigger:
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* - set output to high if PWM_POLARITY_INVERSED
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* - set output to low if PWM_POLARITY_NORMAL
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*
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* This is why we're reverting polarity in this case.
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*/
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if (tcbpwm->duty == 0)
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polarity = !polarity;
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spin_lock(&tcbpwmc->lock);
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cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
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/* flush old setting and set the new one */
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cmr &= ~ATMEL_TC_TCCLKS;
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if (index == 0) {
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cmr &= ~ATMEL_TC_ACMR_MASK;
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/* Set CMR flags according to given polarity */
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ASWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_ASWTRG_SET;
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} else {
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cmr &= ~ATMEL_TC_BCMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BSWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_BSWTRG_SET;
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}
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/*
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* If duty is 0 or equal to period there's no need to register
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* a specific action on RA/RB and RC compare.
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* The output will be configured on software trigger and keep
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* this config till next config call.
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*/
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if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
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if (index == 0) {
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
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else
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cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
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} else {
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
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else
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cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
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}
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}
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__raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
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if (index == 0)
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__raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA));
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else
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__raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB));
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__raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC));
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/* Use software trigger to apply the new setting */
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__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
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regs + ATMEL_TC_REG(group, CCR));
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spin_unlock(&tcbpwmc->lock);
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return 0;
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}
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static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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unsigned group = pwm->hwpwm / 2;
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unsigned index = pwm->hwpwm % 2;
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struct atmel_tcb_pwm_device *atcbpwm = NULL;
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struct atmel_tc *tc = tcbpwmc->tc;
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int i;
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int slowclk = 0;
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unsigned period;
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unsigned duty;
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unsigned rate = clk_get_rate(tc->clk[group]);
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unsigned long long min;
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unsigned long long max;
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/*
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* Find best clk divisor:
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* the smallest divisor which can fulfill the period_ns requirements.
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*/
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for (i = 0; i < 5; ++i) {
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if (atmel_tc_divisors[i] == 0) {
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slowclk = i;
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continue;
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}
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min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate);
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max = min << tc->tcb_config->counter_width;
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if (max >= period_ns)
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break;
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}
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/*
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* If none of the divisor are small enough to represent period_ns
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* take slow clock (32KHz).
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*/
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if (i == 5) {
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i = slowclk;
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rate = 32768;
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min = div_u64(NSEC_PER_SEC, rate);
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max = min << 16;
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/* If period is too big return ERANGE error */
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if (max < period_ns)
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return -ERANGE;
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}
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duty = div_u64(duty_ns, min);
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period = div_u64(period_ns, min);
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if (index == 0)
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atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1];
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else
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atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1];
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/*
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* PWM devices provided by TCB driver are grouped by 2:
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* - group 0: PWM 0 & 1
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* - group 1: PWM 2 & 3
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* - group 2: PWM 4 & 5
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*
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* PWM devices in a given group must be configured with the
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* same period_ns.
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*
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* We're checking the period value of the second PWM device
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* in this group before applying the new config.
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*/
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if ((atcbpwm && atcbpwm->duty > 0 &&
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atcbpwm->duty != atcbpwm->period) &&
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(atcbpwm->div != i || atcbpwm->period != period)) {
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dev_err(chip->dev,
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"failed to configure period_ns: PWM group already configured with a different value\n");
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return -EINVAL;
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}
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tcbpwm->period = period;
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tcbpwm->div = i;
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tcbpwm->duty = duty;
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/* If the PWM is enabled, call enable to apply the new conf */
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if (test_bit(PWMF_ENABLED, &pwm->flags))
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atmel_tcb_pwm_enable(chip, pwm);
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return 0;
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}
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static const struct pwm_ops atmel_tcb_pwm_ops = {
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.request = atmel_tcb_pwm_request,
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.free = atmel_tcb_pwm_free,
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.config = atmel_tcb_pwm_config,
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.set_polarity = atmel_tcb_pwm_set_polarity,
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.enable = atmel_tcb_pwm_enable,
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.disable = atmel_tcb_pwm_disable,
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};
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static int atmel_tcb_pwm_probe(struct platform_device *pdev)
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{
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struct atmel_tcb_pwm_chip *tcbpwm;
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struct device_node *np = pdev->dev.of_node;
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struct atmel_tc *tc;
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int err;
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int tcblock;
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err = of_property_read_u32(np, "tc-block", &tcblock);
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if (err < 0) {
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dev_err(&pdev->dev,
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"failed to get Timer Counter Block number from device tree (error: %d)\n",
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err);
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return err;
|
||||
}
|
||||
|
||||
tc = atmel_tc_alloc(tcblock, "tcb-pwm");
|
||||
if (tc == NULL) {
|
||||
dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
|
||||
if (tcbpwm == NULL) {
|
||||
atmel_tc_free(tc);
|
||||
dev_err(&pdev->dev, "failed to allocate memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
tcbpwm->chip.dev = &pdev->dev;
|
||||
tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
|
||||
tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||
tcbpwm->chip.of_pwm_n_cells = 3;
|
||||
tcbpwm->chip.base = -1;
|
||||
tcbpwm->chip.npwm = NPWM;
|
||||
tcbpwm->tc = tc;
|
||||
|
||||
spin_lock_init(&tcbpwm->lock);
|
||||
|
||||
err = pwmchip_add(&tcbpwm->chip);
|
||||
if (err < 0) {
|
||||
atmel_tc_free(tc);
|
||||
return err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, tcbpwm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_tcb_pwm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
|
||||
int err;
|
||||
|
||||
err = pwmchip_remove(&tcbpwm->chip);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
atmel_tc_free(tcbpwm->tc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
|
||||
{ .compatible = "atmel,tcb-pwm", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
|
||||
|
||||
static struct platform_driver atmel_tcb_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "atmel-tcb-pwm",
|
||||
.of_match_table = atmel_tcb_pwm_dt_ids,
|
||||
},
|
||||
.probe = atmel_tcb_pwm_probe,
|
||||
.remove = atmel_tcb_pwm_remove,
|
||||
};
|
||||
module_platform_driver(atmel_tcb_pwm_driver);
|
||||
|
||||
MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
|
||||
MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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