ARM: OMAP2: convert sys_ck and osc_ck to standard clock types
osc_ck can be simply defined as a multiplexer clock, and the sys_ck can be a simple divider. Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo
Родитель
7171511eae
Коммит
944ee5dc15
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@ -174,10 +174,9 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
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# Clock framework
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obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
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obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
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@ -57,40 +57,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
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static struct clk osc_ck;
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DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
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static const struct clk_ops osc_ck_ops = {
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.recalc_rate = &omap2_osc_clk_recalc,
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DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
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DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
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DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0);
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/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */
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static const char *aplls_clkin_ck_parent_names[] = {
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"virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck",
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};
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static struct clk_hw_omap osc_ck_hw = {
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.hw = {
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.clk = &osc_ck,
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},
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};
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static struct clk osc_ck = {
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.name = "osc_ck",
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.ops = &osc_ck_ops,
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.hw = &osc_ck_hw.hw,
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.flags = CLK_IS_ROOT,
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};
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DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0,
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OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT,
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OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL);
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DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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static struct clk sys_ck;
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DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck,
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0x0, 2, 1);
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static const char *sys_ck_parent_names[] = {
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"osc_ck",
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static const char *osc_ck_parent_names[] = {
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"aplls_clkin_ck", "aplls_clkin_x2_ck",
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};
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static const struct clk_ops sys_ck_ops = {
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.init = &omap2_init_clk_clkdm,
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.recalc_rate = &omap2xxx_sys_clk_recalc,
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};
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DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0,
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OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
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OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL);
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DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
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DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
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DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL,
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OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, NULL);
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static struct dpll_data dpll_dd = {
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.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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@ -1741,6 +1740,12 @@ static struct omap_clk omap2420_clks[] = {
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/* external root sources */
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CLK(NULL, "func_32k_ck", &func_32k_ck),
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CLK(NULL, "secure_32k_ck", &secure_32k_ck),
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CLK(NULL, "virt_12m_ck", &virt_12m_ck),
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CLK(NULL, "virt_13m_ck", &virt_13m_ck),
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CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
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CLK(NULL, "virt_26m_ck", &virt_26m_ck),
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CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck),
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CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck),
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CLK(NULL, "osc_ck", &osc_ck),
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CLK(NULL, "sys_ck", &sys_ck),
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CLK(NULL, "alt_ck", &alt_ck),
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@ -1904,7 +1909,6 @@ static const char *enable_init_clks[] = {
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int __init omap2420_clk_init(void)
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{
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prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
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cpu_mask = RATE_IN_242X;
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rate_table = omap2420_rate_table;
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@ -55,42 +55,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
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static struct clk osc_ck;
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DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
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static const struct clk_ops osc_ck_ops = {
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.enable = &omap2_enable_osc_ck,
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.disable = omap2_disable_osc_ck,
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.recalc_rate = &omap2_osc_clk_recalc,
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DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
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DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
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DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0);
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/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */
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static const char *aplls_clkin_ck_parent_names[] = {
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"virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck",
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};
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static struct clk_hw_omap osc_ck_hw = {
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.hw = {
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.clk = &osc_ck,
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},
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};
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static struct clk osc_ck = {
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.name = "osc_ck",
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.ops = &osc_ck_ops,
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.hw = &osc_ck_hw.hw,
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.flags = CLK_IS_ROOT,
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};
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DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0,
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OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT,
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OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL);
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DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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static struct clk sys_ck;
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DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck,
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0x0, 2, 1);
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static const char *sys_ck_parent_names[] = {
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"osc_ck",
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static const char *osc_ck_parent_names[] = {
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"aplls_clkin_ck", "aplls_clkin_x2_ck",
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};
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static const struct clk_ops sys_ck_ops = {
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.init = &omap2_init_clk_clkdm,
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.recalc_rate = &omap2xxx_sys_clk_recalc,
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};
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DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0,
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OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
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OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL);
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DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
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DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
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DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL,
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OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, NULL);
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static struct dpll_data dpll_dd = {
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.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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@ -1308,7 +1305,11 @@ static struct clk_hw_omap mdm_osc_ck_hw = {
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.clkdm_name = "mdm_clkdm",
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};
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DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
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static const char *mdm_osc_ck_parent_names[] = {
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"osc_ck",
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};
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DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops);
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static struct clk mmchs1_fck;
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@ -1842,6 +1843,12 @@ static struct omap_clk omap2430_clks[] = {
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/* external root sources */
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CLK(NULL, "func_32k_ck", &func_32k_ck),
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CLK(NULL, "secure_32k_ck", &secure_32k_ck),
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CLK(NULL, "virt_12m_ck", &virt_12m_ck),
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CLK(NULL, "virt_13m_ck", &virt_13m_ck),
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CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
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CLK(NULL, "virt_26m_ck", &virt_26m_ck),
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CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck),
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CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck),
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CLK(NULL, "osc_ck", &osc_ck),
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CLK("twl", "fck", &osc_ck),
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CLK(NULL, "sys_ck", &sys_ck),
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@ -2021,7 +2028,6 @@ static const char *enable_init_clks[] = {
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int __init omap2430_clk_init(void)
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{
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prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
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cpu_mask = RATE_IN_243X;
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rate_table = omap2430_rate_table;
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@ -1,69 +0,0 @@
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/*
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* OMAP2xxx osc_clk-specific clock code
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm-regbits-24xx.h"
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/*
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* XXX This does not actually enable the osc_ck, since the osc_ck must
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* be running for this function to be called. Instead, this function
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* is used to disable an autoidle mode on the osc_ck. The existing
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* clk_enable/clk_disable()-based usecounting for osc_ck should be
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* replaced with autoidle-based usecounting.
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*/
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int omap2_enable_osc_ck(struct clk_hw *clk)
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{
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u32 pcc;
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pcc = readl_relaxed(prcm_clksrc_ctrl);
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writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
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return 0;
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}
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/*
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* XXX This does not actually disable the osc_ck, since doing so would
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* immediately halt the system. Instead, this function is used to
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* enable an autoidle mode on the osc_ck. The existing
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* clk_enable/clk_disable()-based usecounting for osc_ck should be
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* replaced with autoidle-based usecounting.
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*/
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void omap2_disable_osc_ck(struct clk_hw *clk)
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{
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u32 pcc;
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pcc = readl_relaxed(prcm_clksrc_ctrl);
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writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
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}
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unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
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unsigned long parent_rate)
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{
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return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
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}
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@ -1,47 +0,0 @@
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/*
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* OMAP2xxx sys_clk-specific clock code
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm-regbits-24xx.h"
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void __iomem *prcm_clksrc_ctrl;
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u32 omap2xxx_get_sysclkdiv(void)
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{
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u32 div;
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div = readl_relaxed(prcm_clksrc_ctrl);
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div &= OMAP_SYSCLKDIV_MASK;
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div >>= OMAP_SYSCLKDIV_SHIFT;
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return div;
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}
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unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
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unsigned long parent_rate)
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{
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return parent_rate / omap2xxx_get_sysclkdiv();
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}
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@ -45,8 +45,6 @@ int omap2430_clk_init(void);
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#define omap2430_clk_init() do { } while(0)
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#endif
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extern void __iomem *prcm_clksrc_ctrl;
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extern struct clk_hw *dclk_hw;
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int omap2_enable_osc_ck(struct clk_hw *hw);
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void omap2_disable_osc_ck(struct clk_hw *hw);
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@ -107,6 +107,7 @@
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#define OMAP24XX_AUTO_DPLL_SHIFT 0
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#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
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#define OMAP24XX_APLLS_CLKIN_SHIFT 23
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#define OMAP24XX_APLLS_CLKIN_WIDTH 3
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#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
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#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
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#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
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@ -249,6 +249,10 @@ static void __init prcm_setup_regs(void)
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/* Enable wake-up events */
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omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
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WKUP_MOD, PM_WKEN);
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/* Enable SYS_CLKEN control when all domains idle */
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omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
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OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
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}
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int __init omap2_pm_init(void)
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