drm/amdgpu: Add place holder for soc15 asic init on emulation
Add common smu_soc_asic_init function to emulate the sillicon post sequence Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
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amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
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amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
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amdgpu-y += \
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amdgpu-y += \
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vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o
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vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o
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# add GMC block
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# add GMC block
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amdgpu-y += \
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amdgpu-y += \
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@ -1657,6 +1657,8 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
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bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
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bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
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bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
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bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
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int emu_soc_asic_init(struct amdgpu_device *adev);
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/*
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/*
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* Registers read & write functions.
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* Registers read & write functions.
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*/
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*/
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@ -1311,19 +1311,6 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
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}
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}
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adev->ip_blocks[i].status.sw = true;
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adev->ip_blocks[i].status.sw = true;
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if (amdgpu_emu_mode == 1) {
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/* Need to do common hw init first on emulation */
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if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
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r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
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if (r) {
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DRM_ERROR("hw_init of IP block <%s> failed %d\n",
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adev->ip_blocks[i].version->funcs->name, r);
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return r;
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}
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adev->ip_blocks[i].status.hw = true;
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}
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}
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/* need to do gmc hw init early so we can allocate gpu mem */
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/* need to do gmc hw init early so we can allocate gpu mem */
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if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
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if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
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r = amdgpu_device_vram_scratch_init(adev);
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r = amdgpu_device_vram_scratch_init(adev);
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@ -1902,8 +1889,11 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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if (runtime)
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if (runtime)
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vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
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vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
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if (amdgpu_emu_mode == 1)
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if (amdgpu_emu_mode == 1) {
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/* post the asic on emulation mode */
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emu_soc_asic_init(adev);
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goto fence_driver_init;
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goto fence_driver_init;
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}
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/* Read BIOS */
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/* Read BIOS */
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if (!amdgpu_get_bios(adev)) {
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if (!amdgpu_get_bios(adev)) {
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@ -0,0 +1,33 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "soc15.h"
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#include "soc15_common.h"
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#include "soc15_hw_ip.h"
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int emu_soc_asic_init(struct amdgpu_device *adev)
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{
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return 0;
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}
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