net: mvpp2: convert to phylink pcs operations
Convert mvpp2 to phylink's new pcs support. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King
David S. Miller
Родитель
82b1c8fae8
Коммит
94bfe438bc
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@ -967,6 +967,7 @@ struct mvpp2_port {
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phy_interface_t phy_interface;
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struct phylink *phylink;
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struct phylink_config phylink_config;
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struct phylink_pcs phylink_pcs;
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struct phy *comphy;
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struct mvpp2_bm_pool *pool_long;
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@ -1479,8 +1479,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port,
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else
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val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
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if (phy_interface_mode_is_8023z(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII)
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if (phy_interface_mode_is_8023z(state->interface) ||
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state->interface == PHY_INTERFACE_MODE_SGMII)
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val |= MVPP2_GMAC_PCS_LB_EN_MASK;
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else
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val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
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@ -5376,6 +5376,174 @@ static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
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return container_of(config, struct mvpp2_port, phylink_config);
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}
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static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mvpp2_port, phylink_pcs);
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}
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static void mvpp22_xlg_pcs_get_state(struct mvpp2_port *port,
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struct phylink_link_state *state)
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{
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u32 val;
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state->speed = SPEED_10000;
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state->duplex = 1;
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state->an_complete = 1;
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val = readl(port->base + MVPP22_XLG_STATUS);
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state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
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state->pause = 0;
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val = readl(port->base + MVPP22_XLG_CTRL0_REG);
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if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
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state->pause |= MLO_PAUSE_TX;
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if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
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state->pause |= MLO_PAUSE_RX;
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}
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static void mvpp2_gmac_pcs_get_state(struct mvpp2_port *port,
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struct phylink_link_state *state)
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{
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u32 val;
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val = readl(port->base + MVPP2_GMAC_STATUS0);
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state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
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state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
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state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_1000BASEX:
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state->speed = SPEED_1000;
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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state->speed = SPEED_2500;
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break;
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default:
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if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
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state->speed = SPEED_1000;
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else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
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state->speed = SPEED_100;
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else
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state->speed = SPEED_10;
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}
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state->pause = 0;
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if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
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state->pause |= MLO_PAUSE_RX;
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if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
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state->pause |= MLO_PAUSE_TX;
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}
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static void mvpp2_phylink_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
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u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
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mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
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if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
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mvpp22_xlg_pcs_get_state(port, state);
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return;
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}
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}
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mvpp2_gmac_pcs_get_state(port, state);
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}
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static int mvpp2_gmac_pcs_config(struct mvpp2_port *port, unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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u32 mask, val, an, old_an, changed;
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mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
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MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_AN_SPEED_EN |
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MVPP2_GMAC_FLOW_CTRL_AUTONEG |
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MVPP2_GMAC_AN_DUPLEX_EN;
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if (phylink_autoneg_inband(mode)) {
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mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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val = MVPP2_GMAC_IN_BAND_AUTONEG;
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if (interface == PHY_INTERFACE_MODE_SGMII) {
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/* SGMII mode receives the speed and duplex from PHY */
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val |= MVPP2_GMAC_AN_SPEED_EN |
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MVPP2_GMAC_AN_DUPLEX_EN;
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} else {
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/* 802.3z mode has fixed speed and duplex */
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val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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/* The FLOW_CTRL_AUTONEG bit selects either the hardware
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* automatically or the bits in MVPP22_GMAC_CTRL_4_REG
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* manually controls the GMAC pause modes.
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*/
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if (permit_pause_to_mac)
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val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
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/* Configure advertisement bits */
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mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
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if (phylink_test(advertising, Pause))
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val |= MVPP2_GMAC_FC_ADV_EN;
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if (phylink_test(advertising, Asym_Pause))
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val |= MVPP2_GMAC_FC_ADV_ASM_EN;
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}
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} else {
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val = 0;
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}
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old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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an = (an & ~mask) | val;
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changed = an ^ old_an;
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if (changed)
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writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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/* We are only interested in the advertisement bits changing */
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return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
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}
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static int mvpp2_phylink_pcs_config(struct phylink_pcs *pcs,
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unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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int ret;
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if (mvpp2_is_xlg(interface))
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ret = 0;
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else
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ret = mvpp2_gmac_pcs_config(port, mode, interface, advertising,
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permit_pause_to_mac);
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return ret;
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}
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static void mvpp2_phylink_pcs_an_restart(struct phylink_pcs *pcs)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
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port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
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port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static const struct phylink_pcs_ops mvpp2_phylink_pcs_ops = {
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.pcs_get_state = mvpp2_phylink_pcs_get_state,
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.pcs_config = mvpp2_phylink_pcs_config,
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.pcs_an_restart = mvpp2_phylink_pcs_an_restart,
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};
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static void mvpp2_phylink_validate(struct phylink_config *config,
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unsigned long *supported,
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struct phylink_link_state *state)
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@ -5464,89 +5632,6 @@ empty_set:
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bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
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}
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static void mvpp22_xlg_pcs_get_state(struct mvpp2_port *port,
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struct phylink_link_state *state)
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{
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u32 val;
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state->speed = SPEED_10000;
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state->duplex = 1;
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state->an_complete = 1;
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val = readl(port->base + MVPP22_XLG_STATUS);
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state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
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state->pause = 0;
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val = readl(port->base + MVPP22_XLG_CTRL0_REG);
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if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
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state->pause |= MLO_PAUSE_TX;
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if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
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state->pause |= MLO_PAUSE_RX;
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}
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static void mvpp2_gmac_pcs_get_state(struct mvpp2_port *port,
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struct phylink_link_state *state)
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{
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u32 val;
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val = readl(port->base + MVPP2_GMAC_STATUS0);
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state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
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state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
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state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_1000BASEX:
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state->speed = SPEED_1000;
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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state->speed = SPEED_2500;
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break;
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default:
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if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
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state->speed = SPEED_1000;
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else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
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state->speed = SPEED_100;
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else
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state->speed = SPEED_10;
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}
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state->pause = 0;
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if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
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state->pause |= MLO_PAUSE_RX;
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if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
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state->pause |= MLO_PAUSE_TX;
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}
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static void mvpp2_phylink_mac_pcs_get_state(struct phylink_config *config,
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struct phylink_link_state *state)
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{
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struct mvpp2_port *port = mvpp2_phylink_to_port(config);
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if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
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u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
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mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
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if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
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mvpp22_xlg_pcs_get_state(port, state);
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return;
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}
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}
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mvpp2_gmac_pcs_get_state(port, state);
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}
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static void mvpp2_mac_an_restart(struct phylink_config *config)
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{
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struct mvpp2_port *port = mvpp2_phylink_to_port(config);
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u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
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port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
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port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
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const struct phylink_link_state *state)
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{
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@ -5570,20 +5655,14 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
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static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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const struct phylink_link_state *state)
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{
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u32 old_an, an;
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u32 old_ctrl0, ctrl0;
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u32 old_ctrl2, ctrl2;
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u32 old_ctrl4, ctrl4;
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old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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an &= ~(MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
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MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
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MVPP2_GMAC_AN_DUPLEX_EN | MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
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ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
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@ -5607,12 +5686,6 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
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}
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/* Configure advertisement bits */
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if (phylink_test(state->advertising, Pause))
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an |= MVPP2_GMAC_FC_ADV_EN;
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if (phylink_test(state->advertising, Asym_Pause))
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an |= MVPP2_GMAC_FC_ADV_ASM_EN;
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/* Configure negotiation style */
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if (!phylink_autoneg_inband(mode)) {
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/* Phy or fixed speed - no in-band AN, nothing to do, leave the
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@ -5621,12 +5694,6 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
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/* SGMII in-band mode receives the speed and duplex from
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* the PHY. Flow control information is not received. */
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an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX);
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an |= MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_AN_SPEED_EN |
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MVPP2_GMAC_AN_DUPLEX_EN;
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} else if (phy_interface_mode_is_8023z(state->interface)) {
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/* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
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* they negotiate duplex: they are always operating with a fixed
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@ -5634,15 +5701,6 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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* speed and full duplex here.
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*/
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ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
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an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX);
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an |= MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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if (state->pause & MLO_PAUSE_AN && state->an_enabled)
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an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
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}
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if (old_ctrl0 != ctrl0)
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@ -5651,8 +5709,6 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
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if (old_ctrl4 != ctrl4)
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writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
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if (old_an != an)
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writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
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@ -5861,8 +5917,6 @@ static void mvpp2_mac_link_down(struct phylink_config *config,
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static const struct phylink_mac_ops mvpp2_phylink_ops = {
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.validate = mvpp2_phylink_validate,
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.mac_pcs_get_state = mvpp2_phylink_mac_pcs_get_state,
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.mac_an_restart = mvpp2_mac_an_restart,
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.mac_prepare = mvpp2_mac_prepare,
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.mac_config = mvpp2_mac_config,
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.mac_finish = mvpp2_mac_finish,
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@ -5883,6 +5937,9 @@ static void mvpp2_acpi_start(struct mvpp2_port *port)
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mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND,
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port->phy_interface);
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mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
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mvpp2_phylink_pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
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port->phy_interface, state.advertising,
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false);
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mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
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port->phy_interface);
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mvpp2_mac_link_up(&port->phylink_config, NULL,
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@ -6114,6 +6171,9 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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goto err_free_port_pcpu;
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}
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port->phylink = phylink;
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port->phylink_pcs.ops = &mvpp2_phylink_pcs_ops;
|
||||
phylink_set_pcs(phylink, &port->phylink_pcs);
|
||||
} else {
|
||||
port->phylink = NULL;
|
||||
}
|
||||
|
|
|
|||
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Ссылка в новой задаче