Merge branches 'depends/asoc', 'renesas/boards', 'renesas/soc' and 'renesas/soc2' into next/boards2
These are all dependencies for the next set of renesas shmobile board changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
94c78a55b8
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@ -728,7 +728,7 @@ fsia_ick_out:
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static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
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{
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struct clk *fsib_clk;
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struct clk *fdiv_clk = &sh7372_fsidivb_clk;
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struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
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long fsib_rate = 0;
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long fdiv_rate = 0;
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int ackmd_bpfmd;
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@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
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static int fsi_b_set_rate(struct device *dev, int rate, int enable)
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{
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struct clk *fsib_clk;
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struct clk *fdiv_clk = &sh7372_fsidivb_clk;
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struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
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long fsib_rate = 0;
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long fdiv_rate = 0;
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int ackmd_bpfmd;
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@ -65,6 +65,9 @@
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#define SMSTPCR3 IOMEM(0xe615013c)
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#define SMSTPCR4 IOMEM(0xe6150140)
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#define FSIDIVA IOMEM(0xFE1F8000)
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#define FSIDIVB IOMEM(0xFE1F8008)
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/* Fixed 32 KHz root clock from EXTALR pin */
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static struct clk extalr_clk = {
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.rate = 32768,
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@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = {
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};
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/* USB clock */
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/*
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* USBCKCR is controlling usb24 clock
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* bit[7] : parent clock
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* bit[6] : clock divide rate
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* And this bit[7] is used as a "usb24s" from other devices.
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* (Video clock / Sub clock / SPU clock)
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* You can controll this clock as a below.
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*
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* struct clk *usb24 = clk_get(dev, "usb24");
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* struct clk *usb24s = clk_get(NULL, "usb24s");
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* struct clk *system = clk_get(NULL, "system_clk");
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* int rate = clk_get_rate(system);
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*
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* clk_set_parent(usb24s, system); // for bit[7]
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* clk_set_rate(usb24, rate / 2); // for bit[6]
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*/
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static struct clk *usb24s_parents[] = {
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[0] = &system_clk,
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[1] = &extal2_clk
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@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = {
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&hdmi2_clk,
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};
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/* FSI DIV */
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enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
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static struct clk fsidivs[] = {
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[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
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[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
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};
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/* MSTP */
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enum {
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DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
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@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
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CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
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CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
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CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
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CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
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CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
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};
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void __init r8a7740_clock_init(u8 md_ck)
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@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck)
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for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
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ret = clk_register(late_main_clks[k]);
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if (!ret)
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ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = {
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};
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enum { MSTP323, MSTP322, MSTP321, MSTP320,
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MSTP101, MSTP100,
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MSTP030,
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MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015, MSTP014,
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@ -98,6 +99,8 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
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[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
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[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
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[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */
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[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */
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[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
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[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
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[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
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@ -153,6 +156,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
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CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
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CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
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CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
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CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
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@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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};
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/* FSI DIV */
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static unsigned long fsidiv_recalc(struct clk *clk)
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{
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unsigned long value;
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enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
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value = __raw_readl(clk->mapping->base);
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value >>= 16;
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if (value < 2)
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return 0;
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return clk->parent->rate / value;
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}
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static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_div_range_round(clk, 2, 0xffff, rate);
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}
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static void fsidiv_disable(struct clk *clk)
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{
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__raw_writel(0, clk->mapping->base);
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}
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static int fsidiv_enable(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base) >> 16;
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if (value < 2)
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return -EIO;
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__raw_writel((value << 16) | 0x3, clk->mapping->base);
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return 0;
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}
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static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
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{
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int idx;
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idx = (clk->parent->rate / rate) & 0xffff;
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if (idx < 2)
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return -EINVAL;
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__raw_writel(idx << 16, clk->mapping->base);
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return 0;
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}
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static struct sh_clk_ops fsidiv_clk_ops = {
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.recalc = fsidiv_recalc,
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.round_rate = fsidiv_round_rate,
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.set_rate = fsidiv_set_rate,
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.enable = fsidiv_enable,
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.disable = fsidiv_disable,
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};
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static struct clk_mapping fsidiva_clk_mapping = {
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.phys = FSIDIVA,
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.len = 8,
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};
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struct clk sh7372_fsidiva_clk = {
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.ops = &fsidiv_clk_ops,
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.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
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.mapping = &fsidiva_clk_mapping,
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};
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static struct clk_mapping fsidivb_clk_mapping = {
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.phys = FSIDIVB,
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.len = 8,
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};
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struct clk sh7372_fsidivb_clk = {
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.ops = &fsidiv_clk_ops,
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.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
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.mapping = &fsidivb_clk_mapping,
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};
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static struct clk *late_main_clks[] = {
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&sh7372_fsidiva_clk,
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&sh7372_fsidivb_clk,
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static struct clk fsidivs[] = {
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[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
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[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
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};
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enum { MSTP001, MSTP000,
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@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
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CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
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CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
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CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
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CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),
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/* DIV4 clocks */
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CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
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@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
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CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
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CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
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CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
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CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
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CLKDEV_ICK_ID("xcka", "sh_fsi2", &sh7372_fsiack_clk),
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CLKDEV_ICK_ID("xckb", "sh_fsi2", &sh7372_fsibck_clk),
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};
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void __init sh7372_clock_init(void)
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@ -706,8 +636,8 @@ void __init sh7372_clock_init(void)
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
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ret = clk_register(late_main_clks[k]);
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if (!ret)
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ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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@ -71,7 +71,7 @@ enum {
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GPIO_FN_A19,
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/* IPSR0 */
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GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
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GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
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GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
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GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
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GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
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@ -479,8 +479,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
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extern struct clk sh7372_pllc2_clk;
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extern struct clk sh7372_fsiack_clk;
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extern struct clk sh7372_fsibck_clk;
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extern struct clk sh7372_fsidiva_clk;
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extern struct clk sh7372_fsidivb_clk;
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extern void sh7372_intcs_suspend(void);
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extern void sh7372_intcs_resume(void);
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@ -140,7 +140,7 @@ enum {
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FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
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FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
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FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
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FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
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FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
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FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
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/* GPSR5 */
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@ -176,7 +176,7 @@ enum {
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FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
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FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
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FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
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FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
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FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
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FN_SCIF_CLK, FN_TCLK0_C,
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/* IPSR1 */
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@ -447,7 +447,7 @@ enum {
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A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
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BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
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ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
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PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
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USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
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SCIF_CLK_MARK, TCLK0_C_MARK,
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EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
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@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
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PINMUX_DATA(A18_MARK, FN_A18),
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PINMUX_DATA(A19_MARK, FN_A19),
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PINMUX_IPSR_DATA(IP0_2_0, PENC2),
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PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
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PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
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PINMUX_IPSR_DATA(IP0_2_0, PWM1),
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PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
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@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
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GPIO_FN(A19),
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/* IPSR0 */
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GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
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GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
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GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
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GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
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GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
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@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_4_30_FN, FN_IP8_18,
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GP_4_29_FN, FN_IP8_17_16,
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GP_4_28_FN, FN_IP0_2_0,
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GP_4_27_FN, FN_PENC1,
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GP_4_26_FN, FN_PENC0,
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GP_4_27_FN, FN_USB_PENC1,
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GP_4_26_FN, FN_USB_PENC0,
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GP_4_25_FN, FN_IP8_15_12,
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GP_4_24_FN, FN_IP8_11_8,
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GP_4_23_FN, FN_IP8_7_4,
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@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
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FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
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/* IP0_2_0 [3] */
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FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
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FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
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FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
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},
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{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
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@ -361,3 +361,89 @@ int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
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return sh_clk_div_register_ops(clks, nr, table,
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&sh_clk_div4_reparent_clk_ops);
|
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}
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||||
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/* FSI-DIV */
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||||
static unsigned long fsidiv_recalc(struct clk *clk)
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{
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||||
u32 value;
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||||
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||||
value = __raw_readl(clk->mapping->base);
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||||
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value >>= 16;
|
||||
if (value < 2)
|
||||
return clk->parent->rate;
|
||||
|
||||
return clk->parent->rate / value;
|
||||
}
|
||||
|
||||
static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
return clk_rate_div_range_round(clk, 1, 0xffff, rate);
|
||||
}
|
||||
|
||||
static void fsidiv_disable(struct clk *clk)
|
||||
{
|
||||
__raw_writel(0, clk->mapping->base);
|
||||
}
|
||||
|
||||
static int fsidiv_enable(struct clk *clk)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = __raw_readl(clk->mapping->base) >> 16;
|
||||
if (value < 2)
|
||||
return 0;
|
||||
|
||||
__raw_writel((value << 16) | 0x3, clk->mapping->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 val;
|
||||
int idx;
|
||||
|
||||
idx = (clk->parent->rate / rate) & 0xffff;
|
||||
if (idx < 2)
|
||||
__raw_writel(0, clk->mapping->base);
|
||||
else
|
||||
__raw_writel(idx << 16, clk->mapping->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops fsidiv_clk_ops = {
|
||||
.recalc = fsidiv_recalc,
|
||||
.round_rate = fsidiv_round_rate,
|
||||
.set_rate = fsidiv_set_rate,
|
||||
.enable = fsidiv_enable,
|
||||
.disable = fsidiv_disable,
|
||||
};
|
||||
|
||||
int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
|
||||
{
|
||||
struct clk_mapping *map;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nr; i++) {
|
||||
|
||||
map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
|
||||
if (!map) {
|
||||
pr_err("%s: unable to alloc memory\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* clks[i].enable_reg came from SH_CLK_FSIDIV() */
|
||||
map->phys = (phys_addr_t)clks[i].enable_reg;
|
||||
map->len = 8;
|
||||
|
||||
clks[i].enable_reg = 0; /* remove .enable_reg */
|
||||
clks[i].ops = &fsidiv_clk_ops;
|
||||
clks[i].mapping = map;
|
||||
|
||||
clk_register(&clks[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -199,4 +199,13 @@ int sh_clk_div6_reparent_register(struct clk *clks, int nr);
|
|||
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
|
||||
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
|
||||
|
||||
/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
|
||||
#define SH_CLK_FSIDIV(_reg, _parent) \
|
||||
{ \
|
||||
.enable_reg = (void __iomem *)_reg, \
|
||||
.parent = _parent, \
|
||||
}
|
||||
|
||||
int sh_clk_fsidiv_register(struct clk *clks, int nr);
|
||||
|
||||
#endif /* __SH_CLOCK_H */
|
||||
|
|
|
|||
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