serial: 8250_uniphier: hardcode regshift to avoid unneeded memory read
For this driver, uart_port::regshift is always 2. Hardcode the shift value instead of reading ->regshift to get an already known value. (pointed out by Denys Vlasenko) Furthermore, I am using register macros that are already shifted, which will save code a bit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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5131dcd781
Коммит
94cbb6978b
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@ -24,10 +24,22 @@
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/* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */
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#define UNIPHIER_UART_DEFAULT_FIFO_SIZE 64
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#define UNIPHIER_UART_CHAR_FCR 3 /* Character / FIFO Control Register */
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#define UNIPHIER_UART_LCR_MCR 4 /* Line/Modem Control Register */
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#define UNIPHIER_UART_LCR_SHIFT 8
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#define UNIPHIER_UART_DLR 9 /* Divisor Latch Register */
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/*
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* This hardware is similar to 8250, but its register map is a bit different:
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* - MMIO32 (regshift = 2)
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* - FCR is not at 2, but 3
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* - LCR and MCR are not at 3 and 4, they share 4
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* - Divisor latch at 9, no divisor latch access bit
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*/
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#define UNIPHIER_UART_REGSHIFT 2
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/* bit[15:8] = CHAR (not used), bit[7:0] = FCR */
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#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
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/* bit[15:8] = LCR, bit[7:0] = MCR */
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#define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT))
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/* Divisor Latch Register */
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#define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT))
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struct uniphier8250_priv {
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int line;
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@ -44,7 +56,7 @@ static int __init uniphier_early_console_setup(struct earlycon_device *device,
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/* This hardware always expects MMIO32 register interface. */
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device->port.iotype = UPIO_MEM32;
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device->port.regshift = 2;
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device->port.regshift = UNIPHIER_UART_REGSHIFT;
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/*
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* Do not touch the divisor register in early_serial8250_setup();
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@ -68,17 +80,16 @@ static unsigned int uniphier_serial_in(struct uart_port *p, int offset)
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switch (offset) {
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case UART_LCR:
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valshift = UNIPHIER_UART_LCR_SHIFT;
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valshift = 8;
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/* fall through */
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case UART_MCR:
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offset = UNIPHIER_UART_LCR_MCR;
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break;
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default:
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offset <<= UNIPHIER_UART_REGSHIFT;
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break;
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}
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offset <<= p->regshift;
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/*
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* The return value must be masked with 0xff because LCR and MCR reside
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* in the same register that must be accessed by 32-bit write/read.
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@ -97,7 +108,7 @@ static void uniphier_serial_out(struct uart_port *p, int offset, int value)
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offset = UNIPHIER_UART_CHAR_FCR;
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break;
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case UART_LCR:
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valshift = UNIPHIER_UART_LCR_SHIFT;
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valshift = 8;
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/* Divisor latch access bit does not exist. */
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value &= ~UART_LCR_DLAB;
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/* fall through */
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@ -106,11 +117,10 @@ static void uniphier_serial_out(struct uart_port *p, int offset, int value)
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break;
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default:
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normal = true;
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offset <<= UNIPHIER_UART_REGSHIFT;
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break;
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}
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offset <<= p->regshift;
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if (normal) {
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writel(value, p->membase + offset);
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} else {
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@ -139,16 +149,12 @@ static void uniphier_serial_out(struct uart_port *p, int offset, int value)
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*/
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static int uniphier_serial_dl_read(struct uart_8250_port *up)
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{
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int offset = UNIPHIER_UART_DLR << up->port.regshift;
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return readl(up->port.membase + offset);
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return readl(up->port.membase + UNIPHIER_UART_DLR);
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}
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static void uniphier_serial_dl_write(struct uart_8250_port *up, int value)
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{
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int offset = UNIPHIER_UART_DLR << up->port.regshift;
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writel(value, up->port.membase + offset);
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writel(value, up->port.membase + UNIPHIER_UART_DLR);
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}
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static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port,
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@ -234,7 +240,7 @@ static int uniphier_uart_probe(struct platform_device *pdev)
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up.port.type = PORT_16550A;
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up.port.iotype = UPIO_MEM32;
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up.port.regshift = 2;
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up.port.regshift = UNIPHIER_UART_REGSHIFT;
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up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE;
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up.capabilities = UART_CAP_FIFO;
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