ARM: dts: Add ethernet to a bunch of platforms
These platforms have the PHY defined already so we just need to add a single device node to each of them to activate the ethernet device. The PHY skew/delay settings for pin control is known from a few vendor trees and old OpenWRT patch sets. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -214,6 +214,56 @@
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groups = "gpio1dgrp";
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};
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};
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pinctrl-gmii {
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mux {
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function = "gmii";
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groups = "gmii_gmac0_grp";
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};
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/*
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* In the vendor Linux tree, these values are set for the C3
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* version of the SL3512 ASIC with the comment "benson suggest"
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*/
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conf0 {
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pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
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skew-delay = <0>;
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};
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conf1 {
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pins = "T8 GMAC0 RXC";
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skew-delay = <10>;
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};
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conf2 {
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pins = "T11 GMAC1 RXC";
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skew-delay = <15>;
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};
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conf3 {
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pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
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skew-delay = <7>;
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};
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conf4 {
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pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC";
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skew-delay = <10>;
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};
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conf5 {
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/* The data lines all have default skew */
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pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
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"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
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"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
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"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
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"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
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"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
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skew-delay = <7>;
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};
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conf6 {
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pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
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"R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
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skew-delay = <5>;
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};
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/* Set up drive strength on GMAC0 to 16 mA */
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conf7 {
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groups = "gmii_gmac0_grp";
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drive-strength = <16>;
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};
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};
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};
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};
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@ -234,6 +284,18 @@
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pinctrl-0 = <&gpio1_default_pins>;
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};
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ethernet@60000000 {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet-port@1 {
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/* Not used in this platform */
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};
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};
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ata@63000000 {
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status = "okay";
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};
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@ -129,6 +129,50 @@
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groups = "gpio1dgrp";
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};
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};
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pinctrl-gmii {
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mux {
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function = "gmii";
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groups = "gmii_gmac0_grp";
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};
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/* Settings come from OpenWRT */
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conf0 {
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pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
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skew-delay = <0>;
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};
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conf1 {
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pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC";
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skew-delay = <15>;
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};
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conf2 {
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pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
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skew-delay = <7>;
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};
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conf3 {
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pins = "V7 GMAC0 TXC";
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skew-delay = <11>;
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};
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conf4 {
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pins = "P10 GMAC1 TXC";
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skew-delay = <10>;
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};
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conf5 {
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/* The data lines all have default skew */
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pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
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"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
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"U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
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"R7 GMAC0 TXD2", "P7 GMAC0 TXD3",
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"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
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"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
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"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
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"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
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skew-delay = <7>;
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};
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/* Set up drive strength on GMAC0 to 16 mA */
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conf6 {
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groups = "gmii_gmac0_grp";
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drive-strength = <16>;
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};
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};
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};
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};
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@ -143,6 +187,18 @@
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pinctrl-0 = <&gpio1_default_pins>;
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};
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ethernet@60000000 {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet-port@1 {
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/* Not used in this platform */
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};
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};
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ata@63000000 {
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status = "okay";
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};
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@ -114,5 +114,17 @@
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pinctrl-names = "default";
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pinctrl-0 = <&gpio1_default_pins>;
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};
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ethernet@60000000 {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet-port@1 {
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/* Not used in this platform */
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};
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};
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};
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};
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@ -160,5 +160,17 @@
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<0x6000 0 0 3 &pci_intc 1>,
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<0x6000 0 0 4 &pci_intc 2>;
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};
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ethernet@60000000 {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet-port@1 {
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/* Not used in this platform */
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};
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};
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};
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};
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@ -136,6 +136,13 @@
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"gpio0bgrp";
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};
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};
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pinctrl-gmii {
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/* This platform use both the ethernet ports */
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mux {
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function = "gmii";
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groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
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};
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};
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};
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};
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@ -165,5 +172,18 @@
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<0x6000 0 0 3 &pci_intc 1>,
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<0x6000 0 0 4 &pci_intc 2>;
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};
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ethernet@60000000 {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet-port@1 {
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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};
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};
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