powerpc/smp: Add support detecting thread-groups sharing L2 cache
On POWER systems, groups of threads within a core sharing the L2-cache
can be indicated by the "ibm,thread-groups" property array with the
identifier "2".
This patch adds support for detecting this, and when present, populate
the populating the cpu_l2_cache_mask of every CPU to the core-siblings
which share L2 with the CPU as specified in the by the
"ibm,thread-groups" property array.
On a platform with the following "ibm,thread-group" configuration
00000001 00000002 00000004 00000000
00000002 00000004 00000006 00000001
00000003 00000005 00000007 00000002
00000002 00000004 00000000 00000002
00000004 00000006 00000001 00000003
00000005 00000007
Without this patch, the sched-domain hierarchy for CPUs 0,1 would be
CPU0 attaching sched-domain(s):
domain-0: span=0,2,4,6 level=SMT
domain-1: span=0-7 level=CACHE
domain-2: span=0-15,24-39,48-55 level=MC
domain-3: span=0-55 level=DIE
CPU1 attaching sched-domain(s):
domain-0: span=1,3,5,7 level=SMT
domain-1: span=0-7 level=CACHE
domain-2: span=0-15,24-39,48-55 level=MC
domain-3: span=0-55 level=DIE
The CACHE domain at 0-7 is incorrect since the ibm,thread-groups
sub-array
[00000002 00000002 00000004
00000000 00000002 00000004 00000006
00000001 00000003 00000005 00000007]
indicates that L2 (Property "2") is shared only between the threads of a single
group. There are "2" groups of threads where each group contains "4"
threads each. The groups being {0,2,4,6} and {1,3,5,7}.
With this patch, the sched-domain hierarchy for CPUs 0,1 would be
CPU0 attaching sched-domain(s):
domain-0: span=0,2,4,6 level=SMT
domain-1: span=0-15,24-39,48-55 level=MC
domain-2: span=0-55 level=DIE
CPU1 attaching sched-domain(s):
domain-0: span=1,3,5,7 level=SMT
domain-1: span=0-15,24-39,48-55 level=MC
domain-2: span=0-55 level=DIE
The CACHE domain with span=0,2,4,6 for CPU 0 (span=1,3,5,7 for CPU 1
resp.) gets degenerated into the SMT domain. Furthermore, the
last-level-cache domain gets correctly set to the SMT sched-domain.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1607596739-32439-5-git-send-email-ego@linux.vnet.ibm.com
This commit is contained in:
Gautham R. Shenoy
Michael Ellerman
Родитель
fbd2b672e9
Коммит
9538abee18
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@ -134,6 +134,7 @@ static inline struct cpumask *cpu_smallcore_mask(int cpu)
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extern int cpu_to_core_id(int cpu);
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extern bool has_big_cores;
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extern bool thread_group_shares_l2;
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#define cpu_smt_mask cpu_smt_mask
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#ifdef CONFIG_SCHED_SMT
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@ -187,6 +188,7 @@ extern void __cpu_die(unsigned int cpu);
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/* for UP */
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#define hard_smp_processor_id() get_hard_smp_processor_id(0)
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#define smp_setup_cpu_maps()
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#define thread_group_shares_l2 0
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static inline void inhibit_secondary_onlining(void) {}
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static inline void uninhibit_secondary_onlining(void) {}
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static inline const struct cpumask *cpu_sibling_mask(int cpu)
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@ -76,6 +76,7 @@ static DEFINE_PER_CPU(int, cpu_state) = { 0 };
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struct task_struct *secondary_current;
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bool has_big_cores;
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bool coregroup_enabled;
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bool thread_group_shares_l2;
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DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
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DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
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@ -99,6 +100,7 @@ enum {
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#define MAX_THREAD_LIST_SIZE 8
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#define THREAD_GROUP_SHARE_L1 1
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#define THREAD_GROUP_SHARE_L2 2
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struct thread_groups {
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unsigned int property;
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unsigned int nr_groups;
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@ -107,7 +109,7 @@ struct thread_groups {
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};
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/* Maximum number of properties that groups of threads within a core can share */
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#define MAX_THREAD_GROUP_PROPERTIES 1
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#define MAX_THREAD_GROUP_PROPERTIES 2
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struct thread_groups_list {
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unsigned int nr_properties;
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@ -121,6 +123,13 @@ static struct thread_groups_list tgl[NR_CPUS] __initdata;
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*/
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DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
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/*
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* On some big-cores system, thread_group_l2_cache_map for each CPU
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* corresponds to the set its siblings within the core that share the
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* L2-cache.
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*/
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DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map);
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/* SMP operations for this machine */
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struct smp_ops_t *smp_ops;
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@ -718,7 +727,9 @@ static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
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*
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* ibm,thread-groups[i + 0] tells us the property based on which the
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* threads are being grouped together. If this value is 1, it implies
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* that the threads in the same group share L1, translation cache.
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* that the threads in the same group share L1, translation cache. If
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* the value is 2, it implies that the threads in the same group share
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* the same L2 cache.
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*
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* ibm,thread-groups[i+1] tells us how many such thread groups exist for the
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* property ibm,thread-groups[i]
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@ -872,9 +883,10 @@ static int __init init_thread_group_cache_map(int cpu, int cache_property)
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int first_thread = cpu_first_thread_sibling(cpu);
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int i, cpu_group_start = -1, err = 0;
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struct thread_groups *tg = NULL;
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cpumask_var_t *mask;
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cpumask_var_t *mask = NULL;
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if (cache_property != THREAD_GROUP_SHARE_L1)
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if (cache_property != THREAD_GROUP_SHARE_L1 &&
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cache_property != THREAD_GROUP_SHARE_L2)
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return -EINVAL;
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tg = get_thread_groups(cpu, cache_property, &err);
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@ -888,7 +900,11 @@ static int __init init_thread_group_cache_map(int cpu, int cache_property)
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return -ENODATA;
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}
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mask = &per_cpu(thread_group_l1_cache_map, cpu);
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if (cache_property == THREAD_GROUP_SHARE_L1)
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mask = &per_cpu(thread_group_l1_cache_map, cpu);
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else if (cache_property == THREAD_GROUP_SHARE_L2)
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mask = &per_cpu(thread_group_l2_cache_map, cpu);
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zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
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for (i = first_thread; i < first_thread + threads_per_core; i++) {
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@ -990,6 +1006,16 @@ static int init_big_cores(void)
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}
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has_big_cores = true;
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for_each_possible_cpu(cpu) {
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int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2);
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if (err)
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return err;
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}
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thread_group_shares_l2 = true;
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pr_debug("L2 cache only shared by the threads in the small core\n");
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return 0;
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}
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@ -1304,6 +1330,28 @@ static bool update_mask_by_l2(int cpu, cpumask_var_t *mask)
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if (has_big_cores)
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submask_fn = cpu_smallcore_mask;
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/*
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* If the threads in a thread-group share L2 cache, then the
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* L2-mask can be obtained from thread_group_l2_cache_map.
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*/
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if (thread_group_shares_l2) {
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cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu));
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for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) {
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if (cpu_online(i))
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set_cpus_related(i, cpu, cpu_l2_cache_mask);
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}
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/* Verify that L1-cache siblings are a subset of L2 cache-siblings */
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if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) &&
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!cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) {
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pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n",
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cpu);
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}
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return true;
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}
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l2_cache = cpu_to_l2cache(cpu);
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if (!l2_cache || !*mask) {
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/* Assume only core siblings share cache with this CPU */
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