RDMA/bnxt_re: Refactor notification queue management code
Cleaning up the notification queue data structures and management code. The CQ and SRQ event handlers have been type defined instead of in-place declaration. NQ doorbell register descriptor has been added in base NQ structure. The nq->vector has been renamed to nq->msix_vec. Link: https://lore.kernel.org/r/1581786665-23705-7-git-send-email-devesh.sharma@broadcom.com Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Devesh Sharma
Jason Gunthorpe
Родитель
cee0c7bba4
Коммит
9555352bac
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@ -236,16 +236,16 @@ fail:
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static void bnxt_qplib_service_nq(unsigned long data)
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{
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struct bnxt_qplib_nq *nq = (struct bnxt_qplib_nq *)data;
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bool gen_p5 = bnxt_qplib_is_chip_gen_p5(nq->res->cctx);
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struct bnxt_qplib_hwq *hwq = &nq->hwq;
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struct nq_base *nqe, **nq_ptr;
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struct bnxt_qplib_cq *cq;
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int num_cqne_processed = 0;
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int num_srqne_processed = 0;
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u32 sw_cons, raw_cons;
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u16 type;
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int budget = nq->budget;
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u32 sw_cons, raw_cons;
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uintptr_t q_handle;
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bool gen_p5 = bnxt_qplib_is_chip_gen_p5(nq->res->cctx);
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u16 type;
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/* Service the NQ until empty */
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raw_cons = hwq->cons;
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@ -314,7 +314,7 @@ static void bnxt_qplib_service_nq(unsigned long data)
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}
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if (hwq->cons != raw_cons) {
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hwq->cons = raw_cons;
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bnxt_qplib_ring_nq_db_rearm(nq->bar_reg_iomem, hwq->cons,
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bnxt_qplib_ring_nq_db_rearm(nq->nq_db.db, hwq->cons,
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hwq->max_elements, nq->ring_id,
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gen_p5);
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}
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@ -333,7 +333,7 @@ static irqreturn_t bnxt_qplib_nq_irq(int irq, void *dev_instance)
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prefetch(&nq_ptr[NQE_PG(sw_cons)][NQE_IDX(sw_cons)]);
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/* Fan out to CPU affinitized kthreads? */
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tasklet_schedule(&nq->worker);
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tasklet_schedule(&nq->nq_tasklet);
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return IRQ_HANDLED;
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}
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@ -341,17 +341,17 @@ static irqreturn_t bnxt_qplib_nq_irq(int irq, void *dev_instance)
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void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill)
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{
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bool gen_p5 = bnxt_qplib_is_chip_gen_p5(nq->res->cctx);
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tasklet_disable(&nq->worker);
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tasklet_disable(&nq->nq_tasklet);
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/* Mask h/w interrupt */
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bnxt_qplib_ring_nq_db(nq->bar_reg_iomem, nq->hwq.cons,
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bnxt_qplib_ring_nq_db(nq->nq_db.db, nq->hwq.cons,
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nq->hwq.max_elements, nq->ring_id, gen_p5);
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/* Sync with last running IRQ handler */
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synchronize_irq(nq->vector);
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synchronize_irq(nq->msix_vec);
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if (kill)
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tasklet_kill(&nq->worker);
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tasklet_kill(&nq->nq_tasklet);
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if (nq->requested) {
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irq_set_affinity_hint(nq->vector, NULL);
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free_irq(nq->vector, nq);
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irq_set_affinity_hint(nq->msix_vec, NULL);
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free_irq(nq->msix_vec, nq);
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nq->requested = false;
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}
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}
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@ -364,16 +364,17 @@ void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq)
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}
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/* Make sure the HW is stopped! */
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if (nq->requested)
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bnxt_qplib_nq_stop_irq(nq, true);
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bnxt_qplib_nq_stop_irq(nq, true);
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if (nq->bar_reg_iomem)
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iounmap(nq->bar_reg_iomem);
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nq->bar_reg_iomem = NULL;
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if (nq->nq_db.reg.bar_reg) {
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iounmap(nq->nq_db.reg.bar_reg);
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nq->nq_db.reg.bar_reg = NULL;
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nq->nq_db.db = NULL;
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}
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nq->cqn_handler = NULL;
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nq->srqn_handler = NULL;
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nq->vector = 0;
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nq->msix_vec = 0;
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}
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int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
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@ -385,68 +386,87 @@ int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
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if (nq->requested)
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return -EFAULT;
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nq->vector = msix_vector;
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nq->msix_vec = msix_vector;
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if (need_init)
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tasklet_init(&nq->worker, bnxt_qplib_service_nq,
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tasklet_init(&nq->nq_tasklet, bnxt_qplib_service_nq,
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(unsigned long)nq);
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else
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tasklet_enable(&nq->worker);
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tasklet_enable(&nq->nq_tasklet);
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snprintf(nq->name, sizeof(nq->name), "bnxt_qplib_nq-%d", nq_indx);
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rc = request_irq(nq->vector, bnxt_qplib_nq_irq, 0, nq->name, nq);
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rc = request_irq(nq->msix_vec, bnxt_qplib_nq_irq, 0, nq->name, nq);
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if (rc)
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return rc;
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cpumask_clear(&nq->mask);
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cpumask_set_cpu(nq_indx, &nq->mask);
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rc = irq_set_affinity_hint(nq->vector, &nq->mask);
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rc = irq_set_affinity_hint(nq->msix_vec, &nq->mask);
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if (rc) {
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dev_warn(&nq->pdev->dev,
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"set affinity failed; vector: %d nq_idx: %d\n",
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nq->vector, nq_indx);
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nq->msix_vec, nq_indx);
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}
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nq->requested = true;
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bnxt_qplib_ring_nq_db_rearm(nq->bar_reg_iomem, nq->hwq.cons,
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bnxt_qplib_ring_nq_db_rearm(nq->nq_db.db, nq->hwq.cons,
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nq->hwq.max_elements, nq->ring_id, gen_p5);
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return rc;
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}
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static int bnxt_qplib_map_nq_db(struct bnxt_qplib_nq *nq, u32 reg_offt)
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{
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resource_size_t reg_base;
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struct bnxt_qplib_nq_db *nq_db;
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struct pci_dev *pdev;
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int rc = 0;
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pdev = nq->pdev;
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nq_db = &nq->nq_db;
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nq_db->reg.bar_id = NQ_CONS_PCI_BAR_REGION;
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nq_db->reg.bar_base = pci_resource_start(pdev, nq_db->reg.bar_id);
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if (!nq_db->reg.bar_base) {
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dev_err(&pdev->dev, "QPLIB: NQ BAR region %d resc start is 0!",
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nq_db->reg.bar_id);
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rc = -ENOMEM;
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goto fail;
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}
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reg_base = nq_db->reg.bar_base + reg_offt;
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/* Unconditionally map 8 bytes to support 57500 series */
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nq_db->reg.len = 8;
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nq_db->reg.bar_reg = ioremap(reg_base, nq_db->reg.len);
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if (!nq_db->reg.bar_reg) {
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dev_err(&pdev->dev, "QPLIB: NQ BAR region %d mapping failed",
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nq_db->reg.bar_id);
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rc = -ENOMEM;
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goto fail;
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}
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nq_db->db = nq_db->reg.bar_reg;
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fail:
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return rc;
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}
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int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
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int nq_idx, int msix_vector, int bar_reg_offset,
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int (*cqn_handler)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_cq *),
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int (*srqn_handler)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_srq *,
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u8 event))
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cqn_handler_t cqn_handler,
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srqn_handler_t srqn_handler)
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{
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resource_size_t nq_base;
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int rc = -1;
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if (cqn_handler)
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nq->cqn_handler = cqn_handler;
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if (srqn_handler)
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nq->srqn_handler = srqn_handler;
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nq->pdev = pdev;
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nq->cqn_handler = cqn_handler;
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nq->srqn_handler = srqn_handler;
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/* Have a task to schedule CQ notifiers in post send case */
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nq->cqn_wq = create_singlethread_workqueue("bnxt_qplib_nq");
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if (!nq->cqn_wq)
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return -ENOMEM;
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nq->bar_reg = NQ_CONS_PCI_BAR_REGION;
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nq->bar_reg_off = bar_reg_offset;
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nq_base = pci_resource_start(pdev, nq->bar_reg);
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if (!nq_base) {
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rc = -ENOMEM;
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rc = bnxt_qplib_map_nq_db(nq, bar_reg_offset);
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if (rc)
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goto fail;
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}
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/* Unconditionally map 8 bytes to support 57500 series */
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nq->bar_reg_iomem = ioremap(nq_base + nq->bar_reg_off, 8);
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if (!nq->bar_reg_iomem) {
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rc = -ENOMEM;
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goto fail;
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}
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rc = bnxt_qplib_nq_start_irq(nq, nq_idx, msix_vector, true);
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if (rc) {
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@ -470,29 +470,32 @@ static inline void bnxt_qplib_ring_nq_db(void __iomem *db, u32 raw_cons,
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writel(NQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK), db);
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}
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struct bnxt_qplib_nq_db {
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struct bnxt_qplib_reg_desc reg;
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void __iomem *db;
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};
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typedef int (*cqn_handler_t)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_cq *cq);
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typedef int (*srqn_handler_t)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_srq *srq, u8 event);
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struct bnxt_qplib_nq {
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struct pci_dev *pdev;
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struct bnxt_qplib_res *res;
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struct pci_dev *pdev;
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struct bnxt_qplib_res *res;
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char name[32];
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struct bnxt_qplib_hwq hwq;
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struct bnxt_qplib_nq_db nq_db;
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u16 ring_id;
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int msix_vec;
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cpumask_t mask;
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struct tasklet_struct nq_tasklet;
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bool requested;
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int budget;
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int vector;
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cpumask_t mask;
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int budget;
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bool requested;
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struct tasklet_struct worker;
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struct bnxt_qplib_hwq hwq;
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u16 bar_reg;
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u32 bar_reg_off;
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u16 ring_id;
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void __iomem *bar_reg_iomem;
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int (*cqn_handler)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_cq *cq);
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int (*srqn_handler)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_srq *srq,
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u8 event);
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struct workqueue_struct *cqn_wq;
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char name[32];
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cqn_handler_t cqn_handler;
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srqn_handler_t srqn_handler;
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struct workqueue_struct *cqn_wq;
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};
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struct bnxt_qplib_nq_work {
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@ -507,11 +510,8 @@ int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
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int msix_vector, bool need_init);
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int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
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int nq_idx, int msix_vector, int bar_reg_offset,
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int (*cqn_handler)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_cq *cq),
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int (*srqn_handler)(struct bnxt_qplib_nq *nq,
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struct bnxt_qplib_srq *srq,
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u8 event));
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cqn_handler_t cqn_handler,
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srqn_handler_t srq_handler);
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int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,
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struct bnxt_qplib_srq *srq);
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int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res,
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