Merge branch 'fix/edma' into fixes
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956e6c8e18
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@ -1238,6 +1238,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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struct edma_desc *edesc;
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dma_addr_t src_addr, dst_addr;
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enum dma_slave_buswidth dev_width;
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bool use_intermediate = false;
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u32 burst;
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int i, ret, nslots;
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@ -1279,8 +1280,21 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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* but the synchronization is difficult to achieve with Cyclic and
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* cannot be guaranteed, so we error out early.
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*/
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if (nslots > MAX_NR_SG)
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return NULL;
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if (nslots > MAX_NR_SG) {
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/*
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* If the burst and period sizes are the same, we can put
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* the full buffer into a single period and activate
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* intermediate interrupts. This will produce interrupts
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* after each burst, which is also after each desired period.
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*/
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if (burst == period_len) {
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period_len = buf_len;
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nslots = 2;
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use_intermediate = true;
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} else {
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return NULL;
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}
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}
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edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
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GFP_ATOMIC);
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@ -1358,8 +1372,13 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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/*
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* Enable period interrupt only if it is requested
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*/
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if (tx_flags & DMA_PREP_INTERRUPT)
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if (tx_flags & DMA_PREP_INTERRUPT) {
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edesc->pset[i].param.opt |= TCINTEN;
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/* Also enable intermediate interrupts if necessary */
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if (use_intermediate)
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edesc->pset[i].param.opt |= ITCINTEN;
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}
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}
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/* Place the cyclic channel to highest priority queue */
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@ -1570,32 +1589,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
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return IRQ_HANDLED;
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}
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static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable)
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{
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struct platform_device *tc_pdev;
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int ret;
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if (!IS_ENABLED(CONFIG_OF) || !tc)
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return;
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tc_pdev = of_find_device_by_node(tc->node);
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if (!tc_pdev) {
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pr_err("%s: TPTC device is not found\n", __func__);
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return;
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}
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if (!pm_runtime_enabled(&tc_pdev->dev))
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pm_runtime_enable(&tc_pdev->dev);
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if (enable)
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ret = pm_runtime_get_sync(&tc_pdev->dev);
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else
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ret = pm_runtime_put_sync(&tc_pdev->dev);
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if (ret < 0)
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pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__,
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enable ? "get" : "put", dev_name(&tc_pdev->dev));
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}
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/* Alloc channel resources */
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static int edma_alloc_chan_resources(struct dma_chan *chan)
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{
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@ -1632,8 +1625,6 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
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EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
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echan->hw_triggered ? "HW" : "SW");
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edma_tc_set_pm_state(echan->tc, true);
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return 0;
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err_slot:
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@ -1670,7 +1661,6 @@ static void edma_free_chan_resources(struct dma_chan *chan)
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echan->alloced = false;
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}
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edma_tc_set_pm_state(echan->tc, false);
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echan->tc = NULL;
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echan->hw_triggered = false;
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@ -2417,10 +2407,8 @@ static int edma_pm_suspend(struct device *dev)
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int i;
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for (i = 0; i < ecc->num_channels; i++) {
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if (echan[i].alloced) {
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if (echan[i].alloced)
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edma_setup_interrupt(&echan[i], false);
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edma_tc_set_pm_state(echan[i].tc, false);
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}
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}
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return 0;
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@ -2450,8 +2438,6 @@ static int edma_pm_resume(struct device *dev)
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/* Set up channel -> slot mapping for the entry slot */
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edma_set_chmap(&echan[i], echan[i].slot[0]);
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edma_tc_set_pm_state(echan[i].tc, true);
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}
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}
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@ -2475,7 +2461,8 @@ static struct platform_driver edma_driver = {
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static int edma_tptc_probe(struct platform_device *pdev)
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{
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return 0;
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pm_runtime_enable(&pdev->dev);
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return pm_runtime_get_sync(&pdev->dev);
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}
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static struct platform_driver edma_tptc_driver = {
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