davinci-mcasp: use bitfield definitions for PDIR
The current driver creates value for set/clr of PDIR using (x<<26) instead of the #defines that are convieniently made available. Update the driver to use the bitfield definitions of PDIR. There is no functional change introduced by this patch. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Reviewed-by: James Nuss <jamesnuss@nanometrics.ca> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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049cfaaa47
Коммит
9595c8f035
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@ -434,7 +434,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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ACLKX | AHCLKX | AFSX);
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break;
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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case SND_SOC_DAIFMT_CBM_CFS:
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/* codec is clock master and frame slave */
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/* codec is clock master and frame slave */
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@ -444,7 +445,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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ACLKX | AFSX | ACLKR | AFSR);
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break;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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case SND_SOC_DAIFMT_CBM_CFM:
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/* codec is clock and frame master */
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/* codec is clock and frame master */
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@ -454,7 +456,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
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mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
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ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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break;
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break;
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default:
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default:
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