i2c: Add DaVinci I2C controller support
Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Acked-by: Trilok Soni <soni.trilok@gmail.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
Vladimir Barinov
Jean Delvare
Родитель
7589a326d1
Коммит
95a7f10ead
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@ -106,6 +106,19 @@ config I2C_BLACKFIN_TWI_CLK_KHZ
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help
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The unit of the TWI clock is kHz.
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config I2C_DAVINCI
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tristate "DaVinci I2C driver"
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depends on ARCH_DAVINCI
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help
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Support for TI DaVinci I2C controller driver.
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This driver can also be built as a module. If so, the module
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will be called i2c-davinci.
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Please note that this driver might be needed to bring up other
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devices such as DaVinci NIC.
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For details please see http://www.ti.com/davinci
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config I2C_ELEKTOR
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tristate "Elektor ISA card"
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depends on ISA && BROKEN_ON_SMP
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@ -11,6 +11,7 @@ obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
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obj-$(CONFIG_I2C_AT91) += i2c-at91.o
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obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
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obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
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obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
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obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
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obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
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obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
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@ -0,0 +1,586 @@
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/*
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* TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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*
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* Updated by Vinod & Sudhakar Feb 2005
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/arch/i2c.h>
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/* ----- global defines ----------------------------------------------- */
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#define DAVINCI_I2C_TIMEOUT (1*HZ)
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#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
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DAVINCI_I2C_IMR_SCD | \
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DAVINCI_I2C_IMR_ARDY | \
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DAVINCI_I2C_IMR_NACK | \
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DAVINCI_I2C_IMR_AL)
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#define DAVINCI_I2C_OAR_REG 0x00
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#define DAVINCI_I2C_IMR_REG 0x04
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#define DAVINCI_I2C_STR_REG 0x08
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#define DAVINCI_I2C_CLKL_REG 0x0c
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#define DAVINCI_I2C_CLKH_REG 0x10
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#define DAVINCI_I2C_CNT_REG 0x14
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#define DAVINCI_I2C_DRR_REG 0x18
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#define DAVINCI_I2C_SAR_REG 0x1c
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#define DAVINCI_I2C_DXR_REG 0x20
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#define DAVINCI_I2C_MDR_REG 0x24
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#define DAVINCI_I2C_IVR_REG 0x28
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#define DAVINCI_I2C_EMDR_REG 0x2c
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#define DAVINCI_I2C_PSC_REG 0x30
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#define DAVINCI_I2C_IVR_AAS 0x07
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#define DAVINCI_I2C_IVR_SCD 0x06
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#define DAVINCI_I2C_IVR_XRDY 0x05
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#define DAVINCI_I2C_IVR_RDR 0x04
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#define DAVINCI_I2C_IVR_ARDY 0x03
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#define DAVINCI_I2C_IVR_NACK 0x02
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#define DAVINCI_I2C_IVR_AL 0x01
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#define DAVINCI_I2C_STR_BB (1 << 12)
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#define DAVINCI_I2C_STR_RSFULL (1 << 11)
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#define DAVINCI_I2C_STR_SCD (1 << 5)
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#define DAVINCI_I2C_STR_ARDY (1 << 2)
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#define DAVINCI_I2C_STR_NACK (1 << 1)
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#define DAVINCI_I2C_STR_AL (1 << 0)
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#define DAVINCI_I2C_MDR_NACK (1 << 15)
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#define DAVINCI_I2C_MDR_STT (1 << 13)
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#define DAVINCI_I2C_MDR_STP (1 << 11)
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#define DAVINCI_I2C_MDR_MST (1 << 10)
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#define DAVINCI_I2C_MDR_TRX (1 << 9)
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#define DAVINCI_I2C_MDR_XA (1 << 8)
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#define DAVINCI_I2C_MDR_IRS (1 << 5)
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#define DAVINCI_I2C_IMR_AAS (1 << 6)
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#define DAVINCI_I2C_IMR_SCD (1 << 5)
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#define DAVINCI_I2C_IMR_XRDY (1 << 4)
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#define DAVINCI_I2C_IMR_RRDY (1 << 3)
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#define DAVINCI_I2C_IMR_ARDY (1 << 2)
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#define DAVINCI_I2C_IMR_NACK (1 << 1)
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#define DAVINCI_I2C_IMR_AL (1 << 0)
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#define MOD_REG_BIT(val, mask, set) do { \
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if (set) { \
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val |= mask; \
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} else { \
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val &= ~mask; \
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} \
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} while (0)
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struct davinci_i2c_dev {
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struct device *dev;
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void __iomem *base;
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struct completion cmd_complete;
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struct clk *clk;
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int cmd_err;
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u8 *buf;
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size_t buf_len;
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int irq;
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struct i2c_adapter adapter;
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};
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/* default platform data to use if not supplied in the platform_device */
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static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
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.bus_freq = 100,
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.bus_delay = 0,
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};
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static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
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int reg, u16 val)
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{
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__raw_writew(val, i2c_dev->base + reg);
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}
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static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
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{
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return __raw_readw(i2c_dev->base + reg);
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}
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/*
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* This functions configures I2C and brings I2C out of reset.
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* This function is called during I2C init function. This function
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* also gets called if I2C encounters any errors.
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*/
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static int i2c_davinci_init(struct davinci_i2c_dev *dev)
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{
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struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
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u16 psc;
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u32 clk;
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u32 clkh;
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u32 clkl;
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u32 input_clock = clk_get_rate(dev->clk);
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u16 w;
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if (!pdata)
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pdata = &davinci_i2c_platform_data_default;
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/* put I2C into reset */
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w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
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MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
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/* NOTE: I2C Clock divider programming info
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* As per I2C specs the following formulas provide prescaler
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* and low/high divider values
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* input clk --> PSC Div -----------> ICCL/H Div --> output clock
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* module clk
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*
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* output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
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*
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* Thus,
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* (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
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*
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* where if PSC == 0, d = 7,
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* if PSC == 1, d = 6
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* if PSC > 1 , d = 5
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*/
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psc = 26; /* To get 1MHz clock */
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clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - 10;
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clkh = (50 * clk) / 100;
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clkl = clk - clkh;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
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dev_dbg(dev->dev, "CLK = %d\n", clk);
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dev_dbg(dev->dev, "PSC = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
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dev_dbg(dev->dev, "CLKL = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
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dev_dbg(dev->dev, "CLKH = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
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/* Take the I2C module out of reset: */
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w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
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MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
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/* Enable interrupts */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
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return 0;
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}
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/*
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* Waiting for bus not busy
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*/
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static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
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char allow_sleep)
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{
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unsigned long timeout;
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timeout = jiffies + DAVINCI_I2C_TIMEOUT;
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while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
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& DAVINCI_I2C_STR_BB) {
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if (time_after(jiffies, timeout)) {
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dev_warn(dev->dev,
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"timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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if (allow_sleep)
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schedule_timeout(1);
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}
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return 0;
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}
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/*
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* Low level master read/write transaction. This function is called
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* from i2c_davinci_xfer.
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*/
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static int
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i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
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u32 flag;
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u32 stat;
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u16 w;
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int r;
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if (msg->len == 0)
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return -EINVAL;
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if (!pdata)
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pdata = &davinci_i2c_platform_data_default;
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/* Introduce a delay, required for some boards (e.g Davinci EVM) */
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if (pdata->bus_delay)
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udelay(pdata->bus_delay);
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/* set the slave address */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
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dev->buf = msg->buf;
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dev->buf_len = msg->len;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
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init_completion(&dev->cmd_complete);
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dev->cmd_err = 0;
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/* Clear any pending interrupts by reading the IVR */
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stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG);
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/* Take I2C out of reset, configure it as master and set the
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* start bit */
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flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
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/* if the slave address is ten bit address, enable XA bit */
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if (msg->flags & I2C_M_TEN)
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flag |= DAVINCI_I2C_MDR_XA;
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if (!(msg->flags & I2C_M_RD))
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flag |= DAVINCI_I2C_MDR_TRX;
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if (stop)
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flag |= DAVINCI_I2C_MDR_STP;
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/* Enable receive or transmit interrupts */
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w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
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if (msg->flags & I2C_M_RD)
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MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
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else
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MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
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/* write the data into mode register */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
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DAVINCI_I2C_TIMEOUT);
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dev->buf_len = 0;
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if (r < 0)
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return r;
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if (r == 0) {
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dev_err(dev->dev, "controller timed out\n");
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i2c_davinci_init(dev);
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return -ETIMEDOUT;
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}
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/* no error */
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if (likely(!dev->cmd_err))
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return msg->len;
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/* We have an error */
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if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
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i2c_davinci_init(dev);
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return -EIO;
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}
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if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
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if (msg->flags & I2C_M_IGNORE_NAK)
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return msg->len;
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if (stop) {
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w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
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MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
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}
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return -EREMOTEIO;
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}
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return -EIO;
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}
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/*
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* Prepare controller for a transaction and call i2c_davinci_xfer_msg
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*/
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static int
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i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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int i;
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int ret;
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dev_dbg(dev->dev, "%s: msgs: %d\n", __FUNCTION__, num);
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ret = i2c_davinci_wait_bus_not_busy(dev, 1);
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if (ret < 0) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return ret;
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}
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for (i = 0; i < num; i++) {
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ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
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if (ret < 0)
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return ret;
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}
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dev_dbg(dev->dev, "%s:%d ret: %d\n", __FUNCTION__, __LINE__, ret);
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return num;
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}
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static u32 i2c_davinci_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
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}
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/*
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* Interrupt service routine. This gets called whenever an I2C interrupt
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* occurs.
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*/
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static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
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{
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struct davinci_i2c_dev *dev = dev_id;
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u32 stat;
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int count = 0;
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u16 w;
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while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
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dev_dbg(dev->dev, "%s: stat=0x%x\n", __FUNCTION__, stat);
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if (count++ == 100) {
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dev_warn(dev->dev, "Too much work in one IRQ\n");
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break;
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}
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switch (stat) {
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case DAVINCI_I2C_IVR_AL:
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dev->cmd_err |= DAVINCI_I2C_STR_AL;
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complete(&dev->cmd_complete);
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break;
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case DAVINCI_I2C_IVR_NACK:
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dev->cmd_err |= DAVINCI_I2C_STR_NACK;
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complete(&dev->cmd_complete);
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break;
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case DAVINCI_I2C_IVR_ARDY:
|
||||
w = davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG);
|
||||
MOD_REG_BIT(w, DAVINCI_I2C_STR_ARDY, 1);
|
||||
davinci_i2c_write_reg(dev, DAVINCI_I2C_STR_REG, w);
|
||||
complete(&dev->cmd_complete);
|
||||
break;
|
||||
|
||||
case DAVINCI_I2C_IVR_RDR:
|
||||
if (dev->buf_len) {
|
||||
*dev->buf++ =
|
||||
davinci_i2c_read_reg(dev,
|
||||
DAVINCI_I2C_DRR_REG);
|
||||
dev->buf_len--;
|
||||
if (dev->buf_len)
|
||||
continue;
|
||||
|
||||
w = davinci_i2c_read_reg(dev,
|
||||
DAVINCI_I2C_STR_REG);
|
||||
MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 0);
|
||||
davinci_i2c_write_reg(dev,
|
||||
DAVINCI_I2C_STR_REG,
|
||||
w);
|
||||
} else
|
||||
dev_err(dev->dev, "RDR IRQ while no"
|
||||
"data requested\n");
|
||||
break;
|
||||
|
||||
case DAVINCI_I2C_IVR_XRDY:
|
||||
if (dev->buf_len) {
|
||||
davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
|
||||
*dev->buf++);
|
||||
dev->buf_len--;
|
||||
if (dev->buf_len)
|
||||
continue;
|
||||
|
||||
w = davinci_i2c_read_reg(dev,
|
||||
DAVINCI_I2C_IMR_REG);
|
||||
MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
|
||||
davinci_i2c_write_reg(dev,
|
||||
DAVINCI_I2C_IMR_REG,
|
||||
w);
|
||||
} else
|
||||
dev_err(dev->dev, "TDR IRQ while no data to"
|
||||
"send\n");
|
||||
break;
|
||||
|
||||
case DAVINCI_I2C_IVR_SCD:
|
||||
w = davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG);
|
||||
MOD_REG_BIT(w, DAVINCI_I2C_STR_SCD, 1);
|
||||
davinci_i2c_write_reg(dev, DAVINCI_I2C_STR_REG, w);
|
||||
complete(&dev->cmd_complete);
|
||||
break;
|
||||
|
||||
case DAVINCI_I2C_IVR_AAS:
|
||||
dev_warn(dev->dev, "Address as slave interrupt\n");
|
||||
}/* switch */
|
||||
}/* while */
|
||||
|
||||
return count ? IRQ_HANDLED : IRQ_NONE;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm i2c_davinci_algo = {
|
||||
.master_xfer = i2c_davinci_xfer,
|
||||
.functionality = i2c_davinci_func,
|
||||
};
|
||||
|
||||
static int davinci_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct davinci_i2c_dev *dev;
|
||||
struct i2c_adapter *adap;
|
||||
struct resource *mem, *irq, *ioarea;
|
||||
int r;
|
||||
|
||||
/* NOTE: driver uses the static register mapping */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&pdev->dev, "no mem resource?\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!irq) {
|
||||
dev_err(&pdev->dev, "no irq resource?\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
|
||||
pdev->name);
|
||||
if (!ioarea) {
|
||||
dev_err(&pdev->dev, "I2C region already claimed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
|
||||
if (!dev) {
|
||||
r = -ENOMEM;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
dev->dev = get_device(&pdev->dev);
|
||||
dev->irq = irq->start;
|
||||
platform_set_drvdata(pdev, dev);
|
||||
|
||||
dev->clk = clk_get(&pdev->dev, "I2CCLK");
|
||||
if (IS_ERR(dev->clk)) {
|
||||
r = -ENODEV;
|
||||
goto err_free_mem;
|
||||
}
|
||||
clk_enable(dev->clk);
|
||||
|
||||
dev->base = (void __iomem *)IO_ADDRESS(mem->start);
|
||||
i2c_davinci_init(dev);
|
||||
|
||||
r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
|
||||
goto err_unuse_clocks;
|
||||
}
|
||||
|
||||
adap = &dev->adapter;
|
||||
i2c_set_adapdata(adap, dev);
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_HWMON;
|
||||
strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
|
||||
adap->algo = &i2c_davinci_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
|
||||
/* FIXME */
|
||||
adap->timeout = 1;
|
||||
adap->retries = 1;
|
||||
|
||||
adap->nr = pdev->id;
|
||||
r = i2c_add_numbered_adapter(adap);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure adding adapter\n");
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
free_irq(dev->irq, dev);
|
||||
err_unuse_clocks:
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
err_free_mem:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
put_device(&pdev->dev);
|
||||
kfree(dev);
|
||||
err_release_region:
|
||||
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int davinci_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
|
||||
struct resource *mem;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
i2c_del_adapter(&dev->adapter);
|
||||
put_device(&pdev->dev);
|
||||
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
|
||||
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
|
||||
free_irq(IRQ_I2C, dev);
|
||||
kfree(dev);
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver davinci_i2c_driver = {
|
||||
.probe = davinci_i2c_probe,
|
||||
.remove = davinci_i2c_remove,
|
||||
.driver = {
|
||||
.name = "i2c_davinci",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C may be needed to bring up other drivers */
|
||||
static int __init davinci_i2c_init_driver(void)
|
||||
{
|
||||
return platform_driver_register(&davinci_i2c_driver);
|
||||
}
|
||||
subsys_initcall(davinci_i2c_init_driver);
|
||||
|
||||
static void __exit davinci_i2c_exit_driver(void)
|
||||
{
|
||||
platform_driver_unregister(&davinci_i2c_driver);
|
||||
}
|
||||
module_exit(davinci_i2c_exit_driver);
|
||||
|
||||
MODULE_AUTHOR("Texas Instruments India");
|
||||
MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* DaVinci I2C controller platfrom_device info
|
||||
*
|
||||
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_I2C_H
|
||||
#define __ASM_ARCH_I2C_H
|
||||
|
||||
/* All frequencies are expressed in kHz */
|
||||
struct davinci_i2c_platform_data {
|
||||
unsigned int bus_freq; /* standard bus frequency */
|
||||
unsigned int bus_delay; /* transaction delay */
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARCH_I2C_H */
|
||||
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