Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Lots of little small things, nothing too major: nouveau regression fixes, vmware fixes for the new hw support, memory leaks in error path fixes" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (31 commits) drm/radeon/ni: fix typo in dpm sq ramping setup drm/radeon/si: fix typo in dpm sq ramping setup drm/radeon: fix CP semaphores on CIK drm/radeon: delete a stray tab drm/radeon: fix display tiling setup on SI drm/radeon/dpm: reduce r7xx vblank mclk threshold to 200 drm/radeon: fill in DRM_CAPs for cursor size drm: add DRM_CAPs for cursor size drm/radeon: unify bpc handling drm/ttm: Fix memory leak in ttm_agp_backend.c drm/ttm: declare 'struct device' in ttm_page_alloc.h drm/nouveau: fix TTM_PL_TT memtype on pre-nv50 drm/nv50/disp: use correct register to determine DP display bpp drm/nouveau/fb: use correct ram oclass for nv1a hardware drm/nv50/gr: add missing nv_error parameter priv drm/nouveau: fix ENG_RUNLIST register address drm/nv4c/bios: disallow retrieving from prom on nv4x igp's drm/nv4c/vga: decode register is in a different place on nv4x igp's drm/nv4c/mc: nv4x igp's have a different msi rearm register drm/nouveau: set irq_enabled manually ...
This commit is contained in:
Linus Torvalds
Коммит
960dfc4eb2
|
|
@ -296,6 +296,18 @@ int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|||
case DRM_CAP_ASYNC_PAGE_FLIP:
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req->value = dev->mode_config.async_page_flip;
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break;
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case DRM_CAP_CURSOR_WIDTH:
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if (dev->mode_config.cursor_width)
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req->value = dev->mode_config.cursor_width;
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else
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req->value = 64;
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break;
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case DRM_CAP_CURSOR_HEIGHT:
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if (dev->mode_config.cursor_height)
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req->value = dev->mode_config.cursor_height;
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else
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req->value = 64;
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break;
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default:
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return -EINVAL;
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}
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|
|
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|
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@ -1151,8 +1151,10 @@ tda998x_encoder_init(struct i2c_client *client,
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priv->current_page = 0xff;
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priv->cec = i2c_new_dummy(client->adapter, 0x34);
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if (!priv->cec)
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if (!priv->cec) {
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kfree(priv);
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return -ENODEV;
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}
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priv->dpms = DRM_MODE_DPMS_OFF;
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encoder_slave->slave_priv = priv;
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|
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@ -8586,6 +8586,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
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if (ring->id == RCS)
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len += 6;
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/*
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* BSpec MI_DISPLAY_FLIP for IVB:
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* "The full packet must be contained within the same cache line."
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*
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* Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
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* cacheline, if we ever start emitting more commands before
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* the MI_DISPLAY_FLIP we may need to first emit everything else,
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* then do the cacheline alignment, and finally emit the
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* MI_DISPLAY_FLIP.
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*/
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ret = intel_ring_cacheline_align(ring);
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if (ret)
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goto err_unpin;
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ret = intel_ring_begin(ring, len);
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if (ret)
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goto err_unpin;
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|
|
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@ -537,6 +537,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
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uint8_t msg[20];
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int msg_bytes;
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uint8_t ack;
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int retry;
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if (WARN_ON(send_bytes > 16))
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return -E2BIG;
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@ -548,19 +549,21 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
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msg[3] = send_bytes - 1;
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memcpy(&msg[4], send, send_bytes);
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msg_bytes = send_bytes + 4;
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for (;;) {
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for (retry = 0; retry < 7; retry++) {
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ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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if (ret < 0)
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return ret;
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ack >>= 4;
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if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
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break;
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return send_bytes;
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else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
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udelay(100);
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usleep_range(400, 500);
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else
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return -EIO;
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}
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return send_bytes;
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DRM_ERROR("too many retries, giving up\n");
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return -EIO;
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}
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/* Write a single byte to the aux channel in native mode */
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|
@ -582,6 +585,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
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int reply_bytes;
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uint8_t ack;
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int ret;
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int retry;
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if (WARN_ON(recv_bytes > 19))
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return -E2BIG;
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|
|
@ -595,7 +599,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
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msg_bytes = 4;
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reply_bytes = recv_bytes + 1;
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for (;;) {
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for (retry = 0; retry < 7; retry++) {
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ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
|
||||
reply, reply_bytes);
|
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if (ret == 0)
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|
|
@ -608,10 +612,13 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
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|||
return ret - 1;
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||||
}
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||||
else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
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udelay(100);
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usleep_range(400, 500);
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else
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return -EIO;
|
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}
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||||
|
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DRM_ERROR("too many retries, giving up\n");
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return -EIO;
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}
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static int
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|
|
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|
|
@ -1653,6 +1653,27 @@ int intel_ring_begin(struct intel_ring_buffer *ring,
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return 0;
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}
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|
||||
/* Align the ring tail to a cacheline boundary */
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int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
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{
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int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
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int ret;
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if (num_dwords == 0)
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return 0;
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|
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ret = intel_ring_begin(ring, num_dwords);
|
||||
if (ret)
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||||
return ret;
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||||
|
||||
while (num_dwords--)
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||||
intel_ring_emit(ring, MI_NOOP);
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||||
|
||||
intel_ring_advance(ring);
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return 0;
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}
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|
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void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
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{
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||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
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|
|
|
|||
|
|
@ -233,6 +233,7 @@ intel_write_status_page(struct intel_ring_buffer *ring,
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|||
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
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||||
|
||||
int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
|
||||
int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
|
||||
static inline void intel_ring_emit(struct intel_ring_buffer *ring,
|
||||
u32 data)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -141,6 +141,7 @@ nouveau-y += core/subdev/mc/base.o
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|||
nouveau-y += core/subdev/mc/nv04.o
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||||
nouveau-y += core/subdev/mc/nv40.o
|
||||
nouveau-y += core/subdev/mc/nv44.o
|
||||
nouveau-y += core/subdev/mc/nv4c.o
|
||||
nouveau-y += core/subdev/mc/nv50.o
|
||||
nouveau-y += core/subdev/mc/nv94.o
|
||||
nouveau-y += core/subdev/mc/nv98.o
|
||||
|
|
|
|||
|
|
@ -311,7 +311,7 @@ nv40_identify(struct nouveau_device *device)
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|||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
|
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
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||||
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|
@ -334,7 +334,7 @@ nv40_identify(struct nouveau_device *device)
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|||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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||||
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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||||
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
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||||
|
|
@ -357,7 +357,7 @@ nv40_identify(struct nouveau_device *device)
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|||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
|
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
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||||
|
|
@ -380,7 +380,7 @@ nv40_identify(struct nouveau_device *device)
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|||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
|
||||
|
|
@ -403,7 +403,7 @@ nv40_identify(struct nouveau_device *device)
|
|||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
|
||||
|
|
|
|||
|
|
@ -1142,7 +1142,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
|
|||
if (conf != ~0) {
|
||||
if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
|
||||
u32 soff = (ffs(outp.or) - 1) * 0x08;
|
||||
u32 ctrl = nv_rd32(priv, 0x610798 + soff);
|
||||
u32 ctrl = nv_rd32(priv, 0x610794 + soff);
|
||||
u32 datarate;
|
||||
|
||||
switch ((ctrl & 0x000f0000) >> 16) {
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
|
|||
|
||||
nv_wr32(priv, 0x002270, cur->addr >> 12);
|
||||
nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
|
||||
if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
|
||||
if (!nv_wait(priv, 0x002284 + (engine * 8), 0x00100000, 0x00000000))
|
||||
nv_error(priv, "runlist %d update timeout\n", engine);
|
||||
mutex_unlock(&nv_subdev(priv)->mutex);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -539,7 +539,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
|
|||
ustatus &= ~0x04030000;
|
||||
}
|
||||
if (ustatus && display) {
|
||||
nv_error("%s - TP%d:", name, i);
|
||||
nv_error(priv, "%s - TP%d:", name, i);
|
||||
nouveau_bitfield_print(nv50_mpc_traps, ustatus);
|
||||
pr_cont("\n");
|
||||
ustatus = 0;
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ struct nouveau_mc_oclass {
|
|||
extern struct nouveau_oclass *nv04_mc_oclass;
|
||||
extern struct nouveau_oclass *nv40_mc_oclass;
|
||||
extern struct nouveau_oclass *nv44_mc_oclass;
|
||||
extern struct nouveau_oclass *nv4c_mc_oclass;
|
||||
extern struct nouveau_oclass *nv50_mc_oclass;
|
||||
extern struct nouveau_oclass *nv94_mc_oclass;
|
||||
extern struct nouveau_oclass *nv98_mc_oclass;
|
||||
|
|
|
|||
|
|
@ -130,6 +130,10 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
|
|||
u16 pcir;
|
||||
int i;
|
||||
|
||||
/* there is no prom on nv4x IGP's */
|
||||
if (device->card_type == NV_40 && device->chipset >= 0x4c)
|
||||
return;
|
||||
|
||||
/* enable access to rom */
|
||||
if (device->card_type >= NV_50)
|
||||
pcireg = 0x088050;
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ nv1a_fb_oclass = &(struct nv04_fb_impl) {
|
|||
.fini = _nouveau_fb_fini,
|
||||
},
|
||||
.base.memtype = nv04_fb_memtype_valid,
|
||||
.base.ram = &nv10_ram_oclass,
|
||||
.base.ram = &nv1a_ram_oclass,
|
||||
.tile.regions = 8,
|
||||
.tile.init = nv10_fb_tile_init,
|
||||
.tile.fini = nv10_fb_tile_fini,
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *,
|
|||
extern const struct nouveau_mc_intr nv04_mc_intr[];
|
||||
int nv04_mc_init(struct nouveau_object *);
|
||||
void nv40_mc_msi_rearm(struct nouveau_mc *);
|
||||
int nv44_mc_init(struct nouveau_object *object);
|
||||
int nv50_mc_init(struct nouveau_object *);
|
||||
extern const struct nouveau_mc_intr nv50_mc_intr[];
|
||||
extern const struct nouveau_mc_intr nvc0_mc_intr[];
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
#include "nv04.h"
|
||||
|
||||
static int
|
||||
int
|
||||
nv44_mc_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nv04_mc_priv *priv = (void *)object;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright 2014 Ilia Mirkin
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ilia Mirkin
|
||||
*/
|
||||
|
||||
#include "nv04.h"
|
||||
|
||||
static void
|
||||
nv4c_mc_msi_rearm(struct nouveau_mc *pmc)
|
||||
{
|
||||
struct nv04_mc_priv *priv = (void *)pmc;
|
||||
nv_wr08(priv, 0x088050, 0xff);
|
||||
}
|
||||
|
||||
struct nouveau_oclass *
|
||||
nv4c_mc_oclass = &(struct nouveau_mc_oclass) {
|
||||
.base.handle = NV_SUBDEV(MC, 0x4c),
|
||||
.base.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nv04_mc_ctor,
|
||||
.dtor = _nouveau_mc_dtor,
|
||||
.init = nv44_mc_init,
|
||||
.fini = _nouveau_mc_fini,
|
||||
},
|
||||
.intr = nv04_mc_intr,
|
||||
.msi_rearm = nv4c_mc_msi_rearm,
|
||||
}.base;
|
||||
|
|
@ -1249,7 +1249,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|||
mem->bus.is_iomem = !dev->agp->cant_use_aperture;
|
||||
}
|
||||
#endif
|
||||
if (!node->memtype)
|
||||
if (nv_device(drm->device)->card_type < NV_50 || !node->memtype)
|
||||
/* untiled */
|
||||
break;
|
||||
/* fallthrough, tiled memory */
|
||||
|
|
|
|||
|
|
@ -376,6 +376,8 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
|
|||
if (ret)
|
||||
goto fail_device;
|
||||
|
||||
dev->irq_enabled = true;
|
||||
|
||||
/* workaround an odd issue on nvc1 by disabling the device's
|
||||
* nosnoop capability. hopefully won't cause issues until a
|
||||
* better fix is found - assuming there is one...
|
||||
|
|
@ -475,6 +477,7 @@ nouveau_drm_remove(struct pci_dev *pdev)
|
|||
struct nouveau_drm *drm = nouveau_drm(dev);
|
||||
struct nouveau_object *device;
|
||||
|
||||
dev->irq_enabled = false;
|
||||
device = drm->client.base.device;
|
||||
drm_put_dev(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,9 @@ nouveau_vga_set_decode(void *priv, bool state)
|
|||
{
|
||||
struct nouveau_device *device = nouveau_dev(priv);
|
||||
|
||||
if (device->chipset >= 0x40)
|
||||
if (device->card_type == NV_40 && device->chipset >= 0x4c)
|
||||
nv_wr32(device, 0x088060, state);
|
||||
else if (device->chipset >= 0x40)
|
||||
nv_wr32(device, 0x088054, state);
|
||||
else
|
||||
nv_wr32(device, 0x001854, state);
|
||||
|
|
|
|||
|
|
@ -559,7 +559,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
|
|||
u32 adjusted_clock = mode->clock;
|
||||
int encoder_mode = atombios_get_encoder_mode(encoder);
|
||||
u32 dp_clock = mode->clock;
|
||||
int bpc = radeon_get_monitor_bpc(connector);
|
||||
int bpc = radeon_crtc->bpc;
|
||||
bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
|
||||
|
||||
/* reset the pll flags */
|
||||
|
|
@ -1176,7 +1176,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
|
|||
evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
|
||||
|
||||
/* Set NUM_BANKS. */
|
||||
if (rdev->family >= CHIP_BONAIRE) {
|
||||
if (rdev->family >= CHIP_TAHITI) {
|
||||
unsigned tileb, index, num_banks, tile_split_bytes;
|
||||
|
||||
/* Calculate the macrotile mode index. */
|
||||
|
|
@ -1194,13 +1194,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
|
||||
if (rdev->family >= CHIP_BONAIRE)
|
||||
num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
|
||||
else
|
||||
num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
|
||||
fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
|
||||
} else {
|
||||
/* SI and older. */
|
||||
if (rdev->family >= CHIP_TAHITI)
|
||||
tmp = rdev->config.si.tile_config;
|
||||
else if (rdev->family >= CHIP_CAYMAN)
|
||||
/* NI and older. */
|
||||
if (rdev->family >= CHIP_CAYMAN)
|
||||
tmp = rdev->config.cayman.tile_config;
|
||||
else
|
||||
tmp = rdev->config.evergreen.tile_config;
|
||||
|
|
|
|||
|
|
@ -464,11 +464,12 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
|
|||
|
||||
static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
|
||||
int bpc = 8;
|
||||
|
||||
if (connector)
|
||||
bpc = radeon_get_monitor_bpc(connector);
|
||||
if (encoder->crtc) {
|
||||
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
|
||||
bpc = radeon_crtc->bpc;
|
||||
}
|
||||
|
||||
switch (bpc) {
|
||||
case 0:
|
||||
|
|
|
|||
|
|
@ -1680,7 +1680,7 @@ bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
|
|||
case RADEON_HPD_6:
|
||||
if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
|
||||
connected = true;
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2588,7 +2588,7 @@ static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
|
|||
if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
|
||||
enable_sq_ramping = false;
|
||||
|
||||
if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
|
||||
if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
|
||||
enable_sq_ramping = false;
|
||||
|
||||
for (i = 0; i < state->performance_level_count; i++) {
|
||||
|
|
|
|||
|
|
@ -135,6 +135,9 @@ extern int radeon_hard_reset;
|
|||
/* R600+ */
|
||||
#define R600_RING_TYPE_UVD_INDEX 5
|
||||
|
||||
/* number of hw syncs before falling back on blocking */
|
||||
#define RADEON_NUM_SYNCS 4
|
||||
|
||||
/* hardcode those limit for now */
|
||||
#define RADEON_VA_IB_OFFSET (1 << 20)
|
||||
#define RADEON_VA_RESERVED_SIZE (8 << 20)
|
||||
|
|
@ -554,7 +557,6 @@ int radeon_mode_dumb_mmap(struct drm_file *filp,
|
|||
/*
|
||||
* Semaphores.
|
||||
*/
|
||||
/* everything here is constant */
|
||||
struct radeon_semaphore {
|
||||
struct radeon_sa_bo *sa_bo;
|
||||
signed waiters;
|
||||
|
|
|
|||
|
|
@ -571,6 +571,8 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
|
|||
radeon_crtc->max_cursor_width = CURSOR_WIDTH;
|
||||
radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
|
||||
}
|
||||
dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
|
||||
dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
|
||||
|
||||
#if 0
|
||||
radeon_crtc->mode_set.crtc = &radeon_crtc->base;
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
|
|||
}
|
||||
|
||||
/* 64 dwords should be enough for fence too */
|
||||
r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
|
||||
r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
|
||||
return r;
|
||||
|
|
|
|||
|
|
@ -34,14 +34,15 @@
|
|||
int radeon_semaphore_create(struct radeon_device *rdev,
|
||||
struct radeon_semaphore **semaphore)
|
||||
{
|
||||
uint32_t *cpu_addr;
|
||||
int i, r;
|
||||
|
||||
*semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL);
|
||||
if (*semaphore == NULL) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo,
|
||||
&(*semaphore)->sa_bo, 8, 8, true);
|
||||
r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &(*semaphore)->sa_bo,
|
||||
8 * RADEON_NUM_SYNCS, 8, true);
|
||||
if (r) {
|
||||
kfree(*semaphore);
|
||||
*semaphore = NULL;
|
||||
|
|
@ -49,7 +50,10 @@ int radeon_semaphore_create(struct radeon_device *rdev,
|
|||
}
|
||||
(*semaphore)->waiters = 0;
|
||||
(*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo);
|
||||
*((uint64_t*)radeon_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0;
|
||||
|
||||
cpu_addr = radeon_sa_bo_cpu_addr((*semaphore)->sa_bo);
|
||||
for (i = 0; i < RADEON_NUM_SYNCS; ++i)
|
||||
cpu_addr[i] = 0;
|
||||
|
||||
for (i = 0; i < RADEON_NUM_RINGS; ++i)
|
||||
(*semaphore)->sync_to[i] = NULL;
|
||||
|
|
@ -125,6 +129,7 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
|
|||
struct radeon_semaphore *semaphore,
|
||||
int ring)
|
||||
{
|
||||
unsigned count = 0;
|
||||
int i, r;
|
||||
|
||||
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
||||
|
|
@ -140,6 +145,12 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (++count > RADEON_NUM_SYNCS) {
|
||||
/* not enough room, wait manually */
|
||||
radeon_fence_wait_locked(fence);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* allocate enough space for sync command */
|
||||
r = radeon_ring_alloc(rdev, &rdev->ring[i], 16);
|
||||
if (r) {
|
||||
|
|
@ -164,6 +175,8 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
|
|||
|
||||
radeon_ring_commit(rdev, &rdev->ring[i]);
|
||||
radeon_fence_note_sync(fence, ring);
|
||||
|
||||
semaphore->gpu_addr += 8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -2526,14 +2526,7 @@ u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)
|
|||
bool rv770_dpm_vblank_too_short(struct radeon_device *rdev)
|
||||
{
|
||||
u32 vblank_time = r600_dpm_get_vblank_time(rdev);
|
||||
u32 switch_limit = 300;
|
||||
|
||||
/* quirks */
|
||||
/* ASUS K70AF */
|
||||
if ((rdev->pdev->device == 0x9553) &&
|
||||
(rdev->pdev->subsystem_vendor == 0x1043) &&
|
||||
(rdev->pdev->subsystem_device == 0x1c42))
|
||||
switch_limit = 200;
|
||||
u32 switch_limit = 200; /* 300 */
|
||||
|
||||
/* RV770 */
|
||||
/* mclk switching doesn't seem to work reliably on desktop RV770s */
|
||||
|
|
|
|||
|
|
@ -2395,7 +2395,7 @@ static int si_populate_sq_ramping_values(struct radeon_device *rdev,
|
|||
if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
|
||||
enable_sq_ramping = false;
|
||||
|
||||
if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
|
||||
if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
|
||||
enable_sq_ramping = false;
|
||||
|
||||
for (i = 0; i < state->performance_level_count; i++) {
|
||||
|
|
|
|||
|
|
@ -126,6 +126,7 @@ struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev,
|
|||
agp_be->ttm.func = &ttm_agp_func;
|
||||
|
||||
if (ttm_tt_init(&agp_be->ttm, bdev, size, page_flags, dummy_read_page)) {
|
||||
kfree(agp_be);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1223,9 +1223,19 @@ typedef enum {
|
|||
#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
|
||||
|
||||
#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
|
||||
|
||||
#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
|
||||
#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
|
||||
#define SVGA_3D_CMD_GB_MOB_FENCE 1133
|
||||
#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
|
||||
#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
|
||||
#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
|
||||
#define SVGA_3D_CMD_NOP_ERROR 1137
|
||||
|
||||
#define SVGA_3D_CMD_RESERVED1 1138
|
||||
#define SVGA_3D_CMD_RESERVED2 1139
|
||||
#define SVGA_3D_CMD_RESERVED3 1140
|
||||
#define SVGA_3D_CMD_RESERVED4 1141
|
||||
#define SVGA_3D_CMD_RESERVED5 1142
|
||||
|
||||
#define SVGA_3D_CMD_MAX 1142
|
||||
#define SVGA_3D_CMD_FUTURE_MAX 3000
|
||||
|
|
@ -1973,8 +1983,7 @@ struct {
|
|||
uint32 sizeInBytes;
|
||||
uint32 validSizeInBytes;
|
||||
SVGAMobFormat ptDepth;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
|
||||
|
||||
typedef
|
||||
|
|
@ -1984,15 +1993,13 @@ struct {
|
|||
uint32 sizeInBytes;
|
||||
uint32 validSizeInBytes;
|
||||
SVGAMobFormat ptDepth;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
SVGAOTableType type;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
|
||||
|
||||
/*
|
||||
|
|
@ -2005,8 +2012,7 @@ struct SVGA3dCmdDefineGBMob {
|
|||
SVGAMobFormat ptDepth;
|
||||
PPN base;
|
||||
uint32 sizeInBytes;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
|
||||
|
||||
|
||||
|
|
@ -2017,8 +2023,7 @@ SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
|
|||
typedef
|
||||
struct SVGA3dCmdDestroyGBMob {
|
||||
SVGAMobId mobid;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
|
||||
|
||||
/*
|
||||
|
|
@ -2031,8 +2036,7 @@ struct SVGA3dCmdRedefineGBMob {
|
|||
SVGAMobFormat ptDepth;
|
||||
PPN base;
|
||||
uint32 sizeInBytes;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
|
||||
|
||||
/*
|
||||
|
|
@ -2045,8 +2049,7 @@ struct SVGA3dCmdDefineGBMob64 {
|
|||
SVGAMobFormat ptDepth;
|
||||
PPN64 base;
|
||||
uint32 sizeInBytes;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
|
||||
|
||||
/*
|
||||
|
|
@ -2059,8 +2062,7 @@ struct SVGA3dCmdRedefineGBMob64 {
|
|||
SVGAMobFormat ptDepth;
|
||||
PPN64 base;
|
||||
uint32 sizeInBytes;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
|
||||
|
||||
/*
|
||||
|
|
@ -2070,8 +2072,7 @@ SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
|
|||
typedef
|
||||
struct SVGA3dCmdUpdateGBMobMapping {
|
||||
SVGAMobId mobid;
|
||||
}
|
||||
__attribute__((__packed__))
|
||||
} __packed
|
||||
SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
|
||||
|
||||
/*
|
||||
|
|
@ -2087,7 +2088,8 @@ struct SVGA3dCmdDefineGBSurface {
|
|||
uint32 multisampleCount;
|
||||
SVGA3dTextureFilter autogenFilter;
|
||||
SVGA3dSize size;
|
||||
} SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
|
||||
} __packed
|
||||
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
|
||||
|
||||
/*
|
||||
* Destroy a guest-backed surface.
|
||||
|
|
@ -2096,7 +2098,8 @@ struct SVGA3dCmdDefineGBSurface {
|
|||
typedef
|
||||
struct SVGA3dCmdDestroyGBSurface {
|
||||
uint32 sid;
|
||||
} SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
|
||||
} __packed
|
||||
SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
|
||||
|
||||
/*
|
||||
* Bind a guest-backed surface to an object.
|
||||
|
|
@ -2106,7 +2109,8 @@ typedef
|
|||
struct SVGA3dCmdBindGBSurface {
|
||||
uint32 sid;
|
||||
SVGAMobId mobid;
|
||||
} SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
|
||||
} __packed
|
||||
SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
|
||||
|
||||
/*
|
||||
* Conditionally bind a mob to a guest backed surface if testMobid
|
||||
|
|
@ -2123,7 +2127,7 @@ struct{
|
|||
SVGAMobId testMobid;
|
||||
SVGAMobId mobid;
|
||||
uint32 flags;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
|
||||
|
||||
/*
|
||||
|
|
@ -2135,7 +2139,8 @@ typedef
|
|||
struct SVGA3dCmdUpdateGBImage {
|
||||
SVGA3dSurfaceImageId image;
|
||||
SVGA3dBox box;
|
||||
} SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
|
||||
} __packed
|
||||
SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
|
||||
|
||||
/*
|
||||
* Update an entire guest-backed surface.
|
||||
|
|
@ -2145,7 +2150,8 @@ struct SVGA3dCmdUpdateGBImage {
|
|||
typedef
|
||||
struct SVGA3dCmdUpdateGBSurface {
|
||||
uint32 sid;
|
||||
} SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
|
||||
} __packed
|
||||
SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
|
||||
|
||||
/*
|
||||
* Readback an image in a guest-backed surface.
|
||||
|
|
@ -2155,7 +2161,8 @@ struct SVGA3dCmdUpdateGBSurface {
|
|||
typedef
|
||||
struct SVGA3dCmdReadbackGBImage {
|
||||
SVGA3dSurfaceImageId image;
|
||||
} SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
|
||||
} __packed
|
||||
SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
|
||||
|
||||
/*
|
||||
* Readback an entire guest-backed surface.
|
||||
|
|
@ -2165,7 +2172,8 @@ struct SVGA3dCmdReadbackGBImage {
|
|||
typedef
|
||||
struct SVGA3dCmdReadbackGBSurface {
|
||||
uint32 sid;
|
||||
} SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
|
||||
} __packed
|
||||
SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
|
||||
|
||||
/*
|
||||
* Readback a sub rect of an image in a guest-backed surface. After
|
||||
|
|
@ -2179,7 +2187,7 @@ struct SVGA3dCmdReadbackGBImagePartial {
|
|||
SVGA3dSurfaceImageId image;
|
||||
SVGA3dBox box;
|
||||
uint32 invertBox;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
|
||||
|
||||
/*
|
||||
|
|
@ -2190,7 +2198,8 @@ SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
|
|||
typedef
|
||||
struct SVGA3dCmdInvalidateGBImage {
|
||||
SVGA3dSurfaceImageId image;
|
||||
} SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
|
||||
} __packed
|
||||
SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
|
||||
|
||||
/*
|
||||
* Invalidate an entire guest-backed surface.
|
||||
|
|
@ -2200,7 +2209,8 @@ struct SVGA3dCmdInvalidateGBImage {
|
|||
typedef
|
||||
struct SVGA3dCmdInvalidateGBSurface {
|
||||
uint32 sid;
|
||||
} SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
|
||||
} __packed
|
||||
SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
|
||||
|
||||
/*
|
||||
* Invalidate a sub rect of an image in a guest-backed surface. After
|
||||
|
|
@ -2214,7 +2224,7 @@ struct SVGA3dCmdInvalidateGBImagePartial {
|
|||
SVGA3dSurfaceImageId image;
|
||||
SVGA3dBox box;
|
||||
uint32 invertBox;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
|
||||
|
||||
/*
|
||||
|
|
@ -2224,7 +2234,8 @@ SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
|
|||
typedef
|
||||
struct SVGA3dCmdDefineGBContext {
|
||||
uint32 cid;
|
||||
} SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
|
||||
} __packed
|
||||
SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
|
||||
|
||||
/*
|
||||
* Destroy a guest-backed context.
|
||||
|
|
@ -2233,7 +2244,8 @@ struct SVGA3dCmdDefineGBContext {
|
|||
typedef
|
||||
struct SVGA3dCmdDestroyGBContext {
|
||||
uint32 cid;
|
||||
} SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
|
||||
} __packed
|
||||
SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
|
||||
|
||||
/*
|
||||
* Bind a guest-backed context.
|
||||
|
|
@ -2252,7 +2264,8 @@ struct SVGA3dCmdBindGBContext {
|
|||
uint32 cid;
|
||||
SVGAMobId mobid;
|
||||
uint32 validContents;
|
||||
} SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
|
||||
} __packed
|
||||
SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
|
||||
|
||||
/*
|
||||
* Readback a guest-backed context.
|
||||
|
|
@ -2262,7 +2275,8 @@ struct SVGA3dCmdBindGBContext {
|
|||
typedef
|
||||
struct SVGA3dCmdReadbackGBContext {
|
||||
uint32 cid;
|
||||
} SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
|
||||
} __packed
|
||||
SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
|
||||
|
||||
/*
|
||||
* Invalidate a guest-backed context.
|
||||
|
|
@ -2270,7 +2284,8 @@ struct SVGA3dCmdReadbackGBContext {
|
|||
typedef
|
||||
struct SVGA3dCmdInvalidateGBContext {
|
||||
uint32 cid;
|
||||
} SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
|
||||
} __packed
|
||||
SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
|
||||
|
||||
/*
|
||||
* Define a guest-backed shader.
|
||||
|
|
@ -2281,7 +2296,8 @@ struct SVGA3dCmdDefineGBShader {
|
|||
uint32 shid;
|
||||
SVGA3dShaderType type;
|
||||
uint32 sizeInBytes;
|
||||
} SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
|
||||
} __packed
|
||||
SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
|
||||
|
||||
/*
|
||||
* Bind a guest-backed shader.
|
||||
|
|
@ -2291,7 +2307,8 @@ typedef struct SVGA3dCmdBindGBShader {
|
|||
uint32 shid;
|
||||
SVGAMobId mobid;
|
||||
uint32 offsetInBytes;
|
||||
} SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
|
||||
} __packed
|
||||
SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
|
||||
|
||||
/*
|
||||
* Destroy a guest-backed shader.
|
||||
|
|
@ -2299,7 +2316,8 @@ typedef struct SVGA3dCmdBindGBShader {
|
|||
|
||||
typedef struct SVGA3dCmdDestroyGBShader {
|
||||
uint32 shid;
|
||||
} SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
|
||||
} __packed
|
||||
SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
|
|
@ -2314,14 +2332,16 @@ struct {
|
|||
* Note that FLOAT and INT constants are 4-dwords in length, while
|
||||
* BOOL constants are 1-dword in length.
|
||||
*/
|
||||
} SVGA3dCmdSetGBShaderConstInline;
|
||||
} __packed
|
||||
SVGA3dCmdSetGBShaderConstInline;
|
||||
/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
uint32 cid;
|
||||
SVGA3dQueryType type;
|
||||
} SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
|
||||
} __packed
|
||||
SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
|
|
@ -2329,7 +2349,8 @@ struct {
|
|||
SVGA3dQueryType type;
|
||||
SVGAMobId mobid;
|
||||
uint32 offset;
|
||||
} SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
|
||||
} __packed
|
||||
SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -2346,21 +2367,22 @@ struct {
|
|||
SVGA3dQueryType type;
|
||||
SVGAMobId mobid;
|
||||
uint32 offset;
|
||||
} SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
|
||||
} __packed
|
||||
SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
SVGAMobId mobid;
|
||||
uint32 fbOffset;
|
||||
uint32 initalized;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
SVGAMobId mobid;
|
||||
uint32 gartOffset;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
|
||||
|
||||
|
||||
|
|
@ -2368,7 +2390,7 @@ typedef
|
|||
struct {
|
||||
uint32 gartOffset;
|
||||
uint32 numPages;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
|
||||
|
||||
|
||||
|
|
@ -2385,27 +2407,27 @@ struct {
|
|||
int32 xRoot;
|
||||
int32 yRoot;
|
||||
uint32 flags;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
uint32 stid;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
uint32 stid;
|
||||
SVGA3dSurfaceImageId image;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
|
||||
|
||||
typedef
|
||||
struct {
|
||||
uint32 stid;
|
||||
SVGA3dBox box;
|
||||
}
|
||||
} __packed
|
||||
SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -38,8 +38,11 @@
|
|||
|
||||
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
|
||||
#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
|
||||
#define min_t(type, x, y) ((x) < (y) ? (x) : (y))
|
||||
#define surf_size_struct SVGA3dSize
|
||||
#define u32 uint32
|
||||
#define u64 uint64_t
|
||||
#define U32_MAX ((u32)~0U)
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
|
@ -704,8 +707,8 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
|
|||
|
||||
static inline u32 clamped_umul32(u32 a, u32 b)
|
||||
{
|
||||
uint64_t tmp = (uint64_t) a*b;
|
||||
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
|
||||
u64 tmp = (u64) a*b;
|
||||
return (tmp > (u64) U32_MAX) ? U32_MAX : tmp;
|
||||
}
|
||||
|
||||
static inline const struct svga3d_surface_desc *
|
||||
|
|
@ -834,7 +837,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
|
|||
bool cubemap)
|
||||
{
|
||||
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
|
||||
u32 total_size = 0;
|
||||
u64 total_size = 0;
|
||||
u32 mip;
|
||||
|
||||
for (mip = 0; mip < num_mip_levels; mip++) {
|
||||
|
|
@ -847,7 +850,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
|
|||
if (cubemap)
|
||||
total_size *= SVGA3D_MAX_SURFACE_FACES;
|
||||
|
||||
return total_size;
|
||||
return (u32) min_t(u64, total_size, (u64) U32_MAX);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -169,10 +169,17 @@ enum {
|
|||
SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
|
||||
SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
|
||||
SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
|
||||
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
|
||||
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
|
||||
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
|
||||
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
|
||||
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
|
||||
SVGA_REG_TOP = 53, /* Must be 1 more than the last register */
|
||||
SVGA_REG_CMD_PREPEND_LOW = 53,
|
||||
SVGA_REG_CMD_PREPEND_HIGH = 54,
|
||||
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
|
||||
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
|
||||
SVGA_REG_MOB_MAX_SIZE = 57,
|
||||
SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
|
||||
|
||||
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
|
||||
/* Next 768 (== 256*3) registers exist for colormap */
|
||||
|
|
|
|||
|
|
@ -551,8 +551,7 @@ static int vmw_context_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
|
|||
cmd->header.size = sizeof(cmd->body);
|
||||
cmd->body.cid = bi->ctx->id;
|
||||
cmd->body.type = bi->i1.shader_type;
|
||||
cmd->body.shid =
|
||||
cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
|
||||
cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
|
||||
return 0;
|
||||
|
|
@ -585,8 +584,7 @@ static int vmw_context_scrub_render_target(struct vmw_ctx_bindinfo *bi,
|
|||
cmd->header.size = sizeof(cmd->body);
|
||||
cmd->body.cid = bi->ctx->id;
|
||||
cmd->body.type = bi->i1.rt_type;
|
||||
cmd->body.target.sid =
|
||||
cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
|
||||
cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
|
||||
cmd->body.target.face = 0;
|
||||
cmd->body.target.mipmap = 0;
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
|
|
@ -628,8 +626,7 @@ static int vmw_context_scrub_texture(struct vmw_ctx_bindinfo *bi,
|
|||
cmd->body.c.cid = bi->ctx->id;
|
||||
cmd->body.s1.stage = bi->i1.texture_stage;
|
||||
cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
|
||||
cmd->body.s1.value =
|
||||
cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
|
||||
cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -667,6 +667,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
|||
dev_priv->memory_size = 512*1024*1024;
|
||||
}
|
||||
dev_priv->max_mob_pages = 0;
|
||||
dev_priv->max_mob_size = 0;
|
||||
if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
|
||||
uint64_t mem_size =
|
||||
vmw_read(dev_priv,
|
||||
|
|
@ -676,6 +677,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
|||
dev_priv->prim_bb_mem =
|
||||
vmw_read(dev_priv,
|
||||
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
|
||||
dev_priv->max_mob_size =
|
||||
vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
|
||||
} else
|
||||
dev_priv->prim_bb_mem = dev_priv->vram_size;
|
||||
|
||||
|
|
|
|||
|
|
@ -386,6 +386,7 @@ struct vmw_private {
|
|||
uint32_t max_gmr_ids;
|
||||
uint32_t max_gmr_pages;
|
||||
uint32_t max_mob_pages;
|
||||
uint32_t max_mob_size;
|
||||
uint32_t memory_size;
|
||||
bool has_gmr;
|
||||
bool has_mob;
|
||||
|
|
|
|||
|
|
@ -602,7 +602,7 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
|
|||
{
|
||||
struct vmw_cid_cmd {
|
||||
SVGA3dCmdHeader header;
|
||||
__le32 cid;
|
||||
uint32_t cid;
|
||||
} *cmd;
|
||||
|
||||
cmd = container_of(header, struct vmw_cid_cmd, header);
|
||||
|
|
@ -1835,7 +1835,7 @@ static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct vmw_cmd_entry const vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
|
||||
static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid,
|
||||
false, false, false),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid,
|
||||
|
|
@ -2032,6 +2032,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
|
|||
goto out_invalid;
|
||||
|
||||
entry = &vmw_cmd_entries[cmd_id];
|
||||
if (unlikely(!entry->func))
|
||||
goto out_invalid;
|
||||
|
||||
if (unlikely(!entry->user_allow && !sw_context->kernel))
|
||||
goto out_privileged;
|
||||
|
||||
|
|
@ -2469,7 +2472,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,
|
|||
if (dev_priv->has_mob) {
|
||||
ret = vmw_rebind_contexts(sw_context);
|
||||
if (unlikely(ret != 0))
|
||||
goto out_err;
|
||||
goto out_unlock_binding;
|
||||
}
|
||||
|
||||
cmd = vmw_fifo_reserve(dev_priv, command_size);
|
||||
|
|
|
|||
|
|
@ -102,6 +102,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
|
|||
vmw_fp->gb_aware = true;
|
||||
param->value = dev_priv->max_mob_pages * PAGE_SIZE;
|
||||
break;
|
||||
case DRM_VMW_PARAM_MAX_MOB_SIZE:
|
||||
param->value = dev_priv->max_mob_size;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Illegal vmwgfx get param request: %d\n",
|
||||
param->param);
|
||||
|
|
|
|||
|
|
@ -371,13 +371,13 @@ int vmw_shader_destroy_ioctl(struct drm_device *dev, void *data,
|
|||
TTM_REF_USAGE);
|
||||
}
|
||||
|
||||
int vmw_shader_alloc(struct vmw_private *dev_priv,
|
||||
struct vmw_dma_buffer *buffer,
|
||||
size_t shader_size,
|
||||
size_t offset,
|
||||
SVGA3dShaderType shader_type,
|
||||
struct ttm_object_file *tfile,
|
||||
u32 *handle)
|
||||
static int vmw_shader_alloc(struct vmw_private *dev_priv,
|
||||
struct vmw_dma_buffer *buffer,
|
||||
size_t shader_size,
|
||||
size_t offset,
|
||||
SVGA3dShaderType shader_type,
|
||||
struct ttm_object_file *tfile,
|
||||
u32 *handle)
|
||||
{
|
||||
struct vmw_user_shader *ushader;
|
||||
struct vmw_resource *res, *tmp;
|
||||
|
|
@ -779,6 +779,8 @@ vmw_compat_shader_man_create(struct vmw_private *dev_priv)
|
|||
int ret;
|
||||
|
||||
man = kzalloc(sizeof(*man), GFP_KERNEL);
|
||||
if (man == NULL)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
man->dev_priv = dev_priv;
|
||||
INIT_LIST_HEAD(&man->list);
|
||||
|
|
|
|||
|
|
@ -907,6 +907,9 @@ struct drm_mode_config {
|
|||
|
||||
/* whether async page flip is supported or not */
|
||||
bool async_page_flip;
|
||||
|
||||
/* cursor size */
|
||||
uint32_t cursor_width, cursor_height;
|
||||
};
|
||||
|
||||
#define obj_to_crtc(x) container_of(x, struct drm_crtc, base)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
#include <drm/ttm/ttm_bo_driver.h>
|
||||
#include <drm/ttm/ttm_memory.h>
|
||||
|
||||
struct device;
|
||||
|
||||
/**
|
||||
* Initialize pool allocator.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -619,6 +619,8 @@ struct drm_gem_open {
|
|||
#define DRM_PRIME_CAP_EXPORT 0x2
|
||||
#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
|
||||
#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
|
||||
#define DRM_CAP_CURSOR_WIDTH 0x8
|
||||
#define DRM_CAP_CURSOR_HEIGHT 0x9
|
||||
|
||||
/** DRM_IOCTL_GET_CAP ioctl argument type */
|
||||
struct drm_get_cap {
|
||||
|
|
|
|||
|
|
@ -87,6 +87,7 @@
|
|||
#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
|
||||
#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
|
||||
#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
|
||||
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
|
||||
|
||||
/**
|
||||
* struct drm_vmw_getparam_arg
|
||||
|
|
|
|||
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