net/mlx5e: Allow coexistence of CQE compression and HW TS PTP
Update setting HW time-stamp to allow coexistence with CQE compression. Turn on RX PTP indication and try to reopen the channels. On success, coexistence with CQE compression is enabled. Otherwise, fall-back to turning off CQE compression. Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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e5fe49465d
Коммит
960fbfe222
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@ -269,6 +269,7 @@ struct mlx5e_params {
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struct mlx5e_xsk *xsk;
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unsigned int sw_mtu;
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int hard_mtu;
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bool ptp_rx;
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};
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enum {
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@ -579,6 +579,9 @@ static int mlx5e_ptp_set_state(struct mlx5e_ptp *c, struct mlx5e_params *params)
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if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_TX_PORT_TS))
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__set_bit(MLX5E_PTP_STATE_TX, c->state);
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if (params->ptp_rx)
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__set_bit(MLX5E_PTP_STATE_RX, c->state);
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return bitmap_empty(c->state, MLX5E_PTP_STATE_NUM_STATES) ? -EINVAL : 0;
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}
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@ -2087,7 +2087,7 @@ int mlx5e_open_channels(struct mlx5e_priv *priv,
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goto err_close_channels;
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}
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if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS)) {
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if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
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err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
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if (err)
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goto err_close_channels;
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@ -2688,6 +2688,8 @@ static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
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nch = priv->channels.params.num_channels;
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ntc = priv->channels.params.num_tc;
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num_rxqs = nch * priv->profile->rq_groups;
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if (priv->channels.params.ptp_rx)
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num_rxqs++;
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mlx5e_netdev_set_tcs(netdev, nch, ntc);
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@ -3968,9 +3970,18 @@ static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
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return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
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}
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static int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
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{
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bool set = *(bool *)ctx;
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return mlx5e_ptp_rx_manage_fs(priv, set);
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}
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int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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{
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struct mlx5e_channels new_channels = {};
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struct hwtstamp_config config;
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bool rx_cqe_compress_def;
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int err;
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if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
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@ -3990,11 +4001,13 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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}
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mutex_lock(&priv->state_lock);
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new_channels.params = priv->channels.params;
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rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
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/* RX HW timestamp */
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switch (config.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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/* Reset CQE compression to Admin default */
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mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
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new_channels.params.ptp_rx = false;
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break;
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case HWTSTAMP_FILTER_ALL:
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case HWTSTAMP_FILTER_SOME:
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@ -4011,15 +4024,7 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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case HWTSTAMP_FILTER_NTP_ALL:
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/* Disable CQE compression */
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if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
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netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
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err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
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if (err) {
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netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
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mutex_unlock(&priv->state_lock);
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return err;
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}
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new_channels.params.ptp_rx = rx_cqe_compress_def;
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config.rx_filter = HWTSTAMP_FILTER_ALL;
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break;
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default:
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@ -4027,6 +4032,20 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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return -ERANGE;
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}
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if (new_channels.params.ptp_rx == priv->channels.params.ptp_rx)
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goto out;
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if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
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priv->channels.params = new_channels.params;
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goto out;
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}
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err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_ptp_rx_manage_fs_ctx,
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&new_channels.params.ptp_rx);
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if (err) {
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mutex_unlock(&priv->state_lock);
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return err;
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}
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out:
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memcpy(&priv->tstamp, &config, sizeof(config));
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mutex_unlock(&priv->state_lock);
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