rt2x00: Add TXOP_CTRL_CFG register definition
Remove the magic value initialisation of the TXOP_CTRL_CFG register by defining its fields and using them during intialisation. The field RESERVED_TRUN_EN is referred to as reserved, however it is set to 1 by the legacy drivers. Hence, do the same. Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -960,8 +960,31 @@
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/*
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* TXOP_CTRL_CFG:
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* TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
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* AC_TRUN_EN: Enable/Disable truncation for AC change
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* TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
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* USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
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* MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
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* RESERVED_TRUN_EN: Reserved
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* LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
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* EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
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* transmissions if extension CCA is clear).
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* EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
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* EXT_CWMIN: CwMin for extension channel backoff
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* 0: Disabled
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*
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*/
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#define TXOP_CTRL_CFG 0x1340
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#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
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#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
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#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
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#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
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#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
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#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
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#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
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#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
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#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
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#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
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/*
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* TX_RTS_CFG:
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@ -2097,7 +2097,23 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
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rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
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}
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rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
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/*
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* The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
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* although it is reserved.
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*/
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rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
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rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
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rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
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rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
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rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
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