Merge branch 'raid56-scrub-replace' of git://github.com/miaoxie/linux-btrfs into for-linus
This commit is contained in:
Коммит
9627aeee3e
|
@ -30,10 +30,6 @@ should only be used when a device has multiple interrupt parents.
|
|||
Example:
|
||||
interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
|
||||
|
||||
A device node may contain either "interrupts" or "interrupts-extended", but not
|
||||
both. If both properties are present, then the operating system should log an
|
||||
error and use only the data in "interrupts".
|
||||
|
||||
2) Interrupt controller nodes
|
||||
-----------------------------
|
||||
|
||||
|
|
|
@ -7,3 +7,14 @@ And for the interrupt mapping part:
|
|||
|
||||
Open Firmware Recommended Practice: Interrupt Mapping
|
||||
http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
|
||||
|
||||
Additionally to the properties specified in the above standards a host bridge
|
||||
driver implementation may support the following properties:
|
||||
|
||||
- linux,pci-domain:
|
||||
If present this property assigns a fixed PCI domain number to a host bridge,
|
||||
otherwise an unstable (across boots) unique number will be assigned.
|
||||
It is required to either not set this property at all or set it for all
|
||||
host bridges in the system, otherwise potentially conflicting domain numbers
|
||||
may be assigned to root buses behind different host bridges. The domain
|
||||
number for each host bridge in the system must be unique.
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
TZ1090-PDC's pin configuration nodes act as a container for an abitrary number
|
||||
TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
|
||||
of subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
TZ1090's pin configuration nodes act as a container for an abitrary number of
|
||||
TZ1090's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Lantiq's pin configuration nodes act as a container for an abitrary number of
|
||||
Lantiq's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those group(s), and two pin configuration parameters:
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Lantiq's pin configuration nodes act as a container for an abitrary number of
|
||||
Lantiq's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those group(s), and two pin configuration parameters:
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an abitrary number of
|
||||
Tegra's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -13,7 +13,7 @@ Optional properties:
|
|||
Please refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes.
|
||||
SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes.
|
||||
Each of these subnodes represents some desired configuration for a group of pins.
|
||||
|
||||
Required subnode-properties:
|
||||
|
|
|
@ -32,7 +32,7 @@ Required properties:
|
|||
Please refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
|
||||
SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
|
||||
of these subnodes represents muxing for a pin, a group, or a list of pins or
|
||||
groups.
|
||||
|
||||
|
|
|
@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an abitrary number of
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -47,7 +47,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an abitrary number of
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an abitrary number of
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -47,7 +47,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an abitrary number of
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an abitrary number of
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -34,6 +34,7 @@ chipidea Chipidea, Inc
|
|||
chrp Common Hardware Reference Platform
|
||||
chunghwa Chunghwa Picture Tubes Ltd.
|
||||
cirrus Cirrus Logic, Inc.
|
||||
cnm Chips&Media, Inc.
|
||||
cortina Cortina Systems, Inc.
|
||||
crystalfontz Crystalfontz America, Inc.
|
||||
dallas Maxim Integrated Products (formerly Dallas Semiconductor)
|
||||
|
@ -92,6 +93,7 @@ maxim Maxim Integrated Products
|
|||
mediatek MediaTek Inc.
|
||||
micrel Micrel Inc.
|
||||
microchip Microchip Technology Inc.
|
||||
micron Micron Technology Inc.
|
||||
mitsubishi Mitsubishi Electric Corporation
|
||||
mosaixtech Mosaix Technologies, Inc.
|
||||
moxa Moxa
|
||||
|
@ -127,6 +129,7 @@ renesas Renesas Electronics Corporation
|
|||
ricoh Ricoh Co. Ltd.
|
||||
rockchip Fuzhou Rockchip Electronics Co., Ltd
|
||||
samsung Samsung Semiconductor
|
||||
sandisk Sandisk Corporation
|
||||
sbs Smart Battery System
|
||||
schindler Schindler
|
||||
seagate Seagate Technology PLC
|
||||
|
@ -138,7 +141,7 @@ silergy Silergy Corp.
|
|||
sirf SiRF Technology, Inc.
|
||||
sitronix Sitronix Technology Corporation
|
||||
smsc Standard Microsystems Corporation
|
||||
snps Synopsys, Inc.
|
||||
snps Synopsys, Inc.
|
||||
solidrun SolidRun
|
||||
sony Sony Corporation
|
||||
spansion Spansion Inc.
|
||||
|
|
|
@ -64,7 +64,7 @@ is formed.
|
|||
At mount time, the two directories given as mount options "lowerdir" and
|
||||
"upperdir" are combined into a merged directory:
|
||||
|
||||
mount -t overlayfs overlayfs -olowerdir=/lower,upperdir=/upper,\
|
||||
mount -t overlay overlay -olowerdir=/lower,upperdir=/upper,\
|
||||
workdir=/work /merged
|
||||
|
||||
The "workdir" needs to be an empty directory on the same filesystem
|
||||
|
|
|
@ -6888,11 +6888,12 @@ F: drivers/scsi/osd/
|
|||
F: include/scsi/osd_*
|
||||
F: fs/exofs/
|
||||
|
||||
OVERLAYFS FILESYSTEM
|
||||
OVERLAY FILESYSTEM
|
||||
M: Miklos Szeredi <miklos@szeredi.hu>
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
L: linux-unionfs@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git
|
||||
S: Supported
|
||||
F: fs/overlayfs/*
|
||||
F: fs/overlayfs/
|
||||
F: Documentation/filesystems/overlayfs.txt
|
||||
|
||||
P54 WIRELESS DRIVER
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 18
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Diseased Newt
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -433,7 +433,7 @@
|
|||
clocks = <&cpg_clocks R8A7740_CLK_S>,
|
||||
<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_B>,
|
||||
<&sub_clk>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_B>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
|
|
|
@ -666,9 +666,9 @@
|
|||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
sd3_clk: sd3_clk@e615007c {
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
|
||||
|
|
|
@ -361,6 +361,10 @@
|
|||
clocks = <&ahb1_gates 6>;
|
||||
resets = <&ahb1_rst 6>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
/* DMA controller requires AHB1 clocked from PLL6 */
|
||||
assigned-clocks = <&ahb1_mux>;
|
||||
assigned-clock-parents = <&pll6>;
|
||||
};
|
||||
|
||||
mmc0: mmc@01c0f000 {
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65913@58";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -15,6 +15,10 @@
|
|||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
|
@ -916,8 +920,6 @@
|
|||
regulator-name = "vddio-sdmmc3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb {
|
||||
|
@ -962,7 +964,7 @@
|
|||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vddio_sdmmc3>;
|
||||
vqmmc-supply = <&vddio_sdmmc3>;
|
||||
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
||||
power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
@ -971,7 +973,6 @@
|
|||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_1v8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
|
|
@ -15,6 +15,10 @@
|
|||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
|
@ -240,7 +244,6 @@
|
|||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_1v8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
|
|
@ -9,13 +9,6 @@
|
|||
compatible = "nvidia,tegra114";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra114-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00028000>;
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -286,7 +286,7 @@
|
|||
* the APB DMA based serial driver, the comptible is
|
||||
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
|
||||
*/
|
||||
serial@0,70006000 {
|
||||
uarta: serial@0,70006000 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -299,7 +299,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006040 {
|
||||
uartb: serial@0,70006040 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006040 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -312,7 +312,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006200 {
|
||||
uartc: serial@0,70006200 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006200 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -325,7 +325,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006300 {
|
||||
uartd: serial@0,70006300 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006300 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -6,6 +6,11 @@
|
|||
model = "Toradex Colibri T20 512MB on Iris";
|
||||
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Avionic Design Medcom-Wide board";
|
||||
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000c500/rtc@56";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/max8907@3c";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -9,14 +9,6 @@
|
|||
compatible = "nvidia,tegra20";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
|
|
|
@ -11,6 +11,10 @@
|
|||
rtc0 = "/i2c@7000c000/rtc@68";
|
||||
rtc1 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc2 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
pcie-controller@00003000 {
|
||||
|
|
|
@ -9,6 +9,7 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -30,6 +30,8 @@
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,9 @@
|
|||
rtc0 = "/i2c@7000c000/rtc@68";
|
||||
rtc1 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc2 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
|
|
|
@ -9,14 +9,6 @@
|
|||
compatible = "nvidia,tegra30";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
pcie-controller@00003000 {
|
||||
compatible = "nvidia,tegra30-pcie";
|
||||
device_type = "pci";
|
||||
|
|
|
@ -217,6 +217,7 @@ CONFIG_I2C_CADENCE=y
|
|||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_I2C_EXYNOS5=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_S3C2410=y
|
||||
CONFIG_I2C_SIRF=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_ST=y
|
||||
|
|
|
@ -455,7 +455,7 @@ enum {
|
|||
MSTP128, MSTP127, MSTP125,
|
||||
MSTP116, MSTP111, MSTP100, MSTP117,
|
||||
|
||||
MSTP230,
|
||||
MSTP230, MSTP229,
|
||||
MSTP222,
|
||||
MSTP218, MSTP217, MSTP216, MSTP214,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
|
@ -474,11 +474,12 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
|
||||
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
|
||||
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
|
||||
[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */
|
||||
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
|
||||
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
|
||||
[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
|
||||
|
@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]),
|
||||
|
||||
|
|
|
@ -68,7 +68,7 @@
|
|||
|
||||
#define SDCKCR 0xE6150074
|
||||
#define SD2CKCR 0xE6150078
|
||||
#define SD3CKCR 0xE615007C
|
||||
#define SD3CKCR 0xE615026C
|
||||
#define MMC0CKCR 0xE6150240
|
||||
#define MMC1CKCR 0xE6150244
|
||||
#define SSPCKCR 0xE6150248
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c/i2c-sh_mobile.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_dma.h>
|
||||
|
@ -192,11 +193,18 @@ static struct resource i2c4_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct i2c_sh_mobile_platform_data i2c_platform_data = {
|
||||
.clks_per_count = 2,
|
||||
};
|
||||
|
||||
static struct platform_device i2c0_device = {
|
||||
.name = "i2c-sh_mobile",
|
||||
.id = 0,
|
||||
.resource = i2c0_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c0_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c1_device = {
|
||||
|
@ -204,6 +212,9 @@ static struct platform_device i2c1_device = {
|
|||
.id = 1,
|
||||
.resource = i2c1_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c1_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c2_device = {
|
||||
|
@ -211,6 +222,9 @@ static struct platform_device i2c2_device = {
|
|||
.id = 2,
|
||||
.resource = i2c2_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c2_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c3_device = {
|
||||
|
@ -218,6 +232,9 @@ static struct platform_device i2c3_device = {
|
|||
.id = 3,
|
||||
.resource = i2c3_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c3_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c4_device = {
|
||||
|
@ -225,6 +242,9 @@ static struct platform_device i2c4_device = {
|
|||
.id = 4,
|
||||
.resource = i2c4_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c4_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
|
||||
|
|
|
@ -20,9 +20,15 @@
|
|||
#define WORD_INSN ".word"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
#define NOP_INSN "nop32"
|
||||
#else
|
||||
#define NOP_INSN "nop"
|
||||
#endif
|
||||
|
||||
static __always_inline bool arch_static_branch(struct static_key *key)
|
||||
{
|
||||
asm_volatile_goto("1:\tnop\n\t"
|
||||
asm_volatile_goto("1:\t" NOP_INSN "\n\t"
|
||||
"nop\n\t"
|
||||
".pushsection __jump_table, \"aw\"\n\t"
|
||||
WORD_INSN " 1b, %l[l_yes], %0\n\t"
|
||||
|
|
|
@ -41,10 +41,8 @@
|
|||
#define cpu_has_mcheck 0
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_mips32r1 0
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_prefetch 0
|
||||
|
|
|
@ -301,7 +301,8 @@ do { \
|
|||
__get_kernel_common((x), size, __gu_ptr); \
|
||||
else \
|
||||
__get_user_common((x), size, __gu_ptr); \
|
||||
} \
|
||||
} else \
|
||||
(x) = 0; \
|
||||
\
|
||||
__gu_err; \
|
||||
})
|
||||
|
@ -316,6 +317,7 @@ do { \
|
|||
" .insn \n" \
|
||||
" .section .fixup,\"ax\" \n" \
|
||||
"3: li %0, %4 \n" \
|
||||
" move %1, $0 \n" \
|
||||
" j 2b \n" \
|
||||
" .previous \n" \
|
||||
" .section __ex_table,\"a\" \n" \
|
||||
|
@ -630,6 +632,7 @@ do { \
|
|||
" .insn \n" \
|
||||
" .section .fixup,\"ax\" \n" \
|
||||
"3: li %0, %4 \n" \
|
||||
" move %1, $0 \n" \
|
||||
" j 2b \n" \
|
||||
" .previous \n" \
|
||||
" .section __ex_table,\"a\" \n" \
|
||||
|
@ -773,10 +776,11 @@ extern void __put_user_unaligned_unknown(void);
|
|||
"jal\t" #destination "\n\t"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
|
||||
#define DADDI_SCRATCH "$0"
|
||||
#else
|
||||
#if defined(CONFIG_CPU_DADDI_WORKAROUNDS) || (defined(CONFIG_EVA) && \
|
||||
defined(CONFIG_CPU_HAS_PREFETCH))
|
||||
#define DADDI_SCRATCH "$3"
|
||||
#else
|
||||
#define DADDI_SCRATCH "$0"
|
||||
#endif
|
||||
|
||||
extern size_t __copy_user(void *__to, const void *__from, size_t __n);
|
||||
|
|
|
@ -757,31 +757,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
c->cputype = CPU_LOONGSON2;
|
||||
__cpu_name[cpu] = "ICT Loongson-2";
|
||||
set_elf_platform(cpu, "loongson2e");
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
break;
|
||||
case PRID_REV_LOONGSON2F:
|
||||
c->cputype = CPU_LOONGSON2;
|
||||
__cpu_name[cpu] = "ICT Loongson-2";
|
||||
set_elf_platform(cpu, "loongson2f");
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
break;
|
||||
case PRID_REV_LOONGSON3A:
|
||||
c->cputype = CPU_LOONGSON3;
|
||||
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
||||
__cpu_name[cpu] = "ICT Loongson-3";
|
||||
set_elf_platform(cpu, "loongson3a");
|
||||
set_isa(c, MIPS_CPU_ISA_M64R1);
|
||||
break;
|
||||
case PRID_REV_LOONGSON3B_R1:
|
||||
case PRID_REV_LOONGSON3B_R2:
|
||||
c->cputype = CPU_LOONGSON3;
|
||||
__cpu_name[cpu] = "ICT Loongson-3";
|
||||
set_elf_platform(cpu, "loongson3b");
|
||||
set_isa(c, MIPS_CPU_ISA_M64R1);
|
||||
break;
|
||||
}
|
||||
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS |
|
||||
MIPS_CPU_FPU | MIPS_CPU_LLSC |
|
||||
MIPS_CPU_32FPR;
|
||||
c->tlbsize = 64;
|
||||
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
||||
break;
|
||||
case PRID_IMP_LOONGSON_32: /* Loongson-1 */
|
||||
decode_configs(c);
|
||||
|
|
|
@ -18,31 +18,53 @@
|
|||
|
||||
#ifdef HAVE_JUMP_LABEL
|
||||
|
||||
#define J_RANGE_MASK ((1ul << 28) - 1)
|
||||
/*
|
||||
* Define parameters for the standard MIPS and the microMIPS jump
|
||||
* instruction encoding respectively:
|
||||
*
|
||||
* - the ISA bit of the target, either 0 or 1 respectively,
|
||||
*
|
||||
* - the amount the jump target address is shifted right to fit in the
|
||||
* immediate field of the machine instruction, either 2 or 1,
|
||||
*
|
||||
* - the mask determining the size of the jump region relative to the
|
||||
* delay-slot instruction, either 256MB or 128MB,
|
||||
*
|
||||
* - the jump target alignment, either 4 or 2 bytes.
|
||||
*/
|
||||
#define J_ISA_BIT IS_ENABLED(CONFIG_CPU_MICROMIPS)
|
||||
#define J_RANGE_SHIFT (2 - J_ISA_BIT)
|
||||
#define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
|
||||
#define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
|
||||
|
||||
void arch_jump_label_transform(struct jump_entry *e,
|
||||
enum jump_label_type type)
|
||||
{
|
||||
union mips_instruction *insn_p;
|
||||
union mips_instruction insn;
|
||||
union mips_instruction *insn_p =
|
||||
(union mips_instruction *)(unsigned long)e->code;
|
||||
|
||||
/* Jump only works within a 256MB aligned region. */
|
||||
BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK));
|
||||
insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
|
||||
|
||||
/* Target must have 4 byte alignment. */
|
||||
BUG_ON((e->target & 3) != 0);
|
||||
/* Jump only works within an aligned region its delay slot is in. */
|
||||
BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
|
||||
|
||||
/* Target must have the right alignment and ISA must be preserved. */
|
||||
BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
|
||||
|
||||
if (type == JUMP_LABEL_ENABLE) {
|
||||
insn.j_format.opcode = j_op;
|
||||
insn.j_format.target = (e->target & J_RANGE_MASK) >> 2;
|
||||
insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
|
||||
insn.j_format.target = e->target >> J_RANGE_SHIFT;
|
||||
} else {
|
||||
insn.word = 0; /* nop */
|
||||
}
|
||||
|
||||
get_online_cpus();
|
||||
mutex_lock(&text_mutex);
|
||||
*insn_p = insn;
|
||||
if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
|
||||
insn_p->halfword[0] = insn.word >> 16;
|
||||
insn_p->halfword[1] = insn.word;
|
||||
} else
|
||||
*insn_p = insn;
|
||||
|
||||
flush_icache_range((unsigned long)insn_p,
|
||||
(unsigned long)insn_p + sizeof(*insn_p));
|
||||
|
|
|
@ -503,6 +503,7 @@
|
|||
STOREB(t0, NBYTES-2(dst), .Ls_exc_p1\@)
|
||||
.Ldone\@:
|
||||
jr ra
|
||||
nop
|
||||
.if __memcpy == 1
|
||||
END(memcpy)
|
||||
.set __memcpy, 0
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
static struct node_data prealloc__node_data[MAX_NUMNODES];
|
||||
unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
|
||||
EXPORT_SYMBOL(__node_distances);
|
||||
struct node_data *__node_data[MAX_NUMNODES];
|
||||
EXPORT_SYMBOL(__node_data);
|
||||
|
||||
|
|
|
@ -299,6 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
|||
|
||||
local_irq_save(flags);
|
||||
|
||||
htw_stop();
|
||||
pid = read_c0_entryhi() & ASID_MASK;
|
||||
address &= (PAGE_MASK << 1);
|
||||
write_c0_entryhi(address | pid);
|
||||
|
@ -346,6 +347,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
|||
tlb_write_indexed();
|
||||
}
|
||||
tlbw_use_hazard();
|
||||
htw_start();
|
||||
flush_itlb_vm(vma);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
@ -422,6 +424,7 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||
|
||||
local_irq_save(flags);
|
||||
/* Save old context and create impossible VPN2 value */
|
||||
htw_stop();
|
||||
old_ctx = read_c0_entryhi();
|
||||
old_pagemask = read_c0_pagemask();
|
||||
wired = read_c0_wired();
|
||||
|
@ -443,6 +446,7 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||
|
||||
write_c0_entryhi(old_ctx);
|
||||
write_c0_pagemask(old_pagemask);
|
||||
htw_start();
|
||||
out:
|
||||
local_irq_restore(flags);
|
||||
return ret;
|
||||
|
|
|
@ -92,7 +92,7 @@ static inline int unwind_user_frame(struct stackframe *old_frame,
|
|||
/* This marks the end of the previous function,
|
||||
which means we overran. */
|
||||
break;
|
||||
stack_size = (unsigned) stack_adjustment;
|
||||
stack_size = (unsigned long) stack_adjustment;
|
||||
} else if (is_ra_save_ins(&ip)) {
|
||||
int ra_slot = ip.i_format.simmediate;
|
||||
if (ra_slot < 0)
|
||||
|
|
|
@ -107,6 +107,7 @@ static void router_recurse(klrou_t *router_a, klrou_t *router_b, int depth)
|
|||
}
|
||||
|
||||
unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
|
||||
EXPORT_SYMBOL(__node_distances);
|
||||
|
||||
static int __init compute_node_distance(nasid_t nasid_a, nasid_t nasid_b)
|
||||
{
|
||||
|
|
|
@ -361,7 +361,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
|
|||
cascade_data->virq = virt_msir;
|
||||
msi->cascade_array[irq_index] = cascade_data;
|
||||
|
||||
ret = request_irq(virt_msir, fsl_msi_cascade, 0,
|
||||
ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
|
||||
"fsl-msi-cascade", cascade_data);
|
||||
if (ret) {
|
||||
dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
|
||||
|
|
|
@ -144,7 +144,7 @@ config INSTRUCTION_DECODER
|
|||
|
||||
config PERF_EVENTS_INTEL_UNCORE
|
||||
def_bool y
|
||||
depends on PERF_EVENTS && SUP_SUP_INTEL && PCI
|
||||
depends on PERF_EVENTS && CPU_SUP_INTEL && PCI
|
||||
|
||||
config OUTPUT_FORMAT
|
||||
string
|
||||
|
|
|
@ -20,7 +20,6 @@
|
|||
#define THREAD_SIZE_ORDER 1
|
||||
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
|
||||
|
||||
#define STACKFAULT_STACK 0
|
||||
#define DOUBLEFAULT_STACK 1
|
||||
#define NMI_STACK 0
|
||||
#define DEBUG_STACK 0
|
||||
|
|
|
@ -14,12 +14,11 @@
|
|||
#define IRQ_STACK_ORDER 2
|
||||
#define IRQ_STACK_SIZE (PAGE_SIZE << IRQ_STACK_ORDER)
|
||||
|
||||
#define STACKFAULT_STACK 1
|
||||
#define DOUBLEFAULT_STACK 2
|
||||
#define NMI_STACK 3
|
||||
#define DEBUG_STACK 4
|
||||
#define MCE_STACK 5
|
||||
#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
|
||||
#define DOUBLEFAULT_STACK 1
|
||||
#define NMI_STACK 2
|
||||
#define DEBUG_STACK 3
|
||||
#define MCE_STACK 4
|
||||
#define N_EXCEPTION_STACKS 4 /* hw limit: 7 */
|
||||
|
||||
#define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT)
|
||||
#define PUD_PAGE_MASK (~(PUD_PAGE_SIZE-1))
|
||||
|
|
|
@ -141,7 +141,7 @@ struct thread_info {
|
|||
/* Only used for 64 bit */
|
||||
#define _TIF_DO_NOTIFY_MASK \
|
||||
(_TIF_SIGPENDING | _TIF_MCE_NOTIFY | _TIF_NOTIFY_RESUME | \
|
||||
_TIF_USER_RETURN_NOTIFY)
|
||||
_TIF_USER_RETURN_NOTIFY | _TIF_UPROBE)
|
||||
|
||||
/* flags to check in __switch_to() */
|
||||
#define _TIF_WORK_CTXSW \
|
||||
|
|
|
@ -39,6 +39,7 @@ asmlinkage void simd_coprocessor_error(void);
|
|||
|
||||
#ifdef CONFIG_TRACING
|
||||
asmlinkage void trace_page_fault(void);
|
||||
#define trace_stack_segment stack_segment
|
||||
#define trace_divide_error divide_error
|
||||
#define trace_bounds bounds
|
||||
#define trace_invalid_op invalid_op
|
||||
|
|
|
@ -146,6 +146,8 @@ EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
|
|||
|
||||
static int __init x86_xsave_setup(char *s)
|
||||
{
|
||||
if (strlen(s))
|
||||
return 0;
|
||||
setup_clear_cpu_cap(X86_FEATURE_XSAVE);
|
||||
setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
|
||||
setup_clear_cpu_cap(X86_FEATURE_XSAVES);
|
||||
|
|
|
@ -465,6 +465,14 @@ static void mc_bp_resume(void)
|
|||
|
||||
if (uci->valid && uci->mc)
|
||||
microcode_ops->apply_microcode(cpu);
|
||||
else if (!uci->mc)
|
||||
/*
|
||||
* We might resume and not have applied late microcode but still
|
||||
* have a newer patch stashed from the early loader. We don't
|
||||
* have it in uci->mc so we have to load it the same way we're
|
||||
* applying patches early on the APs.
|
||||
*/
|
||||
load_ucode_ap();
|
||||
}
|
||||
|
||||
static struct syscore_ops mc_syscore_ops = {
|
||||
|
|
|
@ -486,14 +486,17 @@ static struct attribute_group snbep_uncore_qpi_format_group = {
|
|||
.attrs = snbep_uncore_qpi_formats_attr,
|
||||
};
|
||||
|
||||
#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
|
||||
.init_box = snbep_uncore_msr_init_box, \
|
||||
#define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
|
||||
.disable_box = snbep_uncore_msr_disable_box, \
|
||||
.enable_box = snbep_uncore_msr_enable_box, \
|
||||
.disable_event = snbep_uncore_msr_disable_event, \
|
||||
.enable_event = snbep_uncore_msr_enable_event, \
|
||||
.read_counter = uncore_msr_read_counter
|
||||
|
||||
#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
|
||||
__SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \
|
||||
.init_box = snbep_uncore_msr_init_box \
|
||||
|
||||
static struct intel_uncore_ops snbep_uncore_msr_ops = {
|
||||
SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
|
||||
};
|
||||
|
@ -1919,6 +1922,30 @@ static struct intel_uncore_type hswep_uncore_cbox = {
|
|||
.format_group = &hswep_uncore_cbox_format_group,
|
||||
};
|
||||
|
||||
/*
|
||||
* Write SBOX Initialization register bit by bit to avoid spurious #GPs
|
||||
*/
|
||||
static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box)
|
||||
{
|
||||
unsigned msr = uncore_msr_box_ctl(box);
|
||||
|
||||
if (msr) {
|
||||
u64 init = SNBEP_PMON_BOX_CTL_INT;
|
||||
u64 flags = 0;
|
||||
int i;
|
||||
|
||||
for_each_set_bit(i, (unsigned long *)&init, 64) {
|
||||
flags |= (1ULL << i);
|
||||
wrmsrl(msr, flags);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = {
|
||||
__SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
|
||||
.init_box = hswep_uncore_sbox_msr_init_box
|
||||
};
|
||||
|
||||
static struct attribute *hswep_uncore_sbox_formats_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
&format_attr_umask.attr,
|
||||
|
@ -1944,7 +1971,7 @@ static struct intel_uncore_type hswep_uncore_sbox = {
|
|||
.event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
|
||||
.box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
|
||||
.msr_offset = HSWEP_SBOX_MSR_OFFSET,
|
||||
.ops = &snbep_uncore_msr_ops,
|
||||
.ops = &hswep_uncore_sbox_msr_ops,
|
||||
.format_group = &hswep_uncore_sbox_format_group,
|
||||
};
|
||||
|
||||
|
@ -2025,13 +2052,27 @@ static struct intel_uncore_type hswep_uncore_imc = {
|
|||
SNBEP_UNCORE_PCI_COMMON_INIT(),
|
||||
};
|
||||
|
||||
static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8};
|
||||
|
||||
static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
|
||||
{
|
||||
struct pci_dev *pdev = box->pci_dev;
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
u64 count = 0;
|
||||
|
||||
pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
|
||||
pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static struct intel_uncore_ops hswep_uncore_irp_ops = {
|
||||
.init_box = snbep_uncore_pci_init_box,
|
||||
.disable_box = snbep_uncore_pci_disable_box,
|
||||
.enable_box = snbep_uncore_pci_enable_box,
|
||||
.disable_event = ivbep_uncore_irp_disable_event,
|
||||
.enable_event = ivbep_uncore_irp_enable_event,
|
||||
.read_counter = ivbep_uncore_irp_read_counter,
|
||||
.read_counter = hswep_uncore_irp_read_counter,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type hswep_uncore_irp = {
|
||||
|
|
|
@ -24,7 +24,6 @@ static char x86_stack_ids[][8] = {
|
|||
[ DEBUG_STACK-1 ] = "#DB",
|
||||
[ NMI_STACK-1 ] = "NMI",
|
||||
[ DOUBLEFAULT_STACK-1 ] = "#DF",
|
||||
[ STACKFAULT_STACK-1 ] = "#SS",
|
||||
[ MCE_STACK-1 ] = "#MC",
|
||||
#if DEBUG_STKSZ > EXCEPTION_STKSZ
|
||||
[ N_EXCEPTION_STACKS ...
|
||||
|
|
|
@ -828,9 +828,15 @@ ENTRY(native_iret)
|
|||
jnz native_irq_return_ldt
|
||||
#endif
|
||||
|
||||
.global native_irq_return_iret
|
||||
native_irq_return_iret:
|
||||
/*
|
||||
* This may fault. Non-paranoid faults on return to userspace are
|
||||
* handled by fixup_bad_iret. These include #SS, #GP, and #NP.
|
||||
* Double-faults due to espfix64 are handled in do_double_fault.
|
||||
* Other faults here are fatal.
|
||||
*/
|
||||
iretq
|
||||
_ASM_EXTABLE(native_irq_return_iret, bad_iret)
|
||||
|
||||
#ifdef CONFIG_X86_ESPFIX64
|
||||
native_irq_return_ldt:
|
||||
|
@ -858,25 +864,6 @@ native_irq_return_ldt:
|
|||
jmp native_irq_return_iret
|
||||
#endif
|
||||
|
||||
.section .fixup,"ax"
|
||||
bad_iret:
|
||||
/*
|
||||
* The iret traps when the %cs or %ss being restored is bogus.
|
||||
* We've lost the original trap vector and error code.
|
||||
* #GPF is the most likely one to get for an invalid selector.
|
||||
* So pretend we completed the iret and took the #GPF in user mode.
|
||||
*
|
||||
* We are now running with the kernel GS after exception recovery.
|
||||
* But error_entry expects us to have user GS to match the user %cs,
|
||||
* so swap back.
|
||||
*/
|
||||
pushq $0
|
||||
|
||||
SWAPGS
|
||||
jmp general_protection
|
||||
|
||||
.previous
|
||||
|
||||
/* edi: workmask, edx: work */
|
||||
retint_careful:
|
||||
CFI_RESTORE_STATE
|
||||
|
@ -922,37 +909,6 @@ ENTRY(retint_kernel)
|
|||
CFI_ENDPROC
|
||||
END(common_interrupt)
|
||||
|
||||
/*
|
||||
* If IRET takes a fault on the espfix stack, then we
|
||||
* end up promoting it to a doublefault. In that case,
|
||||
* modify the stack to make it look like we just entered
|
||||
* the #GP handler from user space, similar to bad_iret.
|
||||
*/
|
||||
#ifdef CONFIG_X86_ESPFIX64
|
||||
ALIGN
|
||||
__do_double_fault:
|
||||
XCPT_FRAME 1 RDI+8
|
||||
movq RSP(%rdi),%rax /* Trap on the espfix stack? */
|
||||
sarq $PGDIR_SHIFT,%rax
|
||||
cmpl $ESPFIX_PGD_ENTRY,%eax
|
||||
jne do_double_fault /* No, just deliver the fault */
|
||||
cmpl $__KERNEL_CS,CS(%rdi)
|
||||
jne do_double_fault
|
||||
movq RIP(%rdi),%rax
|
||||
cmpq $native_irq_return_iret,%rax
|
||||
jne do_double_fault /* This shouldn't happen... */
|
||||
movq PER_CPU_VAR(kernel_stack),%rax
|
||||
subq $(6*8-KERNEL_STACK_OFFSET),%rax /* Reset to original stack */
|
||||
movq %rax,RSP(%rdi)
|
||||
movq $0,(%rax) /* Missing (lost) #GP error code */
|
||||
movq $general_protection,RIP(%rdi)
|
||||
retq
|
||||
CFI_ENDPROC
|
||||
END(__do_double_fault)
|
||||
#else
|
||||
# define __do_double_fault do_double_fault
|
||||
#endif
|
||||
|
||||
/*
|
||||
* APIC interrupts.
|
||||
*/
|
||||
|
@ -1124,7 +1080,7 @@ idtentry overflow do_overflow has_error_code=0
|
|||
idtentry bounds do_bounds has_error_code=0
|
||||
idtentry invalid_op do_invalid_op has_error_code=0
|
||||
idtentry device_not_available do_device_not_available has_error_code=0
|
||||
idtentry double_fault __do_double_fault has_error_code=1 paranoid=1
|
||||
idtentry double_fault do_double_fault has_error_code=1 paranoid=1
|
||||
idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
|
||||
idtentry invalid_TSS do_invalid_TSS has_error_code=1
|
||||
idtentry segment_not_present do_segment_not_present has_error_code=1
|
||||
|
@ -1289,7 +1245,7 @@ apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
|
|||
|
||||
idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
||||
idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
||||
idtentry stack_segment do_stack_segment has_error_code=1 paranoid=1
|
||||
idtentry stack_segment do_stack_segment has_error_code=1
|
||||
#ifdef CONFIG_XEN
|
||||
idtentry xen_debug do_debug has_error_code=0
|
||||
idtentry xen_int3 do_int3 has_error_code=0
|
||||
|
@ -1399,17 +1355,16 @@ error_sti:
|
|||
|
||||
/*
|
||||
* There are two places in the kernel that can potentially fault with
|
||||
* usergs. Handle them here. The exception handlers after iret run with
|
||||
* kernel gs again, so don't set the user space flag. B stepping K8s
|
||||
* sometimes report an truncated RIP for IRET exceptions returning to
|
||||
* compat mode. Check for these here too.
|
||||
* usergs. Handle them here. B stepping K8s sometimes report a
|
||||
* truncated RIP for IRET exceptions returning to compat mode. Check
|
||||
* for these here too.
|
||||
*/
|
||||
error_kernelspace:
|
||||
CFI_REL_OFFSET rcx, RCX+8
|
||||
incl %ebx
|
||||
leaq native_irq_return_iret(%rip),%rcx
|
||||
cmpq %rcx,RIP+8(%rsp)
|
||||
je error_swapgs
|
||||
je error_bad_iret
|
||||
movl %ecx,%eax /* zero extend */
|
||||
cmpq %rax,RIP+8(%rsp)
|
||||
je bstep_iret
|
||||
|
@ -1420,7 +1375,15 @@ error_kernelspace:
|
|||
bstep_iret:
|
||||
/* Fix truncated RIP */
|
||||
movq %rcx,RIP+8(%rsp)
|
||||
jmp error_swapgs
|
||||
/* fall through */
|
||||
|
||||
error_bad_iret:
|
||||
SWAPGS
|
||||
mov %rsp,%rdi
|
||||
call fixup_bad_iret
|
||||
mov %rax,%rsp
|
||||
decl %ebx /* Return to usergs */
|
||||
jmp error_sti
|
||||
CFI_ENDPROC
|
||||
END(error_entry)
|
||||
|
||||
|
|
|
@ -1484,7 +1484,7 @@ unsigned long syscall_trace_enter_phase1(struct pt_regs *regs, u32 arch)
|
|||
*/
|
||||
if (work & _TIF_NOHZ) {
|
||||
user_exit();
|
||||
work &= ~TIF_NOHZ;
|
||||
work &= ~_TIF_NOHZ;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SECCOMP
|
||||
|
|
|
@ -233,32 +233,40 @@ DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op)
|
|||
DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun)
|
||||
DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS)
|
||||
DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present)
|
||||
#ifdef CONFIG_X86_32
|
||||
DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment)
|
||||
#endif
|
||||
DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check)
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
/* Runs on IST stack */
|
||||
dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
enum ctx_state prev_state;
|
||||
|
||||
prev_state = exception_enter();
|
||||
if (notify_die(DIE_TRAP, "stack segment", regs, error_code,
|
||||
X86_TRAP_SS, SIGBUS) != NOTIFY_STOP) {
|
||||
preempt_conditional_sti(regs);
|
||||
do_trap(X86_TRAP_SS, SIGBUS, "stack segment", regs, error_code, NULL);
|
||||
preempt_conditional_cli(regs);
|
||||
}
|
||||
exception_exit(prev_state);
|
||||
}
|
||||
|
||||
dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
static const char str[] = "double fault";
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
#ifdef CONFIG_X86_ESPFIX64
|
||||
extern unsigned char native_irq_return_iret[];
|
||||
|
||||
/*
|
||||
* If IRET takes a non-IST fault on the espfix64 stack, then we
|
||||
* end up promoting it to a doublefault. In that case, modify
|
||||
* the stack to make it look like we just entered the #GP
|
||||
* handler from user space, similar to bad_iret.
|
||||
*/
|
||||
if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY &&
|
||||
regs->cs == __KERNEL_CS &&
|
||||
regs->ip == (unsigned long)native_irq_return_iret)
|
||||
{
|
||||
struct pt_regs *normal_regs = task_pt_regs(current);
|
||||
|
||||
/* Fake a #GP(0) from userspace. */
|
||||
memmove(&normal_regs->ip, (void *)regs->sp, 5*8);
|
||||
normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */
|
||||
regs->ip = (unsigned long)general_protection;
|
||||
regs->sp = (unsigned long)&normal_regs->orig_ax;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
exception_enter();
|
||||
/* Return not checked because double check cannot be ignored */
|
||||
notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
|
||||
|
@ -399,6 +407,35 @@ asmlinkage __visible struct pt_regs *sync_regs(struct pt_regs *eregs)
|
|||
return regs;
|
||||
}
|
||||
NOKPROBE_SYMBOL(sync_regs);
|
||||
|
||||
struct bad_iret_stack {
|
||||
void *error_entry_ret;
|
||||
struct pt_regs regs;
|
||||
};
|
||||
|
||||
asmlinkage __visible
|
||||
struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
|
||||
{
|
||||
/*
|
||||
* This is called from entry_64.S early in handling a fault
|
||||
* caused by a bad iret to user mode. To handle the fault
|
||||
* correctly, we want move our stack frame to task_pt_regs
|
||||
* and we want to pretend that the exception came from the
|
||||
* iret target.
|
||||
*/
|
||||
struct bad_iret_stack *new_stack =
|
||||
container_of(task_pt_regs(current),
|
||||
struct bad_iret_stack, regs);
|
||||
|
||||
/* Copy the IRET target to the new stack. */
|
||||
memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
|
||||
|
||||
/* Copy the remainder of the stack from the current stack. */
|
||||
memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
|
||||
|
||||
BUG_ON(!user_mode_vm(&new_stack->regs));
|
||||
return new_stack;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -778,7 +815,7 @@ void __init trap_init(void)
|
|||
set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun);
|
||||
set_intr_gate(X86_TRAP_TS, invalid_TSS);
|
||||
set_intr_gate(X86_TRAP_NP, segment_not_present);
|
||||
set_intr_gate_ist(X86_TRAP_SS, &stack_segment, STACKFAULT_STACK);
|
||||
set_intr_gate(X86_TRAP_SS, stack_segment);
|
||||
set_intr_gate(X86_TRAP_GP, general_protection);
|
||||
set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug);
|
||||
set_intr_gate(X86_TRAP_MF, coprocessor_error);
|
||||
|
|
|
@ -1123,7 +1123,7 @@ void mark_rodata_ro(void)
|
|||
unsigned long end = (unsigned long) &__end_rodata_hpage_align;
|
||||
unsigned long text_end = PFN_ALIGN(&__stop___ex_table);
|
||||
unsigned long rodata_end = PFN_ALIGN(&__end_rodata);
|
||||
unsigned long all_end = PFN_ALIGN(&_end);
|
||||
unsigned long all_end;
|
||||
|
||||
printk(KERN_INFO "Write protecting the kernel read-only data: %luk\n",
|
||||
(end - start) >> 10);
|
||||
|
@ -1134,7 +1134,16 @@ void mark_rodata_ro(void)
|
|||
/*
|
||||
* The rodata/data/bss/brk section (but not the kernel text!)
|
||||
* should also be not-executable.
|
||||
*
|
||||
* We align all_end to PMD_SIZE because the existing mapping
|
||||
* is a full PMD. If we would align _brk_end to PAGE_SIZE we
|
||||
* split the PMD and the reminder between _brk_end and the end
|
||||
* of the PMD will remain mapped executable.
|
||||
*
|
||||
* Any PMD which was setup after the one which covers _brk_end
|
||||
* has been zapped already via cleanup_highmem().
|
||||
*/
|
||||
all_end = roundup((unsigned long)_brk_end, PMD_SIZE);
|
||||
set_memory_nx(rodata_start, (all_end - rodata_start) >> PAGE_SHIFT);
|
||||
|
||||
rodata_test();
|
||||
|
|
|
@ -19,7 +19,16 @@ while (<>) {
|
|||
if ($file_offset == 0) {
|
||||
$file_offset = $offset;
|
||||
} elsif ($file_offset != $offset) {
|
||||
die ".bss and .brk lack common file offset\n";
|
||||
# BFD linker shows the same file offset in ELF.
|
||||
# Gold linker shows them as consecutive.
|
||||
next if ($file_offset + $mem_size == $offset + $size);
|
||||
|
||||
printf STDERR "file_offset: 0x%lx\n", $file_offset;
|
||||
printf STDERR "mem_size: 0x%lx\n", $mem_size;
|
||||
printf STDERR "offset: 0x%lx\n", $offset;
|
||||
printf STDERR "size: 0x%lx\n", $size;
|
||||
|
||||
die ".bss and .brk are non-contiguous\n";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -878,7 +878,7 @@ int acpi_dev_suspend_late(struct device *dev)
|
|||
return 0;
|
||||
|
||||
target_state = acpi_target_system_state();
|
||||
wakeup = device_may_wakeup(dev);
|
||||
wakeup = device_may_wakeup(dev) && acpi_device_can_wakeup(adev);
|
||||
error = acpi_device_wakeup(adev, target_state, wakeup);
|
||||
if (wakeup && error)
|
||||
return error;
|
||||
|
|
|
@ -182,6 +182,12 @@ static void __init sun4i_timer_init(struct device_node *node)
|
|||
/* Make sure timer is stopped before playing with interrupts */
|
||||
sun4i_clkevt_time_stop(0);
|
||||
|
||||
sun4i_clockevent.cpumask = cpu_possible_mask;
|
||||
sun4i_clockevent.irq = irq;
|
||||
|
||||
clockevents_config_and_register(&sun4i_clockevent, rate,
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
ret = setup_irq(irq, &sun4i_timer_irq);
|
||||
if (ret)
|
||||
pr_warn("failed to setup irq %d\n", irq);
|
||||
|
@ -189,12 +195,6 @@ static void __init sun4i_timer_init(struct device_node *node)
|
|||
/* Enable timer0 interrupt */
|
||||
val = readl(timer_base + TIMER_IRQ_EN_REG);
|
||||
writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
|
||||
|
||||
sun4i_clockevent.cpumask = cpu_possible_mask;
|
||||
sun4i_clockevent.irq = irq;
|
||||
|
||||
clockevents_config_and_register(&sun4i_clockevent, rate,
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
|
||||
sun4i_timer_init);
|
||||
|
|
|
@ -271,7 +271,7 @@ struct pl330_config {
|
|||
#define DMAC_MODE_NS (1 << 0)
|
||||
unsigned int mode;
|
||||
unsigned int data_bus_width:10; /* In number of bits */
|
||||
unsigned int data_buf_dep:10;
|
||||
unsigned int data_buf_dep:11;
|
||||
unsigned int num_chan:4;
|
||||
unsigned int num_peri:6;
|
||||
u32 peri_ns;
|
||||
|
@ -2336,7 +2336,7 @@ static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
|
|||
int burst_len;
|
||||
|
||||
burst_len = pl330->pcfg.data_bus_width / 8;
|
||||
burst_len *= pl330->pcfg.data_buf_dep;
|
||||
burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
|
||||
burst_len >>= desc->rqcfg.brst_size;
|
||||
|
||||
/* src/dst_burst_len can't be more than 16 */
|
||||
|
@ -2459,16 +2459,25 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
|
|||
/* Select max possible burst size */
|
||||
burst = pl330->pcfg.data_bus_width / 8;
|
||||
|
||||
while (burst > 1) {
|
||||
if (!(len % burst))
|
||||
break;
|
||||
/*
|
||||
* Make sure we use a burst size that aligns with all the memcpy
|
||||
* parameters because our DMA programming algorithm doesn't cope with
|
||||
* transfers which straddle an entry in the DMA device's MFIFO.
|
||||
*/
|
||||
while ((src | dst | len) & (burst - 1))
|
||||
burst /= 2;
|
||||
}
|
||||
|
||||
desc->rqcfg.brst_size = 0;
|
||||
while (burst != (1 << desc->rqcfg.brst_size))
|
||||
desc->rqcfg.brst_size++;
|
||||
|
||||
/*
|
||||
* If burst size is smaller than bus width then make sure we only
|
||||
* transfer one at a time to avoid a burst stradling an MFIFO entry.
|
||||
*/
|
||||
if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
|
||||
desc->rqcfg.brst_len = 1;
|
||||
|
||||
desc->rqcfg.brst_len = get_burst_len(desc, len);
|
||||
|
||||
desc->txd.flags = flags;
|
||||
|
@ -2732,7 +2741,7 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
|
|||
|
||||
|
||||
dev_info(&adev->dev,
|
||||
"Loaded driver for PL330 DMAC-%d\n", adev->periphid);
|
||||
"Loaded driver for PL330 DMAC-%x\n", adev->periphid);
|
||||
dev_info(&adev->dev,
|
||||
"\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
|
||||
pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
|
||||
|
|
|
@ -230,30 +230,25 @@ static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
|
|||
readl(pchan->base + DMA_CHAN_CUR_PARA));
|
||||
}
|
||||
|
||||
static inline int convert_burst(u32 maxburst, u8 *burst)
|
||||
static inline s8 convert_burst(u32 maxburst)
|
||||
{
|
||||
switch (maxburst) {
|
||||
case 1:
|
||||
*burst = 0;
|
||||
break;
|
||||
return 0;
|
||||
case 8:
|
||||
*burst = 2;
|
||||
break;
|
||||
return 2;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int convert_buswidth(enum dma_slave_buswidth addr_width, u8 *width)
|
||||
static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
|
||||
{
|
||||
if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
|
||||
(addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
|
||||
return -EINVAL;
|
||||
|
||||
*width = addr_width >> 1;
|
||||
return 0;
|
||||
return addr_width >> 1;
|
||||
}
|
||||
|
||||
static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
|
||||
|
@ -284,26 +279,25 @@ static inline int sun6i_dma_cfg_lli(struct sun6i_dma_lli *lli,
|
|||
struct dma_slave_config *config)
|
||||
{
|
||||
u8 src_width, dst_width, src_burst, dst_burst;
|
||||
int ret;
|
||||
|
||||
if (!config)
|
||||
return -EINVAL;
|
||||
|
||||
ret = convert_burst(config->src_maxburst, &src_burst);
|
||||
if (ret)
|
||||
return ret;
|
||||
src_burst = convert_burst(config->src_maxburst);
|
||||
if (src_burst)
|
||||
return src_burst;
|
||||
|
||||
ret = convert_burst(config->dst_maxburst, &dst_burst);
|
||||
if (ret)
|
||||
return ret;
|
||||
dst_burst = convert_burst(config->dst_maxburst);
|
||||
if (dst_burst)
|
||||
return dst_burst;
|
||||
|
||||
ret = convert_buswidth(config->src_addr_width, &src_width);
|
||||
if (ret)
|
||||
return ret;
|
||||
src_width = convert_buswidth(config->src_addr_width);
|
||||
if (src_width)
|
||||
return src_width;
|
||||
|
||||
ret = convert_buswidth(config->dst_addr_width, &dst_width);
|
||||
if (ret)
|
||||
return ret;
|
||||
dst_width = convert_buswidth(config->dst_addr_width);
|
||||
if (dst_width)
|
||||
return dst_width;
|
||||
|
||||
lli->cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
|
||||
DMA_CHAN_CFG_SRC_WIDTH(src_width) |
|
||||
|
@ -542,11 +536,10 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
|
|||
{
|
||||
struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
|
||||
struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
|
||||
struct dma_slave_config *sconfig = &vchan->cfg;
|
||||
struct sun6i_dma_lli *v_lli;
|
||||
struct sun6i_desc *txd;
|
||||
dma_addr_t p_lli;
|
||||
int ret;
|
||||
s8 burst, width;
|
||||
|
||||
dev_dbg(chan2dev(chan),
|
||||
"%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
|
||||
|
@ -565,14 +558,21 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
|
|||
goto err_txd_free;
|
||||
}
|
||||
|
||||
ret = sun6i_dma_cfg_lli(v_lli, src, dest, len, sconfig);
|
||||
if (ret)
|
||||
goto err_dma_free;
|
||||
v_lli->src = src;
|
||||
v_lli->dst = dest;
|
||||
v_lli->len = len;
|
||||
v_lli->para = NORMAL_WAIT;
|
||||
|
||||
burst = convert_burst(8);
|
||||
width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
|
||||
DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
|
||||
DMA_CHAN_CFG_DST_LINEAR_MODE |
|
||||
DMA_CHAN_CFG_SRC_LINEAR_MODE;
|
||||
DMA_CHAN_CFG_SRC_LINEAR_MODE |
|
||||
DMA_CHAN_CFG_SRC_BURST(burst) |
|
||||
DMA_CHAN_CFG_SRC_WIDTH(width) |
|
||||
DMA_CHAN_CFG_DST_BURST(burst) |
|
||||
DMA_CHAN_CFG_DST_WIDTH(width);
|
||||
|
||||
sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
|
||||
|
||||
|
@ -580,8 +580,6 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
|
|||
|
||||
return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
|
||||
|
||||
err_dma_free:
|
||||
dma_pool_free(sdev->pool, v_lli, p_lli);
|
||||
err_txd_free:
|
||||
kfree(txd);
|
||||
return NULL;
|
||||
|
@ -915,6 +913,7 @@ static int sun6i_dma_probe(struct platform_device *pdev)
|
|||
sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy;
|
||||
sdc->slave.device_control = sun6i_dma_control;
|
||||
sdc->slave.chancnt = NR_MAX_VCHANS;
|
||||
sdc->slave.copy_align = 4;
|
||||
|
||||
sdc->slave.dev = &pdev->dev;
|
||||
|
||||
|
|
|
@ -1670,17 +1670,19 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
|
|||
goto out_regs;
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
ret = i915_kick_out_vgacon(dev_priv);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to remove conflicting VGA console\n");
|
||||
goto out_gtt;
|
||||
}
|
||||
|
||||
/* WARNING: Apparently we must kick fbdev drivers before vgacon,
|
||||
* otherwise the vga fbdev driver falls over. */
|
||||
ret = i915_kick_out_firmware_fb(dev_priv);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
|
||||
goto out_gtt;
|
||||
}
|
||||
|
||||
ret = i915_kick_out_vgacon(dev_priv);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to remove conflicting VGA console\n");
|
||||
goto out_gtt;
|
||||
}
|
||||
}
|
||||
|
||||
pci_set_master(dev->pdev);
|
||||
|
|
|
@ -5469,11 +5469,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
|
|||
I915_WRITE(_3D_CHICKEN,
|
||||
_MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
|
||||
|
||||
/* WaSetupGtModeTdRowDispatch:snb */
|
||||
if (IS_SNB_GT1(dev))
|
||||
I915_WRITE(GEN6_GT_MODE,
|
||||
_MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
|
||||
|
||||
/* WaDisable_RenderCache_OperationalFlush:snb */
|
||||
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
||||
|
||||
|
|
|
@ -1256,7 +1256,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
|
|||
(mode_info->atom_context->bios + data_offset +
|
||||
le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
|
||||
rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
|
||||
ppt->usMaximumPowerDeliveryLimit;
|
||||
le16_to_cpu(ppt->usMaximumPowerDeliveryLimit);
|
||||
pt = &ppt->power_tune_table;
|
||||
} else {
|
||||
ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
|
||||
|
|
|
@ -179,6 +179,9 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
|
|||
(rdev->pdev->subsystem_vendor == 0x1734) &&
|
||||
(rdev->pdev->subsystem_device == 0x1107))
|
||||
use_bl = false;
|
||||
/* disable native backlight control on older asics */
|
||||
else if (rdev->family < CHIP_R600)
|
||||
use_bl = false;
|
||||
else
|
||||
use_bl = true;
|
||||
}
|
||||
|
|
|
@ -115,9 +115,12 @@ isert_conn_setup_qp(struct isert_conn *isert_conn, struct rdma_cm_id *cma_id,
|
|||
attr.cap.max_recv_wr = ISERT_QP_MAX_RECV_DTOS;
|
||||
/*
|
||||
* FIXME: Use devattr.max_sge - 2 for max_send_sge as
|
||||
* work-around for RDMA_READ..
|
||||
* work-around for RDMA_READs with ConnectX-2.
|
||||
*
|
||||
* Also, still make sure to have at least two SGEs for
|
||||
* outgoing control PDU responses.
|
||||
*/
|
||||
attr.cap.max_send_sge = device->dev_attr.max_sge - 2;
|
||||
attr.cap.max_send_sge = max(2, device->dev_attr.max_sge - 2);
|
||||
isert_conn->max_sge = attr.cap.max_send_sge;
|
||||
|
||||
attr.cap.max_recv_sge = 1;
|
||||
|
@ -225,12 +228,16 @@ isert_create_device_ib_res(struct isert_device *device)
|
|||
struct isert_cq_desc *cq_desc;
|
||||
struct ib_device_attr *dev_attr;
|
||||
int ret = 0, i, j;
|
||||
int max_rx_cqe, max_tx_cqe;
|
||||
|
||||
dev_attr = &device->dev_attr;
|
||||
ret = isert_query_device(ib_dev, dev_attr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
max_rx_cqe = min(ISER_MAX_RX_CQ_LEN, dev_attr->max_cqe);
|
||||
max_tx_cqe = min(ISER_MAX_TX_CQ_LEN, dev_attr->max_cqe);
|
||||
|
||||
/* asign function handlers */
|
||||
if (dev_attr->device_cap_flags & IB_DEVICE_MEM_MGT_EXTENSIONS &&
|
||||
dev_attr->device_cap_flags & IB_DEVICE_SIGNATURE_HANDOVER) {
|
||||
|
@ -272,7 +279,7 @@ isert_create_device_ib_res(struct isert_device *device)
|
|||
isert_cq_rx_callback,
|
||||
isert_cq_event_callback,
|
||||
(void *)&cq_desc[i],
|
||||
ISER_MAX_RX_CQ_LEN, i);
|
||||
max_rx_cqe, i);
|
||||
if (IS_ERR(device->dev_rx_cq[i])) {
|
||||
ret = PTR_ERR(device->dev_rx_cq[i]);
|
||||
device->dev_rx_cq[i] = NULL;
|
||||
|
@ -284,7 +291,7 @@ isert_create_device_ib_res(struct isert_device *device)
|
|||
isert_cq_tx_callback,
|
||||
isert_cq_event_callback,
|
||||
(void *)&cq_desc[i],
|
||||
ISER_MAX_TX_CQ_LEN, i);
|
||||
max_tx_cqe, i);
|
||||
if (IS_ERR(device->dev_tx_cq[i])) {
|
||||
ret = PTR_ERR(device->dev_tx_cq[i]);
|
||||
device->dev_tx_cq[i] = NULL;
|
||||
|
@ -803,14 +810,25 @@ wake_up:
|
|||
complete(&isert_conn->conn_wait);
|
||||
}
|
||||
|
||||
static void
|
||||
static int
|
||||
isert_disconnected_handler(struct rdma_cm_id *cma_id, bool disconnect)
|
||||
{
|
||||
struct isert_conn *isert_conn = (struct isert_conn *)cma_id->context;
|
||||
struct isert_conn *isert_conn;
|
||||
|
||||
if (!cma_id->qp) {
|
||||
struct isert_np *isert_np = cma_id->context;
|
||||
|
||||
isert_np->np_cm_id = NULL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
isert_conn = (struct isert_conn *)cma_id->context;
|
||||
|
||||
isert_conn->disconnect = disconnect;
|
||||
INIT_WORK(&isert_conn->conn_logout_work, isert_disconnect_work);
|
||||
schedule_work(&isert_conn->conn_logout_work);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
|
@ -825,6 +843,9 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
|
|||
switch (event->event) {
|
||||
case RDMA_CM_EVENT_CONNECT_REQUEST:
|
||||
ret = isert_connect_request(cma_id, event);
|
||||
if (ret)
|
||||
pr_err("isert_cma_handler failed RDMA_CM_EVENT: 0x%08x %d\n",
|
||||
event->event, ret);
|
||||
break;
|
||||
case RDMA_CM_EVENT_ESTABLISHED:
|
||||
isert_connected_handler(cma_id);
|
||||
|
@ -834,7 +855,7 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
|
|||
case RDMA_CM_EVENT_DEVICE_REMOVAL: /* FALLTHRU */
|
||||
disconnect = true;
|
||||
case RDMA_CM_EVENT_TIMEWAIT_EXIT: /* FALLTHRU */
|
||||
isert_disconnected_handler(cma_id, disconnect);
|
||||
ret = isert_disconnected_handler(cma_id, disconnect);
|
||||
break;
|
||||
case RDMA_CM_EVENT_CONNECT_ERROR:
|
||||
default:
|
||||
|
@ -842,12 +863,6 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
|
|||
break;
|
||||
}
|
||||
|
||||
if (ret != 0) {
|
||||
pr_err("isert_cma_handler failed RDMA_CM_EVENT: 0x%08x %d\n",
|
||||
event->event, ret);
|
||||
dump_stack();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -3190,7 +3205,8 @@ isert_free_np(struct iscsi_np *np)
|
|||
{
|
||||
struct isert_np *isert_np = (struct isert_np *)np->np_context;
|
||||
|
||||
rdma_destroy_id(isert_np->np_cm_id);
|
||||
if (isert_np->np_cm_id)
|
||||
rdma_destroy_id(isert_np->np_cm_id);
|
||||
|
||||
np->np_context = NULL;
|
||||
kfree(isert_np);
|
||||
|
|
|
@ -2092,6 +2092,7 @@ static int srpt_create_ch_ib(struct srpt_rdma_ch *ch)
|
|||
if (!qp_init)
|
||||
goto out;
|
||||
|
||||
retry:
|
||||
ch->cq = ib_create_cq(sdev->device, srpt_completion, NULL, ch,
|
||||
ch->rq_size + srp_sq_size, 0);
|
||||
if (IS_ERR(ch->cq)) {
|
||||
|
@ -2115,6 +2116,13 @@ static int srpt_create_ch_ib(struct srpt_rdma_ch *ch)
|
|||
ch->qp = ib_create_qp(sdev->pd, qp_init);
|
||||
if (IS_ERR(ch->qp)) {
|
||||
ret = PTR_ERR(ch->qp);
|
||||
if (ret == -ENOMEM) {
|
||||
srp_sq_size /= 2;
|
||||
if (srp_sq_size >= MIN_SRPT_SQ_SIZE) {
|
||||
ib_destroy_cq(ch->cq);
|
||||
goto retry;
|
||||
}
|
||||
}
|
||||
printk(KERN_ERR "failed to create_qp ret= %d\n", ret);
|
||||
goto err_destroy_cq;
|
||||
}
|
||||
|
|
|
@ -2471,7 +2471,8 @@ static void bond_loadbalance_arp_mon(struct work_struct *work)
|
|||
bond_slave_state_change(bond);
|
||||
if (BOND_MODE(bond) == BOND_MODE_XOR)
|
||||
bond_update_slave_arr(bond, NULL);
|
||||
} else if (do_failover) {
|
||||
}
|
||||
if (do_failover) {
|
||||
block_netpoll_tx();
|
||||
bond_select_active_slave(bond);
|
||||
unblock_netpoll_tx();
|
||||
|
|
|
@ -110,7 +110,7 @@ static int can_calc_bittiming(struct net_device *dev, struct can_bittiming *bt,
|
|||
long rate;
|
||||
u64 v64;
|
||||
|
||||
/* Use CIA recommended sample points */
|
||||
/* Use CiA recommended sample points */
|
||||
if (bt->sample_point) {
|
||||
sampl_pt = bt->sample_point;
|
||||
} else {
|
||||
|
@ -382,7 +382,7 @@ void can_free_echo_skb(struct net_device *dev, unsigned int idx)
|
|||
BUG_ON(idx >= priv->echo_skb_max);
|
||||
|
||||
if (priv->echo_skb[idx]) {
|
||||
kfree_skb(priv->echo_skb[idx]);
|
||||
dev_kfree_skb_any(priv->echo_skb[idx]);
|
||||
priv->echo_skb[idx] = NULL;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,4 +1,5 @@
|
|||
config CAN_M_CAN
|
||||
depends on HAS_IOMEM
|
||||
tristate "Bosch M_CAN devices"
|
||||
---help---
|
||||
Say Y here if you want to support for Bosch M_CAN controller.
|
||||
|
|
|
@ -105,14 +105,36 @@ enum m_can_mram_cfg {
|
|||
MRAM_CFG_NUM,
|
||||
};
|
||||
|
||||
/* Fast Bit Timing & Prescaler Register (FBTP) */
|
||||
#define FBTR_FBRP_MASK 0x1f
|
||||
#define FBTR_FBRP_SHIFT 16
|
||||
#define FBTR_FTSEG1_SHIFT 8
|
||||
#define FBTR_FTSEG1_MASK (0xf << FBTR_FTSEG1_SHIFT)
|
||||
#define FBTR_FTSEG2_SHIFT 4
|
||||
#define FBTR_FTSEG2_MASK (0x7 << FBTR_FTSEG2_SHIFT)
|
||||
#define FBTR_FSJW_SHIFT 0
|
||||
#define FBTR_FSJW_MASK 0x3
|
||||
|
||||
/* Test Register (TEST) */
|
||||
#define TEST_LBCK BIT(4)
|
||||
|
||||
/* CC Control Register(CCCR) */
|
||||
#define CCCR_TEST BIT(7)
|
||||
#define CCCR_MON BIT(5)
|
||||
#define CCCR_CCE BIT(1)
|
||||
#define CCCR_INIT BIT(0)
|
||||
#define CCCR_TEST BIT(7)
|
||||
#define CCCR_CMR_MASK 0x3
|
||||
#define CCCR_CMR_SHIFT 10
|
||||
#define CCCR_CMR_CANFD 0x1
|
||||
#define CCCR_CMR_CANFD_BRS 0x2
|
||||
#define CCCR_CMR_CAN 0x3
|
||||
#define CCCR_CME_MASK 0x3
|
||||
#define CCCR_CME_SHIFT 8
|
||||
#define CCCR_CME_CAN 0
|
||||
#define CCCR_CME_CANFD 0x1
|
||||
#define CCCR_CME_CANFD_BRS 0x2
|
||||
#define CCCR_TEST BIT(7)
|
||||
#define CCCR_MON BIT(5)
|
||||
#define CCCR_CCE BIT(1)
|
||||
#define CCCR_INIT BIT(0)
|
||||
#define CCCR_CANFD 0x10
|
||||
|
||||
/* Bit Timing & Prescaler Register (BTP) */
|
||||
#define BTR_BRP_MASK 0x3ff
|
||||
|
@ -204,6 +226,7 @@ enum m_can_mram_cfg {
|
|||
|
||||
/* Rx Buffer / FIFO Element Size Configuration (RXESC) */
|
||||
#define M_CAN_RXESC_8BYTES 0x0
|
||||
#define M_CAN_RXESC_64BYTES 0x777
|
||||
|
||||
/* Tx Buffer Configuration(TXBC) */
|
||||
#define TXBC_NDTB_OFF 16
|
||||
|
@ -211,6 +234,7 @@ enum m_can_mram_cfg {
|
|||
|
||||
/* Tx Buffer Element Size Configuration(TXESC) */
|
||||
#define TXESC_TBDS_8BYTES 0x0
|
||||
#define TXESC_TBDS_64BYTES 0x7
|
||||
|
||||
/* Tx Event FIFO Con.guration (TXEFC) */
|
||||
#define TXEFC_EFS_OFF 16
|
||||
|
@ -219,11 +243,11 @@ enum m_can_mram_cfg {
|
|||
/* Message RAM Configuration (in bytes) */
|
||||
#define SIDF_ELEMENT_SIZE 4
|
||||
#define XIDF_ELEMENT_SIZE 8
|
||||
#define RXF0_ELEMENT_SIZE 16
|
||||
#define RXF1_ELEMENT_SIZE 16
|
||||
#define RXF0_ELEMENT_SIZE 72
|
||||
#define RXF1_ELEMENT_SIZE 72
|
||||
#define RXB_ELEMENT_SIZE 16
|
||||
#define TXE_ELEMENT_SIZE 8
|
||||
#define TXB_ELEMENT_SIZE 16
|
||||
#define TXB_ELEMENT_SIZE 72
|
||||
|
||||
/* Message RAM Elements */
|
||||
#define M_CAN_FIFO_ID 0x0
|
||||
|
@ -231,11 +255,17 @@ enum m_can_mram_cfg {
|
|||
#define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
|
||||
|
||||
/* Rx Buffer Element */
|
||||
/* R0 */
|
||||
#define RX_BUF_ESI BIT(31)
|
||||
#define RX_BUF_XTD BIT(30)
|
||||
#define RX_BUF_RTR BIT(29)
|
||||
/* R1 */
|
||||
#define RX_BUF_ANMF BIT(31)
|
||||
#define RX_BUF_EDL BIT(21)
|
||||
#define RX_BUF_BRS BIT(20)
|
||||
|
||||
/* Tx Buffer Element */
|
||||
/* R0 */
|
||||
#define TX_BUF_XTD BIT(30)
|
||||
#define TX_BUF_RTR BIT(29)
|
||||
|
||||
|
@ -296,6 +326,7 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv,
|
|||
if (enable) {
|
||||
/* enable m_can configuration */
|
||||
m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
|
||||
udelay(5);
|
||||
/* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
|
||||
m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
|
||||
} else {
|
||||
|
@ -326,41 +357,67 @@ static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
|
|||
m_can_write(priv, M_CAN_ILE, 0x0);
|
||||
}
|
||||
|
||||
static void m_can_read_fifo(const struct net_device *dev, struct can_frame *cf,
|
||||
u32 rxfs)
|
||||
static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
|
||||
{
|
||||
struct net_device_stats *stats = &dev->stats;
|
||||
struct m_can_priv *priv = netdev_priv(dev);
|
||||
u32 id, fgi;
|
||||
struct canfd_frame *cf;
|
||||
struct sk_buff *skb;
|
||||
u32 id, fgi, dlc;
|
||||
int i;
|
||||
|
||||
/* calculate the fifo get index for where to read data */
|
||||
fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
|
||||
dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
|
||||
if (dlc & RX_BUF_EDL)
|
||||
skb = alloc_canfd_skb(dev, &cf);
|
||||
else
|
||||
skb = alloc_can_skb(dev, (struct can_frame **)&cf);
|
||||
if (!skb) {
|
||||
stats->rx_dropped++;
|
||||
return;
|
||||
}
|
||||
|
||||
if (dlc & RX_BUF_EDL)
|
||||
cf->len = can_dlc2len((dlc >> 16) & 0x0F);
|
||||
else
|
||||
cf->len = get_can_dlc((dlc >> 16) & 0x0F);
|
||||
|
||||
id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
|
||||
if (id & RX_BUF_XTD)
|
||||
cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
|
||||
else
|
||||
cf->can_id = (id >> 18) & CAN_SFF_MASK;
|
||||
|
||||
if (id & RX_BUF_RTR) {
|
||||
if (id & RX_BUF_ESI) {
|
||||
cf->flags |= CANFD_ESI;
|
||||
netdev_dbg(dev, "ESI Error\n");
|
||||
}
|
||||
|
||||
if (!(dlc & RX_BUF_EDL) && (id & RX_BUF_RTR)) {
|
||||
cf->can_id |= CAN_RTR_FLAG;
|
||||
} else {
|
||||
id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
|
||||
cf->can_dlc = get_can_dlc((id >> 16) & 0x0F);
|
||||
*(u32 *)(cf->data + 0) = m_can_fifo_read(priv, fgi,
|
||||
M_CAN_FIFO_DATA(0));
|
||||
*(u32 *)(cf->data + 4) = m_can_fifo_read(priv, fgi,
|
||||
M_CAN_FIFO_DATA(1));
|
||||
if (dlc & RX_BUF_BRS)
|
||||
cf->flags |= CANFD_BRS;
|
||||
|
||||
for (i = 0; i < cf->len; i += 4)
|
||||
*(u32 *)(cf->data + i) =
|
||||
m_can_fifo_read(priv, fgi,
|
||||
M_CAN_FIFO_DATA(i / 4));
|
||||
}
|
||||
|
||||
/* acknowledge rx fifo 0 */
|
||||
m_can_write(priv, M_CAN_RXF0A, fgi);
|
||||
|
||||
stats->rx_packets++;
|
||||
stats->rx_bytes += cf->len;
|
||||
|
||||
netif_receive_skb(skb);
|
||||
}
|
||||
|
||||
static int m_can_do_rx_poll(struct net_device *dev, int quota)
|
||||
{
|
||||
struct m_can_priv *priv = netdev_priv(dev);
|
||||
struct net_device_stats *stats = &dev->stats;
|
||||
struct sk_buff *skb;
|
||||
struct can_frame *frame;
|
||||
u32 pkts = 0;
|
||||
u32 rxfs;
|
||||
|
||||
|
@ -374,18 +431,7 @@ static int m_can_do_rx_poll(struct net_device *dev, int quota)
|
|||
if (rxfs & RXFS_RFL)
|
||||
netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
|
||||
|
||||
skb = alloc_can_skb(dev, &frame);
|
||||
if (!skb) {
|
||||
stats->rx_dropped++;
|
||||
return pkts;
|
||||
}
|
||||
|
||||
m_can_read_fifo(dev, frame, rxfs);
|
||||
|
||||
stats->rx_packets++;
|
||||
stats->rx_bytes += frame->can_dlc;
|
||||
|
||||
netif_receive_skb(skb);
|
||||
m_can_read_fifo(dev, rxfs);
|
||||
|
||||
quota--;
|
||||
pkts++;
|
||||
|
@ -481,11 +527,23 @@ static int m_can_handle_lec_err(struct net_device *dev,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int __m_can_get_berr_counter(const struct net_device *dev,
|
||||
struct can_berr_counter *bec)
|
||||
{
|
||||
struct m_can_priv *priv = netdev_priv(dev);
|
||||
unsigned int ecr;
|
||||
|
||||
ecr = m_can_read(priv, M_CAN_ECR);
|
||||
bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
|
||||
bec->txerr = ecr & ECR_TEC_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int m_can_get_berr_counter(const struct net_device *dev,
|
||||
struct can_berr_counter *bec)
|
||||
{
|
||||
struct m_can_priv *priv = netdev_priv(dev);
|
||||
unsigned int ecr;
|
||||
int err;
|
||||
|
||||
err = clk_prepare_enable(priv->hclk);
|
||||
|
@ -498,9 +556,7 @@ static int m_can_get_berr_counter(const struct net_device *dev,
|
|||
return err;
|
||||
}
|
||||
|
||||
ecr = m_can_read(priv, M_CAN_ECR);
|
||||
bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
|
||||
bec->txerr = ecr & ECR_TEC_MASK;
|
||||
__m_can_get_berr_counter(dev, bec);
|
||||
|
||||
clk_disable_unprepare(priv->cclk);
|
||||
clk_disable_unprepare(priv->hclk);
|
||||
|
@ -544,7 +600,7 @@ static int m_can_handle_state_change(struct net_device *dev,
|
|||
if (unlikely(!skb))
|
||||
return 0;
|
||||
|
||||
m_can_get_berr_counter(dev, &bec);
|
||||
__m_can_get_berr_counter(dev, &bec);
|
||||
|
||||
switch (new_state) {
|
||||
case CAN_STATE_ERROR_ACTIVE:
|
||||
|
@ -596,14 +652,14 @@ static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
|
|||
|
||||
if ((psr & PSR_EP) &&
|
||||
(priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
|
||||
netdev_dbg(dev, "entered error warning state\n");
|
||||
netdev_dbg(dev, "entered error passive state\n");
|
||||
work_done += m_can_handle_state_change(dev,
|
||||
CAN_STATE_ERROR_PASSIVE);
|
||||
}
|
||||
|
||||
if ((psr & PSR_BO) &&
|
||||
(priv->can.state != CAN_STATE_BUS_OFF)) {
|
||||
netdev_dbg(dev, "entered error warning state\n");
|
||||
netdev_dbg(dev, "entered error bus off state\n");
|
||||
work_done += m_can_handle_state_change(dev,
|
||||
CAN_STATE_BUS_OFF);
|
||||
}
|
||||
|
@ -615,7 +671,7 @@ static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
|
|||
{
|
||||
if (irqstatus & IR_WDI)
|
||||
netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
|
||||
if (irqstatus & IR_BEU)
|
||||
if (irqstatus & IR_ELO)
|
||||
netdev_err(dev, "Error Logging Overflow\n");
|
||||
if (irqstatus & IR_BEU)
|
||||
netdev_err(dev, "Bit Error Uncorrected\n");
|
||||
|
@ -733,10 +789,23 @@ static const struct can_bittiming_const m_can_bittiming_const = {
|
|||
.brp_inc = 1,
|
||||
};
|
||||
|
||||
static const struct can_bittiming_const m_can_data_bittiming_const = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
|
||||
.tseg1_max = 16,
|
||||
.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
|
||||
.tseg2_max = 8,
|
||||
.sjw_max = 4,
|
||||
.brp_min = 1,
|
||||
.brp_max = 32,
|
||||
.brp_inc = 1,
|
||||
};
|
||||
|
||||
static int m_can_set_bittiming(struct net_device *dev)
|
||||
{
|
||||
struct m_can_priv *priv = netdev_priv(dev);
|
||||
const struct can_bittiming *bt = &priv->can.bittiming;
|
||||
const struct can_bittiming *dbt = &priv->can.data_bittiming;
|
||||
u16 brp, sjw, tseg1, tseg2;
|
||||
u32 reg_btp;
|
||||
|
||||
|
@ -747,7 +816,17 @@ static int m_can_set_bittiming(struct net_device *dev)
|
|||
reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
|
||||
(tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
|
||||
m_can_write(priv, M_CAN_BTP, reg_btp);
|
||||
netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp);
|
||||
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
brp = dbt->brp - 1;
|
||||
sjw = dbt->sjw - 1;
|
||||
tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
|
||||
tseg2 = dbt->phase_seg2 - 1;
|
||||
reg_btp = (brp << FBTR_FBRP_SHIFT) | (sjw << FBTR_FSJW_SHIFT) |
|
||||
(tseg1 << FBTR_FTSEG1_SHIFT) |
|
||||
(tseg2 << FBTR_FTSEG2_SHIFT);
|
||||
m_can_write(priv, M_CAN_FBTP, reg_btp);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -767,8 +846,8 @@ static void m_can_chip_config(struct net_device *dev)
|
|||
|
||||
m_can_config_endisable(priv, true);
|
||||
|
||||
/* RX Buffer/FIFO Element Size 8 bytes data field */
|
||||
m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES);
|
||||
/* RX Buffer/FIFO Element Size 64 bytes data field */
|
||||
m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
|
||||
|
||||
/* Accept Non-matching Frames Into FIFO 0 */
|
||||
m_can_write(priv, M_CAN_GFC, 0x0);
|
||||
|
@ -777,8 +856,8 @@ static void m_can_chip_config(struct net_device *dev)
|
|||
m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
|
||||
priv->mcfg[MRAM_TXB].off);
|
||||
|
||||
/* only support 8 bytes firstly */
|
||||
m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES);
|
||||
/* support 64 bytes payload */
|
||||
m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
|
||||
|
||||
m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
|
||||
priv->mcfg[MRAM_TXE].off);
|
||||
|
@ -793,7 +872,8 @@ static void m_can_chip_config(struct net_device *dev)
|
|||
RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
|
||||
|
||||
cccr = m_can_read(priv, M_CAN_CCCR);
|
||||
cccr &= ~(CCCR_TEST | CCCR_MON);
|
||||
cccr &= ~(CCCR_TEST | CCCR_MON | (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
|
||||
(CCCR_CME_MASK << CCCR_CME_SHIFT));
|
||||
test = m_can_read(priv, M_CAN_TEST);
|
||||
test &= ~TEST_LBCK;
|
||||
|
||||
|
@ -805,6 +885,9 @@ static void m_can_chip_config(struct net_device *dev)
|
|||
test |= TEST_LBCK;
|
||||
}
|
||||
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
|
||||
cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
|
||||
|
||||
m_can_write(priv, M_CAN_CCCR, cccr);
|
||||
m_can_write(priv, M_CAN_TEST, test);
|
||||
|
||||
|
@ -869,11 +952,13 @@ static struct net_device *alloc_m_can_dev(void)
|
|||
|
||||
priv->dev = dev;
|
||||
priv->can.bittiming_const = &m_can_bittiming_const;
|
||||
priv->can.data_bittiming_const = &m_can_data_bittiming_const;
|
||||
priv->can.do_set_mode = m_can_set_mode;
|
||||
priv->can.do_get_berr_counter = m_can_get_berr_counter;
|
||||
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
|
||||
CAN_CTRLMODE_LISTENONLY |
|
||||
CAN_CTRLMODE_BERR_REPORTING;
|
||||
CAN_CTRLMODE_BERR_REPORTING |
|
||||
CAN_CTRLMODE_FD;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
@ -956,8 +1041,9 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
|
|||
struct net_device *dev)
|
||||
{
|
||||
struct m_can_priv *priv = netdev_priv(dev);
|
||||
struct can_frame *cf = (struct can_frame *)skb->data;
|
||||
u32 id;
|
||||
struct canfd_frame *cf = (struct canfd_frame *)skb->data;
|
||||
u32 id, cccr;
|
||||
int i;
|
||||
|
||||
if (can_dropped_invalid_skb(dev, skb))
|
||||
return NETDEV_TX_OK;
|
||||
|
@ -976,11 +1062,28 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
|
|||
|
||||
/* message ram configuration */
|
||||
m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
|
||||
m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, cf->can_dlc << 16);
|
||||
m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), *(u32 *)(cf->data + 0));
|
||||
m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), *(u32 *)(cf->data + 4));
|
||||
m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
|
||||
|
||||
for (i = 0; i < cf->len; i += 4)
|
||||
m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
|
||||
*(u32 *)(cf->data + i));
|
||||
|
||||
can_put_echo_skb(skb, dev, 0);
|
||||
|
||||
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
cccr = m_can_read(priv, M_CAN_CCCR);
|
||||
cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
|
||||
if (can_is_canfd_skb(skb)) {
|
||||
if (cf->flags & CANFD_BRS)
|
||||
cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
|
||||
else
|
||||
cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
|
||||
} else {
|
||||
cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
|
||||
}
|
||||
m_can_write(priv, M_CAN_CCCR, cccr);
|
||||
}
|
||||
|
||||
/* enable first TX buffer to start transfer */
|
||||
m_can_write(priv, M_CAN_TXBTIE, 0x1);
|
||||
m_can_write(priv, M_CAN_TXBAR, 0x1);
|
||||
|
@ -992,6 +1095,7 @@ static const struct net_device_ops m_can_netdev_ops = {
|
|||
.ndo_open = m_can_open,
|
||||
.ndo_stop = m_can_close,
|
||||
.ndo_start_xmit = m_can_start_xmit,
|
||||
.ndo_change_mtu = can_change_mtu,
|
||||
};
|
||||
|
||||
static int register_m_can_dev(struct net_device *dev)
|
||||
|
@ -1009,7 +1113,7 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
|
|||
struct resource *res;
|
||||
void __iomem *addr;
|
||||
u32 out_val[MRAM_CFG_LEN];
|
||||
int ret;
|
||||
int i, start, end, ret;
|
||||
|
||||
/* message ram could be shared */
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
|
||||
|
@ -1060,6 +1164,15 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
|
|||
priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
|
||||
priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
|
||||
|
||||
/* initialize the entire Message RAM in use to avoid possible
|
||||
* ECC/parity checksum errors when reading an uninitialized buffer
|
||||
*/
|
||||
start = priv->mcfg[MRAM_SIDF].off;
|
||||
end = priv->mcfg[MRAM_TXB].off +
|
||||
priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
|
||||
for (i = start; i < end; i += 4)
|
||||
writel(0x0, priv->mram_base + i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -628,6 +628,7 @@ static const struct net_device_ops rcar_can_netdev_ops = {
|
|||
.ndo_open = rcar_can_open,
|
||||
.ndo_stop = rcar_can_close,
|
||||
.ndo_start_xmit = rcar_can_start_xmit,
|
||||
.ndo_change_mtu = can_change_mtu,
|
||||
};
|
||||
|
||||
static void rcar_can_rx_pkt(struct rcar_can_priv *priv)
|
||||
|
|
|
@ -214,7 +214,7 @@ static int kvaser_pci_add_chan(struct pci_dev *pdev, int channel,
|
|||
struct net_device *dev;
|
||||
struct sja1000_priv *priv;
|
||||
struct kvaser_pci *board;
|
||||
int err, init_step;
|
||||
int err;
|
||||
|
||||
dev = alloc_sja1000dev(sizeof(struct kvaser_pci));
|
||||
if (dev == NULL)
|
||||
|
@ -235,7 +235,6 @@ static int kvaser_pci_add_chan(struct pci_dev *pdev, int channel,
|
|||
if (channel == 0) {
|
||||
board->xilinx_ver =
|
||||
ioread8(board->res_addr + XILINX_VERINT) >> 4;
|
||||
init_step = 2;
|
||||
|
||||
/* Assert PTADR# - we're in passive mode so the other bits are
|
||||
not important */
|
||||
|
@ -264,8 +263,6 @@ static int kvaser_pci_add_chan(struct pci_dev *pdev, int channel,
|
|||
priv->irq_flags = IRQF_SHARED;
|
||||
dev->irq = pdev->irq;
|
||||
|
||||
init_step = 4;
|
||||
|
||||
dev_info(&pdev->dev, "reg_base=%p conf_addr=%p irq=%d\n",
|
||||
priv->reg_base, board->conf_addr, dev->irq);
|
||||
|
||||
|
|
|
@ -434,10 +434,9 @@ static void ems_usb_read_bulk_callback(struct urb *urb)
|
|||
if (urb->actual_length > CPC_HEADER_SIZE) {
|
||||
struct ems_cpc_msg *msg;
|
||||
u8 *ibuf = urb->transfer_buffer;
|
||||
u8 msg_count, again, start;
|
||||
u8 msg_count, start;
|
||||
|
||||
msg_count = ibuf[0] & ~0x80;
|
||||
again = ibuf[0] & 0x80;
|
||||
|
||||
start = CPC_HEADER_SIZE;
|
||||
|
||||
|
|
|
@ -464,7 +464,6 @@ static void esd_usb2_write_bulk_callback(struct urb *urb)
|
|||
{
|
||||
struct esd_tx_urb_context *context = urb->context;
|
||||
struct esd_usb2_net_priv *priv;
|
||||
struct esd_usb2 *dev;
|
||||
struct net_device *netdev;
|
||||
size_t size = sizeof(struct esd_usb2_msg);
|
||||
|
||||
|
@ -472,7 +471,6 @@ static void esd_usb2_write_bulk_callback(struct urb *urb)
|
|||
|
||||
priv = context->priv;
|
||||
netdev = priv->netdev;
|
||||
dev = priv->usb2;
|
||||
|
||||
/* free up our allocated buffer */
|
||||
usb_free_coherent(urb->dev, size,
|
||||
|
@ -1143,6 +1141,7 @@ static void esd_usb2_disconnect(struct usb_interface *intf)
|
|||
}
|
||||
}
|
||||
unlink_all_urbs(dev);
|
||||
kfree(dev);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -718,6 +718,7 @@ static const struct net_device_ops gs_usb_netdev_ops = {
|
|||
.ndo_open = gs_can_open,
|
||||
.ndo_stop = gs_can_close,
|
||||
.ndo_start_xmit = gs_can_start_xmit,
|
||||
.ndo_change_mtu = can_change_mtu,
|
||||
};
|
||||
|
||||
static struct gs_can *gs_make_candev(unsigned int channel, struct usb_interface *intf)
|
||||
|
|
|
@ -300,7 +300,8 @@ static int xcan_set_bittiming(struct net_device *ndev)
|
|||
static int xcan_chip_start(struct net_device *ndev)
|
||||
{
|
||||
struct xcan_priv *priv = netdev_priv(ndev);
|
||||
u32 err, reg_msr, reg_sr_mask;
|
||||
u32 reg_msr, reg_sr_mask;
|
||||
int err;
|
||||
unsigned long timeout;
|
||||
|
||||
/* Check if it is in reset mode */
|
||||
|
@ -961,6 +962,7 @@ static const struct net_device_ops xcan_netdev_ops = {
|
|||
.ndo_open = xcan_open,
|
||||
.ndo_stop = xcan_close,
|
||||
.ndo_start_xmit = xcan_start_xmit,
|
||||
.ndo_change_mtu = can_change_mtu,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -1082,7 +1082,7 @@ static int cxgb4_cee_peer_getpg(struct net_device *dev, struct cee_pg *pg)
|
|||
pgid = be32_to_cpu(pcmd.u.dcb.pgid.pgid);
|
||||
|
||||
for (i = 0; i < CXGB4_MAX_PRIORITY; i++)
|
||||
pg->prio_pg[i] = (pgid >> (i * 4)) & 0xF;
|
||||
pg->prio_pg[7 - i] = (pgid >> (i * 4)) & 0xF;
|
||||
|
||||
INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
|
||||
pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
|
||||
|
|
|
@ -4421,6 +4421,11 @@ static void be_del_vxlan_port(struct net_device *netdev, sa_family_t sa_family,
|
|||
"Disabled VxLAN offloads for UDP port %d\n",
|
||||
be16_to_cpu(port));
|
||||
}
|
||||
|
||||
static bool be_gso_check(struct sk_buff *skb, struct net_device *dev)
|
||||
{
|
||||
return vxlan_gso_check(skb);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct net_device_ops be_netdev_ops = {
|
||||
|
@ -4450,6 +4455,7 @@ static const struct net_device_ops be_netdev_ops = {
|
|||
#ifdef CONFIG_BE2NET_VXLAN
|
||||
.ndo_add_vxlan_port = be_add_vxlan_port,
|
||||
.ndo_del_vxlan_port = be_del_vxlan_port,
|
||||
.ndo_gso_check = be_gso_check,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
@ -1693,7 +1693,7 @@ int mlx4_en_start_port(struct net_device *dev)
|
|||
mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
|
||||
|
||||
#ifdef CONFIG_MLX4_EN_VXLAN
|
||||
if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
|
||||
if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
|
||||
vxlan_get_rx_port(dev);
|
||||
#endif
|
||||
priv->port_up = true;
|
||||
|
@ -2355,6 +2355,11 @@ static void mlx4_en_del_vxlan_port(struct net_device *dev,
|
|||
|
||||
queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
|
||||
}
|
||||
|
||||
static bool mlx4_en_gso_check(struct sk_buff *skb, struct net_device *dev)
|
||||
{
|
||||
return vxlan_gso_check(skb);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct net_device_ops mlx4_netdev_ops = {
|
||||
|
@ -2386,6 +2391,7 @@ static const struct net_device_ops mlx4_netdev_ops = {
|
|||
#ifdef CONFIG_MLX4_EN_VXLAN
|
||||
.ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
|
||||
.ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
|
||||
.ndo_gso_check = mlx4_en_gso_check,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
@ -2416,6 +2422,11 @@ static const struct net_device_ops mlx4_netdev_ops_master = {
|
|||
.ndo_rx_flow_steer = mlx4_en_filter_rfs,
|
||||
#endif
|
||||
.ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
|
||||
#ifdef CONFIG_MLX4_EN_VXLAN
|
||||
.ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
|
||||
.ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
|
||||
.ndo_gso_check = mlx4_en_gso_check,
|
||||
#endif
|
||||
};
|
||||
|
||||
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
|
||||
|
|
|
@ -503,6 +503,11 @@ static void qlcnic_del_vxlan_port(struct net_device *netdev,
|
|||
|
||||
adapter->flags |= QLCNIC_DEL_VXLAN_PORT;
|
||||
}
|
||||
|
||||
static bool qlcnic_gso_check(struct sk_buff *skb, struct net_device *dev)
|
||||
{
|
||||
return vxlan_gso_check(skb);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct net_device_ops qlcnic_netdev_ops = {
|
||||
|
@ -526,6 +531,7 @@ static const struct net_device_ops qlcnic_netdev_ops = {
|
|||
#ifdef CONFIG_QLCNIC_VXLAN
|
||||
.ndo_add_vxlan_port = qlcnic_add_vxlan_port,
|
||||
.ndo_del_vxlan_port = qlcnic_del_vxlan_port,
|
||||
.ndo_gso_check = qlcnic_gso_check,
|
||||
#endif
|
||||
#ifdef CONFIG_NET_POLL_CONTROLLER
|
||||
.ndo_poll_controller = qlcnic_poll_controller,
|
||||
|
|
|
@ -129,9 +129,9 @@ do { \
|
|||
#define CPSW_VLAN_AWARE BIT(1)
|
||||
#define CPSW_ALE_VLAN_AWARE 1
|
||||
|
||||
#define CPSW_FIFO_NORMAL_MODE (0 << 15)
|
||||
#define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
|
||||
#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
|
||||
#define CPSW_FIFO_NORMAL_MODE (0 << 16)
|
||||
#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
|
||||
#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
|
||||
|
||||
#define CPSW_INTPACEEN (0x3f << 16)
|
||||
#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
|
||||
|
|
|
@ -377,17 +377,20 @@ static int ieee802154fake_probe(struct platform_device *pdev)
|
|||
|
||||
err = wpan_phy_register(phy);
|
||||
if (err)
|
||||
goto out;
|
||||
goto err_phy_reg;
|
||||
|
||||
err = register_netdev(dev);
|
||||
if (err < 0)
|
||||
goto out;
|
||||
if (err)
|
||||
goto err_netdev_reg;
|
||||
|
||||
dev_info(&pdev->dev, "Added ieee802154 HardMAC hardware\n");
|
||||
return 0;
|
||||
|
||||
out:
|
||||
unregister_netdev(dev);
|
||||
err_netdev_reg:
|
||||
wpan_phy_unregister(phy);
|
||||
err_phy_reg:
|
||||
free_netdev(dev);
|
||||
wpan_phy_free(phy);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
|
@ -506,7 +506,9 @@ static int pptp_getname(struct socket *sock, struct sockaddr *uaddr,
|
|||
int len = sizeof(struct sockaddr_pppox);
|
||||
struct sockaddr_pppox sp;
|
||||
|
||||
sp.sa_family = AF_PPPOX;
|
||||
memset(&sp.sa_addr, 0, sizeof(sp.sa_addr));
|
||||
|
||||
sp.sa_family = AF_PPPOX;
|
||||
sp.sa_protocol = PX_PROTO_PPTP;
|
||||
sp.sa_addr.pptp = pppox_sk(sock->sk)->proto.pptp.src_addr;
|
||||
|
||||
|
|
Некоторые файлы не были показаны из-за слишком большого количества измененных файлов Показать больше
Загрузка…
Ссылка в новой задаче