dmaengine: Add support for BCM2835
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA. Signed-off-by: Florian Meier <florian.meier@koalo.de> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Florian Meier
Vinod Koul
Родитель
0adcdeed6f
Коммит
96286b5766
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@ -0,0 +1,57 @@
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* BCM2835 DMA controller
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The BCM2835 DMA controller has 16 channels in total.
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Only the lower 13 channels have an associated IRQ.
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Some arbitrary channels are used by the firmware
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(1,3,6,7 in the current firmware version).
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The channels 0,2 and 3 have special functionality
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and should not be used by the driver.
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Required properties:
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- compatible: Should be "brcm,bcm2835-dma".
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain the DMA interrupts associated
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to the DMA channels in ascending order.
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- #dma-cells: Must be <1>, the cell in the dmas property of the
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client device represents the DREQ number.
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- brcm,dma-channel-mask: Bit mask representing the channels
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not used by the firmware in ascending order,
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i.e. first channel corresponds to LSB.
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Example:
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dma: dma@7e007000 {
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compatible = "brcm,bcm2835-dma";
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reg = <0x7e007000 0xf00>;
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interrupts = <1 16>,
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<1 17>,
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<1 18>,
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<1 19>,
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<1 20>,
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<1 21>,
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<1 22>,
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<1 23>,
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<1 24>,
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<1 25>,
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<1 26>,
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<1 27>,
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<1 28>;
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#dma-cells = <1>;
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brcm,dma-channel-mask = <0x7f35>;
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};
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DMA clients connected to the BCM2835 DMA controller must use the format
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described in the dma.txt file, using a two-cell specifier for each channel.
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Example:
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bcm2835_i2s: i2s@7e203000 {
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compatible = "brcm,bcm2835-i2s";
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reg = < 0x7e203000 0x20>,
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< 0x7e101098 0x02>;
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dmas = <&dma 2>,
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<&dma 3>;
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dma-names = "tx", "rx";
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};
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@ -301,6 +301,12 @@ config DMA_OMAP
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config DMA_BCM2835
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tristate "BCM2835 DMA engine support"
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depends on (ARCH_BCM2835 || MACH_BCM2708)
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config TI_CPPI41
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tristate "AM33xx CPPI41 DMA support"
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depends on ARCH_OMAP
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@ -38,6 +38,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
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obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
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obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
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obj-$(CONFIG_TI_CPPI41) += cppi41.o
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@ -0,0 +1,706 @@
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/*
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* BCM2835 DMA engine support
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*
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* This driver only supports cyclic DMA transfers
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* as needed for the I2S module.
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*
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* Author: Florian Meier <florian.meier@koalo.de>
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* Copyright 2013
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*
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* Based on
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* OMAP DMAengine support by Russell King
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*
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* BCM2708 DMA Driver
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* Copyright (C) 2010 Broadcom
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*
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* Raspberry Pi PCM I2S ALSA Driver
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* Copyright (c) by Phil Poole 2013
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*
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* MARVELL MMP Peripheral DMA Driver
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* Copyright 2012 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include "virt-dma.h"
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struct bcm2835_dmadev {
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struct dma_device ddev;
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spinlock_t lock;
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void __iomem *base;
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struct device_dma_parameters dma_parms;
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};
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struct bcm2835_dma_cb {
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uint32_t info;
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uint32_t src;
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uint32_t dst;
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uint32_t length;
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uint32_t stride;
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uint32_t next;
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uint32_t pad[2];
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};
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struct bcm2835_chan {
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struct virt_dma_chan vc;
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struct list_head node;
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struct dma_slave_config cfg;
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bool cyclic;
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unsigned int dreq;
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int ch;
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struct bcm2835_desc *desc;
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void __iomem *chan_base;
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int irq_number;
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};
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struct bcm2835_desc {
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struct virt_dma_desc vd;
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enum dma_transfer_direction dir;
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unsigned int control_block_size;
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struct bcm2835_dma_cb *control_block_base;
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dma_addr_t control_block_base_phys;
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unsigned int frames;
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size_t size;
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};
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#define BCM2835_DMA_CS 0x00
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#define BCM2835_DMA_ADDR 0x04
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#define BCM2835_DMA_SOURCE_AD 0x0c
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#define BCM2835_DMA_DEST_AD 0x10
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#define BCM2835_DMA_NEXTCB 0x1C
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/* DMA CS Control and Status bits */
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#define BCM2835_DMA_ACTIVE BIT(0)
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#define BCM2835_DMA_INT BIT(2)
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#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
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#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
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#define BCM2835_DMA_ERR BIT(8)
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#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
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#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
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#define BCM2835_DMA_INT_EN BIT(0)
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#define BCM2835_DMA_D_INC BIT(4)
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#define BCM2835_DMA_D_DREQ BIT(6)
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#define BCM2835_DMA_S_INC BIT(8)
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#define BCM2835_DMA_S_DREQ BIT(10)
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#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
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#define BCM2835_DMA_DATA_TYPE_S8 1
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#define BCM2835_DMA_DATA_TYPE_S16 2
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#define BCM2835_DMA_DATA_TYPE_S32 4
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#define BCM2835_DMA_DATA_TYPE_S128 16
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#define BCM2835_DMA_BULK_MASK BIT(0)
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#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
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/* Valid only for channels 0 - 14, 15 has its own base address */
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#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
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#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
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static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
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{
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return container_of(d, struct bcm2835_dmadev, ddev);
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}
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static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct bcm2835_chan, vc.chan);
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}
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static inline struct bcm2835_desc *to_bcm2835_dma_desc(
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struct dma_async_tx_descriptor *t)
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{
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return container_of(t, struct bcm2835_desc, vd.tx);
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}
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static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
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{
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struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
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dma_free_coherent(desc->vd.tx.chan->device->dev,
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desc->control_block_size,
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desc->control_block_base,
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desc->control_block_base_phys);
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kfree(desc);
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}
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static int bcm2835_dma_abort(void __iomem *chan_base)
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{
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unsigned long cs;
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long int timeout = 10000;
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cs = readl(chan_base + BCM2835_DMA_CS);
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if (!(cs & BCM2835_DMA_ACTIVE))
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return 0;
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/* Write 0 to the active bit - Pause the DMA */
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writel(0, chan_base + BCM2835_DMA_CS);
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/* Wait for any current AXI transfer to complete */
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while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
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cpu_relax();
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cs = readl(chan_base + BCM2835_DMA_CS);
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}
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/* We'll un-pause when we set of our next DMA */
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if (!timeout)
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return -ETIMEDOUT;
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if (!(cs & BCM2835_DMA_ACTIVE))
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return 0;
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/* Terminate the control block chain */
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writel(0, chan_base + BCM2835_DMA_NEXTCB);
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/* Abort the whole DMA */
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writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
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chan_base + BCM2835_DMA_CS);
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return 0;
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}
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static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
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{
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struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
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struct bcm2835_desc *d;
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if (!vd) {
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c->desc = NULL;
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return;
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}
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list_del(&vd->node);
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c->desc = d = to_bcm2835_dma_desc(&vd->tx);
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writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
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writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
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}
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static irqreturn_t bcm2835_dma_callback(int irq, void *data)
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{
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struct bcm2835_chan *c = data;
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struct bcm2835_desc *d;
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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/* Acknowledge interrupt */
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writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
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d = c->desc;
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if (d) {
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/* TODO Only works for cyclic DMA */
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vchan_cyclic_callback(&d->vd);
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}
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/* Keep the DMA engine running */
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writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
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spin_unlock_irqrestore(&c->vc.lock, flags);
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return IRQ_HANDLED;
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}
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static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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dev_dbg(c->vc.chan.device->dev,
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"Allocating DMA channel %d\n", c->ch);
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return request_irq(c->irq_number,
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bcm2835_dma_callback, 0, "DMA IRQ", c);
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}
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static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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vchan_free_chan_resources(&c->vc);
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free_irq(c->irq_number, c);
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dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
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}
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static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
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{
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return d->size;
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}
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static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
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{
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unsigned int i;
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size_t size;
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for (size = i = 0; i < d->frames; i++) {
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struct bcm2835_dma_cb *control_block =
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&d->control_block_base[i];
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size_t this_size = control_block->length;
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dma_addr_t dma;
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if (d->dir == DMA_DEV_TO_MEM)
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dma = control_block->dst;
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else
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dma = control_block->src;
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if (size)
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size += this_size;
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else if (addr >= dma && addr < dma + this_size)
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size += dma + this_size - addr;
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}
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return size;
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}
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static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *txstate)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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struct virt_dma_desc *vd;
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enum dma_status ret;
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unsigned long flags;
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ret = dma_cookie_status(chan, cookie, txstate);
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if (ret == DMA_COMPLETE || !txstate)
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return ret;
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spin_lock_irqsave(&c->vc.lock, flags);
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vd = vchan_find_desc(&c->vc, cookie);
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if (vd) {
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txstate->residue =
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bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
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} else if (c->desc && c->desc->vd.tx.cookie == cookie) {
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struct bcm2835_desc *d = c->desc;
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dma_addr_t pos;
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if (d->dir == DMA_MEM_TO_DEV)
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pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
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else if (d->dir == DMA_DEV_TO_MEM)
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pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
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else
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pos = 0;
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txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
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} else {
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txstate->residue = 0;
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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return ret;
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}
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static void bcm2835_dma_issue_pending(struct dma_chan *chan)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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unsigned long flags;
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c->cyclic = true; /* Nothing else is implemented */
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spin_lock_irqsave(&c->vc.lock, flags);
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if (vchan_issue_pending(&c->vc) && !c->desc)
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bcm2835_dma_start_desc(c);
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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enum dma_slave_buswidth dev_width;
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struct bcm2835_desc *d;
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dma_addr_t dev_addr;
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unsigned int es, sync_type;
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unsigned int frame;
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/* Grab configuration */
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if (!is_slave_direction(direction)) {
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dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
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return NULL;
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}
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if (direction == DMA_DEV_TO_MEM) {
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dev_addr = c->cfg.src_addr;
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dev_width = c->cfg.src_addr_width;
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sync_type = BCM2835_DMA_S_DREQ;
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} else {
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dev_addr = c->cfg.dst_addr;
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dev_width = c->cfg.dst_addr_width;
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sync_type = BCM2835_DMA_D_DREQ;
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}
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/* Bus width translates to the element size (ES) */
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switch (dev_width) {
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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es = BCM2835_DMA_DATA_TYPE_S32;
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break;
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default:
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return NULL;
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}
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/* Now allocate and setup the descriptor. */
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d = kzalloc(sizeof(*d), GFP_NOWAIT);
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if (!d)
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return NULL;
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d->dir = direction;
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d->frames = buf_len / period_len;
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/* Allocate memory for control blocks */
|
||||
d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
|
||||
d->control_block_base = dma_zalloc_coherent(chan->device->dev,
|
||||
d->control_block_size, &d->control_block_base_phys,
|
||||
GFP_NOWAIT);
|
||||
|
||||
if (!d->control_block_base) {
|
||||
kfree(d);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Iterate over all frames, create a control block
|
||||
* for each frame and link them together.
|
||||
*/
|
||||
for (frame = 0; frame < d->frames; frame++) {
|
||||
struct bcm2835_dma_cb *control_block =
|
||||
&d->control_block_base[frame];
|
||||
|
||||
/* Setup adresses */
|
||||
if (d->dir == DMA_DEV_TO_MEM) {
|
||||
control_block->info = BCM2835_DMA_D_INC;
|
||||
control_block->src = dev_addr;
|
||||
control_block->dst = buf_addr + frame * period_len;
|
||||
} else {
|
||||
control_block->info = BCM2835_DMA_S_INC;
|
||||
control_block->src = buf_addr + frame * period_len;
|
||||
control_block->dst = dev_addr;
|
||||
}
|
||||
|
||||
/* Enable interrupt */
|
||||
control_block->info |= BCM2835_DMA_INT_EN;
|
||||
|
||||
/* Setup synchronization */
|
||||
if (sync_type != 0)
|
||||
control_block->info |= sync_type;
|
||||
|
||||
/* Setup DREQ channel */
|
||||
if (c->dreq != 0)
|
||||
control_block->info |=
|
||||
BCM2835_DMA_PER_MAP(c->dreq);
|
||||
|
||||
/* Length of a frame */
|
||||
control_block->length = period_len;
|
||||
d->size += control_block->length;
|
||||
|
||||
/*
|
||||
* Next block is the next frame.
|
||||
* This DMA engine driver currently only supports cyclic DMA.
|
||||
* Therefore, wrap around at number of frames.
|
||||
*/
|
||||
control_block->next = d->control_block_base_phys +
|
||||
sizeof(struct bcm2835_dma_cb)
|
||||
* ((frame + 1) % d->frames);
|
||||
}
|
||||
|
||||
return vchan_tx_prep(&c->vc, &d->vd, flags);
|
||||
}
|
||||
|
||||
static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
|
||||
struct dma_slave_config *cfg)
|
||||
{
|
||||
if ((cfg->direction == DMA_DEV_TO_MEM &&
|
||||
cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
|
||||
(cfg->direction == DMA_MEM_TO_DEV &&
|
||||
cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
|
||||
!is_slave_direction(cfg->direction)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
c->cfg = *cfg;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
|
||||
{
|
||||
struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
|
||||
unsigned long flags;
|
||||
int timeout = 10000;
|
||||
LIST_HEAD(head);
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
|
||||
/* Prevent this channel being scheduled */
|
||||
spin_lock(&d->lock);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock(&d->lock);
|
||||
|
||||
/*
|
||||
* Stop DMA activity: we assume the callback will not be called
|
||||
* after bcm_dma_abort() returns (even if it does, it will see
|
||||
* c->desc is NULL and exit.)
|
||||
*/
|
||||
if (c->desc) {
|
||||
c->desc = NULL;
|
||||
bcm2835_dma_abort(c->chan_base);
|
||||
|
||||
/* Wait for stopping */
|
||||
while (--timeout) {
|
||||
if (!(readl(c->chan_base + BCM2835_DMA_CS) &
|
||||
BCM2835_DMA_ACTIVE))
|
||||
break;
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
if (!timeout)
|
||||
dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
|
||||
}
|
||||
|
||||
vchan_get_all_descriptors(&c->vc, &head);
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
vchan_dma_desc_free_list(&c->vc, &head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_SLAVE_CONFIG:
|
||||
return bcm2835_dma_slave_config(c,
|
||||
(struct dma_slave_config *)arg);
|
||||
|
||||
case DMA_TERMINATE_ALL:
|
||||
return bcm2835_dma_terminate_all(c);
|
||||
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
}
|
||||
|
||||
static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
|
||||
{
|
||||
struct bcm2835_chan *c;
|
||||
|
||||
c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
|
||||
if (!c)
|
||||
return -ENOMEM;
|
||||
|
||||
c->vc.desc_free = bcm2835_dma_desc_free;
|
||||
vchan_init(&c->vc, &d->ddev);
|
||||
INIT_LIST_HEAD(&c->node);
|
||||
|
||||
d->ddev.chancnt++;
|
||||
|
||||
c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
|
||||
c->ch = chan_id;
|
||||
c->irq_number = irq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bcm2835_dma_free(struct bcm2835_dmadev *od)
|
||||
{
|
||||
struct bcm2835_chan *c, *next;
|
||||
|
||||
list_for_each_entry_safe(c, next, &od->ddev.channels,
|
||||
vc.chan.device_node) {
|
||||
list_del(&c->vc.chan.device_node);
|
||||
tasklet_kill(&c->vc.task);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm2835_dma_of_match[] = {
|
||||
{ .compatible = "brcm,bcm2835-dma", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
|
||||
|
||||
static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct bcm2835_dmadev *d = ofdma->of_dma_data;
|
||||
struct dma_chan *chan;
|
||||
|
||||
chan = dma_get_any_slave_channel(&d->ddev);
|
||||
if (!chan)
|
||||
return NULL;
|
||||
|
||||
/* Set DREQ from param */
|
||||
to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
|
||||
|
||||
return chan;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
|
||||
struct dma_slave_caps *caps)
|
||||
{
|
||||
caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
caps->cmd_pause = false;
|
||||
caps->cmd_terminate = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_dmadev *od;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int rc;
|
||||
int i;
|
||||
int irq;
|
||||
uint32_t chans_available;
|
||||
|
||||
if (!pdev->dev.dma_mask)
|
||||
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
||||
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
|
||||
if (!od)
|
||||
return -ENOMEM;
|
||||
|
||||
pdev->dev.dma_parms = &od->dma_parms;
|
||||
dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
od->base = base;
|
||||
|
||||
dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
|
||||
od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
|
||||
od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
|
||||
od->ddev.device_tx_status = bcm2835_dma_tx_status;
|
||||
od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
|
||||
od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
|
||||
od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
|
||||
od->ddev.device_control = bcm2835_dma_control;
|
||||
od->ddev.dev = &pdev->dev;
|
||||
INIT_LIST_HEAD(&od->ddev.channels);
|
||||
spin_lock_init(&od->lock);
|
||||
|
||||
platform_set_drvdata(pdev, od);
|
||||
|
||||
/* Request DMA channel mask from device tree */
|
||||
if (of_property_read_u32(pdev->dev.of_node,
|
||||
"brcm,dma-channel-mask",
|
||||
&chans_available)) {
|
||||
dev_err(&pdev->dev, "Failed to get channel mask\n");
|
||||
rc = -EINVAL;
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do not use the FIQ and BULK channels,
|
||||
* because they are used by the GPU.
|
||||
*/
|
||||
chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
|
||||
|
||||
for (i = 0; i < pdev->num_resources; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
if (irq < 0)
|
||||
break;
|
||||
|
||||
if (chans_available & (1 << i)) {
|
||||
rc = bcm2835_dma_chan_init(od, i, irq);
|
||||
if (rc)
|
||||
goto err_no_dma;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
|
||||
|
||||
/* Device-tree DMA controller registration */
|
||||
rc = of_dma_controller_register(pdev->dev.of_node,
|
||||
bcm2835_dma_xlate, od);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "Failed to register DMA controller\n");
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
rc = dma_async_device_register(&od->ddev);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to register slave DMA engine device: %d\n", rc);
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_no_dma:
|
||||
bcm2835_dma_free(od);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bcm2835_dma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
|
||||
|
||||
dma_async_device_unregister(&od->ddev);
|
||||
bcm2835_dma_free(od);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver bcm2835_dma_driver = {
|
||||
.probe = bcm2835_dma_probe,
|
||||
.remove = bcm2835_dma_remove,
|
||||
.driver = {
|
||||
.name = "bcm2835-dma",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(bcm2835_dma_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(bcm2835_dma_driver);
|
||||
|
||||
MODULE_ALIAS("platform:bcm2835-dma");
|
||||
MODULE_DESCRIPTION("BCM2835 DMA engine driver");
|
||||
MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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