x86, amd-nb: Cleanup AMD northbridge caching code
Support more than just the "Misc Control" part of the northbridges. Support more flags by turning "gart_supported" into a single bit flag that is stored in a flags member. Clean up related code by using a set of functions (amd_nb_num(), amd_nb_has_feature() and node_to_amd_nb()) instead of accessing the NB data structures directly. Reorder the initialization code and put the GART flush words caching in a separate function. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Hans Rosenfeld
Borislav Petkov
Родитель
eec1d4fa00
Коммит
9653a5c76c
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@ -3,36 +3,52 @@
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#include <linux/pci.h>
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extern struct pci_device_id amd_nb_ids[];
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extern struct pci_device_id amd_nb_misc_ids[];
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struct bootnode;
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extern int early_is_amd_nb(u32 value);
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extern int cache_amd_northbridges(void);
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extern int amd_cache_northbridges(void);
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extern void amd_flush_garts(void);
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extern int amd_get_nodes(struct bootnode *nodes);
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extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn);
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extern int amd_scan_nodes(void);
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struct amd_northbridge {
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struct pci_dev *misc;
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};
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struct amd_northbridge_info {
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u16 num;
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u8 gart_supported;
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struct pci_dev **nb_misc;
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u64 flags;
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struct amd_northbridge *nb;
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};
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extern struct amd_northbridge_info amd_northbridges;
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#define AMD_NB_GART 0x1
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#ifdef CONFIG_AMD_NB
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static inline struct pci_dev *node_to_amd_nb_misc(int node)
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static inline int amd_nb_num(void)
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{
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return (node < amd_northbridges.num) ? amd_northbridges.nb_misc[node] : NULL;
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return amd_northbridges.num;
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}
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static inline int amd_nb_has_feature(int feature)
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{
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return ((amd_northbridges.flags & feature) == feature);
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}
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static inline struct amd_northbridge *node_to_amd_nb(int node)
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{
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return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
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}
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#else
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static inline struct pci_dev *node_to_amd_nb_misc(int node)
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{
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return NULL;
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}
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#define amd_nb_num(x) 0
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#define amd_nb_has_feature(x) false
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#define node_to_amd_nb(x) NULL
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#endif
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@ -12,74 +12,65 @@
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static u32 *flush_words;
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struct pci_device_id amd_nb_ids[] = {
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struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
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{}
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};
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EXPORT_SYMBOL(amd_nb_ids);
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EXPORT_SYMBOL(amd_nb_misc_ids);
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struct amd_northbridge_info amd_northbridges;
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EXPORT_SYMBOL(amd_northbridges);
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static struct pci_dev *next_amd_northbridge(struct pci_dev *dev)
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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struct pci_device_id *ids)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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} while (!pci_match_id(&amd_nb_ids[0], dev));
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} while (!pci_match_id(ids, dev));
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return dev;
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}
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int cache_amd_northbridges(void)
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int amd_cache_northbridges(void)
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{
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int i;
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struct pci_dev *dev;
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int i = 0;
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struct amd_northbridge *nb;
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struct pci_dev *misc;
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if (amd_northbridges.num)
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if (amd_nb_num())
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return 0;
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dev = NULL;
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while ((dev = next_amd_northbridge(dev)) != NULL)
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amd_northbridges.num++;
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misc = NULL;
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while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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i++;
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if (i == 0)
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return 0;
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nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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return -ENOMEM;
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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misc = NULL;
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for (i = 0; i != amd_nb_num(); i++) {
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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}
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/* some CPU families (e.g. family 0x11) do not support GART */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
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boot_cpu_data.x86 == 0x15)
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amd_northbridges.gart_supported = 1;
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amd_northbridges.flags |= AMD_NB_GART;
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amd_northbridges.nb_misc = kmalloc((amd_northbridges.num + 1) *
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sizeof(void *), GFP_KERNEL);
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if (!amd_northbridges.nb_misc)
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return -ENOMEM;
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if (!amd_northbridges.num) {
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amd_northbridges.nb_misc[0] = NULL;
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return 0;
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}
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if (amd_northbridges.gart_supported) {
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flush_words = kmalloc(amd_northbridges.num * sizeof(u32),
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GFP_KERNEL);
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if (!flush_words) {
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kfree(amd_northbridges.nb_misc);
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return -ENOMEM;
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}
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}
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dev = NULL;
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i = 0;
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while ((dev = next_amd_northbridge(dev)) != NULL) {
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amd_northbridges.nb_misc[i] = dev;
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if (amd_northbridges.gart_supported)
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pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
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}
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amd_northbridges.nb_misc[i] = NULL;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cache_amd_northbridges);
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EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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/* Ignores subdevice/subvendor but as far as I can figure out
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they're useless anyways */
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@ -88,19 +79,39 @@ int __init early_is_amd_nb(u32 device)
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struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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device >>= 16;
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for (id = amd_nb_ids; id->vendor; id++)
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for (id = amd_nb_misc_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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return 1;
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return 0;
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}
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int amd_cache_gart(void)
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{
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int i;
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if (!amd_nb_has_feature(AMD_NB_GART))
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return 0;
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flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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amd_northbridges.flags &= ~AMD_NB_GART;
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return -ENOMEM;
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}
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for (i = 0; i != amd_nb_num(); i++)
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pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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&flush_words[i]);
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return 0;
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}
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void amd_flush_garts(void)
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{
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int flushed, i;
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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if (!amd_northbridges.gart_supported)
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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/* Avoid races between AGP and IOMMU. In theory it's not needed
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@ -109,16 +120,16 @@ void amd_flush_garts(void)
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that it doesn't matter to serialize more. -AK */
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
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for (i = 0; i < amd_northbridges.num; i++) {
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pci_write_config_dword(amd_northbridges.nb_misc[i], 0x9c,
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flush_words[i]|1);
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for (i = 0; i < amd_nb_num(); i++) {
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pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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flush_words[i] | 1);
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flushed++;
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}
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for (i = 0; i < amd_northbridges.num; i++) {
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for (i = 0; i < amd_nb_num(); i++) {
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
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pci_read_config_dword(amd_northbridges.nb_misc[i],
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pci_read_config_dword(node_to_amd_nb(i)->misc,
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0x9c, &w);
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if (!(w & 1))
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break;
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@ -135,11 +146,15 @@ static __init int init_amd_nbs(void)
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{
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int err = 0;
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err = cache_amd_northbridges();
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err = amd_cache_northbridges();
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if (err < 0)
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printk(KERN_NOTICE "AMD NB: Cannot enumerate AMD northbridges.\n");
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if (amd_cache_gart() < 0)
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printk(KERN_NOTICE "AMD NB: Cannot initialize GART flush words, "
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"GART support disabled.\n");
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return err;
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}
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@ -333,7 +333,7 @@ static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
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static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
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{
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struct amd_l3_cache *l3;
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struct pci_dev *dev = node_to_amd_nb_misc(node);
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struct pci_dev *dev = node_to_amd_nb(node)->misc;
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l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
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if (!l3) {
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@ -370,7 +370,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
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return;
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/* not in virtualized environments */
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if (amd_northbridges.num == 0)
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if (amd_nb_num() == 0)
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return;
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/*
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@ -378,7 +378,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
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* never freed but this is done only on shutdown so it doesn't matter.
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*/
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if (!l3_caches) {
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int size = amd_northbridges.num * sizeof(struct amd_l3_cache *);
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int size = amd_nb_num() * sizeof(struct amd_l3_cache *);
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l3_caches = kzalloc(size, GFP_ATOMIC);
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if (!l3_caches)
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@ -561,11 +561,11 @@ static void enable_gart_translations(void)
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{
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int i;
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if (!amd_northbridges.gart_supported)
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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for (i = 0; i < amd_northbridges.num; i++) {
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struct pci_dev *dev = amd_northbridges.nb_misc[i];
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for (i = 0; i < amd_nb_num(); i++) {
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struct pci_dev *dev = node_to_amd_nb(i)->misc;
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enable_gart_translation(dev, __pa(agp_gatt_table));
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}
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@ -596,13 +596,13 @@ static void gart_fixup_northbridges(struct sys_device *dev)
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if (!fix_up_north_bridges)
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return;
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if (!amd_northbridges.gart_supported)
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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pr_info("PCI-DMA: Restoring GART aperture settings\n");
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for (i = 0; i < amd_northbridges.num; i++) {
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struct pci_dev *dev = amd_northbridges.nb_misc[i];
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for (i = 0; i < amd_nb_num(); i++) {
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struct pci_dev *dev = node_to_amd_nb(i)->misc;
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/*
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* Don't enable translations just yet. That is the next
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@ -656,8 +656,8 @@ static __init int init_amd_gatt(struct agp_kern_info *info)
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aper_size = aper_base = info->aper_size = 0;
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dev = NULL;
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for (i = 0; i < amd_northbridges.num; i++) {
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dev = amd_northbridges.nb_misc[i];
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for (i = 0; i < amd_nb_num(); i++) {
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dev = node_to_amd_nb(i)->misc;
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new_aper_base = read_aperture(dev, &new_aper_size);
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if (!new_aper_base)
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goto nommu;
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@ -725,13 +725,13 @@ static void gart_iommu_shutdown(void)
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if (!no_agp)
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return;
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if (!amd_northbridges.gart_supported)
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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for (i = 0; i < amd_northbridges.num; i++) {
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for (i = 0; i < amd_nb_num(); i++) {
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u32 ctl;
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dev = amd_northbridges.nb_misc[i];
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dev = node_to_amd_nb(i)->misc;
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
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ctl &= ~GARTEN;
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@ -749,7 +749,7 @@ int __init gart_iommu_init(void)
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unsigned long scratch;
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long i;
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if (!amd_northbridges.gart_supported)
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if (!amd_nb_has_feature(AMD_NB_GART))
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return 0;
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#ifndef CONFIG_AGP_AMD64
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@ -124,7 +124,7 @@ static int amd64_fetch_size(void)
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u32 temp;
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struct aper_size_info_32 *values;
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dev = amd_northbridges.nb_misc[0];
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dev = node_to_amd_nb(0)->misc;
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if (dev==NULL)
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return 0;
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@ -181,14 +181,13 @@ static int amd_8151_configure(void)
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unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
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int i;
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if (!amd_northbridges.gart_supported)
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if (!amd_nb_has_feature(AMD_NB_GART))
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return 0;
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/* Configure AGP regs in each x86-64 host bridge. */
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for (i = 0; i < amd_northbridges.num; i++) {
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for (i = 0; i < amd_nb_num(); i++) {
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agp_bridge->gart_bus_addr =
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amd64_configure(amd_northbridges.nb_misc[i],
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gatt_bus);
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amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
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}
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amd_flush_garts();
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return 0;
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@ -200,11 +199,11 @@ static void amd64_cleanup(void)
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u32 tmp;
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int i;
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if (!amd_northbridges.gart_supported)
|
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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for (i = 0; i < amd_northbridges.num; i++) {
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struct pci_dev *dev = amd_northbridges.nb_misc[i];
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for (i = 0; i < amd_nb_num(); i++) {
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struct pci_dev *dev = node_to_amd_nb(i)->misc;
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/* disable gart translation */
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
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tmp &= ~GARTEN;
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@ -331,15 +330,15 @@ static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
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{
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int i;
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|
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if (cache_amd_northbridges() < 0)
|
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if (amd_cache_northbridges() < 0)
|
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return -ENODEV;
|
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|
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if (!amd_northbridges.gart_supported)
|
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if (!amd_nb_has_feature(AMD_NB_GART))
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return -ENODEV;
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|
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i = 0;
|
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for (i = 0; i < amd_northbridges.num; i++) {
|
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struct pci_dev *dev = amd_northbridges.nb_misc[i];
|
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for (i = 0; i < amd_nb_num(); i++) {
|
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struct pci_dev *dev = node_to_amd_nb(i)->misc;
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if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
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dev_err(&dev->dev, "no usable aperture found\n");
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#ifdef __x86_64__
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@ -416,7 +415,7 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
|
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}
|
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/* shadow x86-64 registers into ULi registers */
|
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pci_read_config_dword (amd_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
|
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pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
|
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&httfea);
|
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|
||||
/* if x86-64 aperture base is beyond 4G, exit here */
|
||||
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|
@ -484,7 +483,7 @@ static int nforce3_agp_init(struct pci_dev *pdev)
|
|||
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
|
||||
|
||||
/* shadow x86-64 registers into NVIDIA registers */
|
||||
pci_read_config_dword (amd_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
|
||||
pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
|
||||
&apbase);
|
||||
|
||||
/* if x86-64 aperture base is beyond 4G, exit here */
|
||||
|
|
@ -778,7 +777,7 @@ int __init agp_amd64_init(void)
|
|||
}
|
||||
|
||||
/* First check that we have at least one AMD64 NB */
|
||||
if (!pci_dev_present(amd_nb_ids))
|
||||
if (!pci_dev_present(amd_nb_misc_ids))
|
||||
return -ENODEV;
|
||||
|
||||
/* Look for any AGP bridge */
|
||||
|
|
|
|||
|
|
@ -2917,7 +2917,7 @@ static int __init amd64_edac_init(void)
|
|||
|
||||
opstate_init();
|
||||
|
||||
if (cache_amd_northbridges() < 0)
|
||||
if (amd_cache_northbridges() < 0)
|
||||
goto err_ret;
|
||||
|
||||
msrs = msrs_alloc();
|
||||
|
|
@ -2934,7 +2934,7 @@ static int __init amd64_edac_init(void)
|
|||
* to finish initialization of the MC instances.
|
||||
*/
|
||||
err = -ENODEV;
|
||||
for (nb = 0; nb < amd_northbridges.num; nb++) {
|
||||
for (nb = 0; nb < amd_nb_num(); nb++) {
|
||||
if (!pvt_lookup[nb])
|
||||
continue;
|
||||
|
||||
|
|
|
|||
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