blackfin: bf60x: add clock support
Add clock support for bf60x. Signed-off-by: Steven Miao <realmz6@gmail.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
This commit is contained in:
Steven Miao
Bob Liu
Родитель
b5affb0147
Коммит
969003152a
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@ -0,0 +1,14 @@
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#ifndef __ASM_CLKDEV__H_
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#define __ASM_CLKDEV__H_
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#include <linux/slab.h>
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static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
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{
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return kzalloc(size, GFP_KERNEL);
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}
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#define __clk_put(clk)
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#define __clk_get(clk) ({ 1; })
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#endif
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@ -48,4 +48,27 @@
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# define CONFIG_VCO_MULT 0
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#endif
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#include <linux/clk.h>
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struct clk_ops {
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unsigned long (*get_rate)(struct clk *clk);
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unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
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int (*set_rate)(struct clk *clk, unsigned long rate);
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int (*enable)(struct clk *clk);
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int (*disable)(struct clk *clk);
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};
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struct clk {
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struct clk *parent;
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const char *name;
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unsigned long rate;
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spinlock_t lock;
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u32 flags;
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const struct clk_ops *ops;
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void __iomem *reg;
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u32 mask;
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u32 shift;
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};
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int clk_init(void);
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#endif
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@ -0,0 +1,390 @@
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <linux/seq_file.h>
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#include <linux/clkdev.h>
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#include <asm/clocks.h>
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#define CGU0_CTL_DF (1 << 0)
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#define CGU0_CTL_MSEL_SHIFT 8
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#define CGU0_CTL_MSEL_MASK (0x7f << 8)
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#define CGU0_STAT_PLLEN (1 << 0)
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#define CGU0_STAT_PLLBP (1 << 1)
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#define CGU0_STAT_PLLLK (1 << 2)
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#define CGU0_STAT_CLKSALGN (1 << 3)
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#define CGU0_STAT_CCBF0 (1 << 4)
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#define CGU0_STAT_CCBF1 (1 << 5)
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#define CGU0_STAT_SCBF0 (1 << 6)
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#define CGU0_STAT_SCBF1 (1 << 7)
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#define CGU0_STAT_DCBF (1 << 8)
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#define CGU0_STAT_OCBF (1 << 9)
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#define CGU0_STAT_ADDRERR (1 << 16)
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#define CGU0_STAT_LWERR (1 << 17)
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#define CGU0_STAT_DIVERR (1 << 18)
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#define CGU0_STAT_WDFMSERR (1 << 19)
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#define CGU0_STAT_WDIVERR (1 << 20)
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#define CGU0_STAT_PLOCKERR (1 << 21)
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#define CGU0_DIV_CSEL_SHIFT 0
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#define CGU0_DIV_CSEL_MASK 0x0000001F
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#define CGU0_DIV_S0SEL_SHIFT 5
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#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
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#define CGU0_DIV_SYSSEL_SHIFT 8
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#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
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#define CGU0_DIV_S1SEL_SHIFT 13
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#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
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#define CGU0_DIV_DSEL_SHIFT 16
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#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
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#define CGU0_DIV_OSEL_SHIFT 22
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#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
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#define CLK(_clk, _devname, _conname) \
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{ \
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.clk = &_clk, \
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.dev_id = _devname, \
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.con_id = _conname, \
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}
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#define NEEDS_INITIALIZATION 0x11
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static LIST_HEAD(clk_list);
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static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
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{
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u32 val2;
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val2 = bfin_read32(reg);
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val2 &= ~mask;
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val2 |= val;
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bfin_write32(reg, val2);
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}
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static void clk_reg_set_bits(u32 reg, uint32_t mask)
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{
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u32 val;
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val = bfin_read32(reg);
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val |= mask;
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bfin_write32(reg, val);
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}
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static void clk_reg_clear_bits(u32 reg, uint32_t mask)
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{
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u32 val;
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val = bfin_read32(reg);
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val &= ~mask;
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bfin_write32(reg, val);
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}
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int wait_for_pll_align(void)
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{
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int i = 10000;
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while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
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if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
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printk(KERN_DEBUG "fail to align clk\n");
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return -1;
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}
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return 0;
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}
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int clk_enable(struct clk *clk)
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{
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int ret = -EIO;
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if (clk->ops && clk->ops->enable)
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ret = clk->ops->enable(clk);
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return ret;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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if (clk->ops && clk->ops->disable)
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clk->ops->disable(clk);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long ret = 0;
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if (clk->ops && clk->ops->get_rate)
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ret = clk->ops->get_rate(clk);
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return ret;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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long ret = -EIO;
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if (clk->ops && clk->ops->round_rate)
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ret = clk->ops->round_rate(clk, rate);
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return ret;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = -EIO;
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if (clk->ops && clk->ops->set_rate)
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ret = clk->ops->set_rate(clk, rate);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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unsigned long vco_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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unsigned long pll_get_rate(struct clk *clk)
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{
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u32 df;
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u32 msel;
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u32 ctl = bfin_read32(CGU0_CTL);
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u32 stat = bfin_read32(CGU0_STAT);
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if (stat & CGU0_STAT_PLLBP)
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return 0;
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msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
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df = (ctl & CGU0_CTL_DF);
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clk->parent->rate = clk_get_rate(clk->parent);
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return clk->parent->rate / (df + 1) * msel * 2;
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}
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unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 div;
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div = rate / clk->parent->rate;
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return clk->parent->rate * div;
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}
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int pll_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 msel;
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u32 stat = bfin_read32(CGU0_STAT);
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if (!(stat & CGU0_STAT_PLLEN))
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return -EBUSY;
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if (!(stat & CGU0_STAT_PLLLK))
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return -EBUSY;
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if (wait_for_pll_align())
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return -EBUSY;
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msel = rate / clk->parent->rate / 2;
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clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
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CGU0_CTL_MSEL_MASK);
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clk->rate = rate;
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return 0;
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}
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unsigned long cclk_get_rate(struct clk *clk)
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{
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if (clk->parent)
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return clk->parent->rate;
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else
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return 0;
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}
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unsigned long sys_clk_get_rate(struct clk *clk)
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{
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unsigned long drate;
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u32 msel;
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u32 df;
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u32 ctl = bfin_read32(CGU0_CTL);
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u32 div = bfin_read32(CGU0_DIV);
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div = (div & clk->mask) >> clk->shift;
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msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
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df = (ctl & CGU0_CTL_DF);
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if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
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drate = clk->parent->rate / (df + 1);
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drate *= msel;
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drate /= div;
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return drate;
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} else {
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clk->parent->rate = clk_get_rate(clk->parent);
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return clk->parent->rate / div;
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}
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}
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unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long max_rate;
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unsigned long drate;
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int i;
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u32 msel;
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u32 df;
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u32 ctl = bfin_read32(CGU0_CTL);
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msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
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df = (ctl & CGU0_CTL_DF);
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max_rate = clk->parent->rate / (df + 1) * msel;
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if (rate > max_rate)
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return 0;
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for (i = 1; i < clk->mask; i++) {
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drate = max_rate / i;
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if (rate >= drate)
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return drate;
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}
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return 0;
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}
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int sys_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 div = bfin_read32(CGU0_DIV);
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div = (div & clk->mask) >> clk->shift;
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rate = clk_round_rate(clk, rate);
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if (!rate)
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return -EINVAL;
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div = (clk_get_rate(clk) * div) / rate;
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if (wait_for_pll_align())
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return -EBUSY;
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clk_reg_write_mask(CGU0_DIV, div << clk->shift,
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clk->mask);
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clk->rate = rate;
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return 0;
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}
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static struct clk_ops vco_ops = {
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.get_rate = vco_get_rate,
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};
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static struct clk_ops pll_ops = {
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.get_rate = pll_get_rate,
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.set_rate = pll_set_rate,
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};
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static struct clk_ops cclk_ops = {
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.get_rate = cclk_get_rate,
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};
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static struct clk_ops sys_clk_ops = {
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.get_rate = sys_clk_get_rate,
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.set_rate = sys_clk_set_rate,
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.round_rate = sys_clk_round_rate,
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};
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static struct clk sys_clkin = {
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.name = "SYS_CLKIN",
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.rate = CONFIG_CLKIN_HZ,
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.ops = &vco_ops,
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};
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static struct clk pll_clk = {
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.name = "PLLCLK",
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.rate = 500000000,
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.parent = &sys_clkin,
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.ops = &pll_ops,
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.flags = NEEDS_INITIALIZATION,
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};
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static struct clk cclk = {
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.name = "CCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_CSEL_MASK,
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.shift = CGU0_DIV_CSEL_SHIFT,
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.parent = &sys_clkin,
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.ops = &sys_clk_ops,
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.flags = NEEDS_INITIALIZATION,
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};
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static struct clk cclk0 = {
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.name = "CCLK0",
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.parent = &cclk,
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.ops = &cclk_ops,
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};
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static struct clk cclk1 = {
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.name = "CCLK1",
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.parent = &cclk,
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.ops = &cclk_ops,
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};
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static struct clk sysclk = {
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.name = "SYSCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_SYSSEL_MASK,
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.shift = CGU0_DIV_SYSSEL_SHIFT,
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.parent = &sys_clkin,
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.ops = &sys_clk_ops,
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.flags = NEEDS_INITIALIZATION,
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};
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static struct clk sclk0 = {
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.name = "SCLK0",
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.rate = 500000000,
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.mask = CGU0_DIV_S0SEL_MASK,
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.shift = CGU0_DIV_S0SEL_SHIFT,
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.parent = &sysclk,
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.ops = &sys_clk_ops,
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};
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static struct clk sclk1 = {
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.name = "SCLK1",
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.rate = 500000000,
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.mask = CGU0_DIV_S1SEL_MASK,
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.shift = CGU0_DIV_S1SEL_SHIFT,
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.parent = &sysclk,
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.ops = &sys_clk_ops,
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};
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static struct clk dclk = {
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.name = "DCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_DSEL_MASK,
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.shift = CGU0_DIV_DSEL_SHIFT,
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.parent = &pll_clk,
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.ops = &sys_clk_ops,
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};
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static struct clk oclk = {
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.name = "OCLK",
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.rate = 500000000,
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.mask = CGU0_DIV_OSEL_MASK,
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.shift = CGU0_DIV_OSEL_SHIFT,
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.parent = &pll_clk,
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};
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static struct clk_lookup bf609_clks[] = {
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CLK(sys_clkin, NULL, "SYS_CLKIN"),
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CLK(pll_clk, NULL, "PLLCLK"),
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CLK(cclk, NULL, "CCLK"),
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CLK(cclk0, NULL, "CCLK0"),
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CLK(cclk1, NULL, "CCLK1"),
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CLK(sysclk, NULL, "SYSCLK"),
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CLK(sclk0, NULL, "SCLK0"),
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CLK(sclk1, NULL, "SCLK1"),
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CLK(dclk, NULL, "DCLK"),
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CLK(oclk, NULL, "OCLK"),
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};
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int __init clk_init(void)
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{
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int i;
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struct clk *clkp;
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for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
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clkp = bf609_clks[i].clk;
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if (clkp->flags & NEEDS_INITIALIZATION)
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clk_get_rate(clkp);
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}
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clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
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return 0;
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}
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@ -0,0 +1,27 @@
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#ifndef __MACH_COMMON_CLKDEV_H
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#define __MACH_COMMON_CLKDEV_H
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#include <linux/clk.h>
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struct clk_ops {
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unsigned long (*get_rate)(struct clk *clk);
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unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
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int (*set_rate)(struct clk *clk, unsigned long rate);
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int (*enable)(struct clk *clk);
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int (*disable)(struct clk *clk);
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};
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struct clk {
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const char *name;
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unsigned long rate;
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spinlock_t lock;
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u32 flags;
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const struct clk_ops *ops;
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const struct params *params;
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void __iomem *reg;
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u32 mask;
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u32 shift;
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};
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#endif
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@ -33,6 +33,8 @@ void init_clocks(void)
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* in the middle of reprogramming things, and that'll screw us up.
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* For example, any automatic DMAs left by U-Boot for splash screens.
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*/
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#if 0
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size_t i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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struct dma_register *dma = dma_io_base_addr[i];
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@ -93,4 +95,6 @@ void init_clocks(void)
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#endif
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do_sync();
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bfin_read16(0);
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#endif
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}
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@ -10,6 +10,7 @@
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/fs.h>
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#include <linux/delay.h>
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@ -17,6 +18,7 @@
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#include <asm/time.h>
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#include <asm/dpmc.h>
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/* this is the table of CCLK frequencies, in Hz */
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/* .index is the entry in the auxiliary dpm_state_table[] */
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static struct cpufreq_frequency_table bfin_freq_table[] = {
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||||
|
|
@ -67,12 +69,22 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
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#else
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min_cclk = sclk;
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#endif
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#ifndef CONFIG_BF60x
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csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
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#else
|
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csel = bfin_read32(CGU0_DIV) & 0x1F;
|
||||
#endif
|
||||
|
||||
for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
|
||||
bfin_freq_table[index].frequency = cclk >> index;
|
||||
#ifndef CONFIG_BF60x
|
||||
dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
|
||||
dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
|
||||
#else
|
||||
dpm_state_table[index].csel = csel;
|
||||
dpm_state_table[index].tscale = TIME_SCALE >> index;
|
||||
#endif
|
||||
|
||||
pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
|
||||
bfin_freq_table[index].frequency,
|
||||
|
|
@ -99,6 +111,20 @@ static unsigned int bfin_getfreq_khz(unsigned int cpu)
|
|||
return get_cclk() / 1000;
|
||||
}
|
||||
|
||||
unsigned long cpu_set_cclk(int cpu, unsigned long new)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = clk_get(NULL, "CCLK");
|
||||
if (IS_ERR(clk))
|
||||
return -ENODEV;
|
||||
|
||||
ret = clk_set_rate(clk, new);
|
||||
clk_put(clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_target(struct cpufreq_policy *poli,
|
||||
unsigned int target_freq, unsigned int relation)
|
||||
{
|
||||
|
|
@ -107,6 +133,7 @@ static int bfin_target(struct cpufreq_policy *poli,
|
|||
struct cpufreq_freqs freqs;
|
||||
static unsigned long lpj_ref;
|
||||
static unsigned int lpj_ref_freq;
|
||||
int ret = 0;
|
||||
|
||||
#if defined(CONFIG_CYCLES_CLOCKSOURCE)
|
||||
cycles_t cycles;
|
||||
|
|
@ -134,9 +161,17 @@ static int bfin_target(struct cpufreq_policy *poli,
|
|||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
if (cpu == CPUFREQ_CPU) {
|
||||
flags = hard_local_irq_save();
|
||||
#ifndef CONFIG_BF60x
|
||||
plldiv = (bfin_read_PLL_DIV() & SSEL) |
|
||||
dpm_state_table[index].csel;
|
||||
bfin_write_PLL_DIV(plldiv);
|
||||
#else
|
||||
ret = cpu_set_cclk(cpu, freqs.new * 1000);
|
||||
if (ret != 0) {
|
||||
pr_debug("cpufreq set freq failed %d\n", ret);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
on_each_cpu(bfin_adjust_core_timer, &index, 1);
|
||||
#if defined(CONFIG_CYCLES_CLOCKSOURCE)
|
||||
cycles = get_cycles();
|
||||
|
|
@ -161,7 +196,7 @@ static int bfin_target(struct cpufreq_policy *poli,
|
|||
}
|
||||
|
||||
pr_debug("cpufreq: done\n");
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_verify_speed(struct cpufreq_policy *policy)
|
||||
|
|
@ -169,7 +204,7 @@ static int bfin_verify_speed(struct cpufreq_policy *policy)
|
|||
return cpufreq_frequency_table_verify(policy, bfin_freq_table);
|
||||
}
|
||||
|
||||
static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
|
||||
static int __bfin_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
|
||||
unsigned long cclk, sclk;
|
||||
|
|
|
|||
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