drm/exynos: Add DECON driver
This patch is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. The current version of the driver supports video mode displays. Changelog v2: - Change config name, DRM_EXYNOS_DECON to DRM_EXYNOS7_DECON. Signed-off-by: Akshu Agrawal <akshua@gmail.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Ajay Kumar
Inki Dae
Родитель
936ce5cce6
Коммит
96976c3d9a
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@ -0,0 +1,68 @@
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Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
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DECON (Display and Enhancement Controller) is the Display Controller for the
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Exynos7 series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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Required properties:
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- compatible: value should be "samsung,exynos7-decon";
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- reg: physical base address and length of the DECON registers set.
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- interrupt-parent: should be the phandle of the decon controller's
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parent interrupt controller.
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- interrupts: should contain a list of all DECON IP block interrupts in the
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order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
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format depends on the interrupt controller used.
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- interrupt-names: should contain the interrupt names: "fifo", "vsync",
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"lcd_sys", in the same order as they were listed in the interrupts
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property.
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must contain a "default" entry.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clock-names: list of clock names sorted in the same order as the clocks
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property. Must contain "pclk_decon0", "aclk_decon0",
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"decon0_eclk", "decon0_vclk".
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- i80-if-timings: timing configuration for lcd i80 interface support.
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Optional Properties:
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- samsung,power-domain: a phandle to DECON power domain node.
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- display-timings: timing settings for DECON, as described in document [1].
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Can be used in case timings cannot be provided otherwise
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or to override timings provided by the panel.
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[1]: Documentation/devicetree/bindings/video/display-timing.txt
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Example:
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SoC specific DT entry:
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decon@13930000 {
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compatible = "samsung,exynos7-decon";
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interrupt-parent = <&combiner>;
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reg = <0x13930000 0x1000>;
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interrupt-names = "lcd_sys", "vsync", "fifo";
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interrupts = <0 188 0>, <0 189 0>, <0 190 0>;
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clocks = <&clock_disp PCLK_DECON_INT>,
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<&clock_disp ACLK_DECON_INT>,
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<&clock_disp SCLK_DECON_INT_ECLK>,
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<&clock_disp SCLK_DECON_INT_EXTCLKPLL>;
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clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk",
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"decon0_vclk";
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status = "disabled";
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};
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Board specific DT entry:
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decon@13930000 {
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pinctrl-0 = <&lcd_clk &pwm1_out>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -24,9 +24,16 @@ config DRM_EXYNOS_FIMD
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help
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Choose this option if you want to use Exynos FIMD for DRM.
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config DRM_EXYNOS7_DECON
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bool "Exynos DRM DECON"
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depends on DRM_EXYNOS
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select FB_MODE_HELPERS
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help
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Choose this option if you want to use Exynos DECON for DRM.
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config DRM_EXYNOS_DPI
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bool "EXYNOS DRM parallel output support"
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depends on DRM_EXYNOS_FIMD
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depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
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select DRM_PANEL
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default n
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help
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@ -34,7 +41,7 @@ config DRM_EXYNOS_DPI
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config DRM_EXYNOS_DSI
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bool "EXYNOS DRM MIPI-DSI driver support"
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depends on DRM_EXYNOS_FIMD
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depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
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select DRM_MIPI_DSI
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select DRM_PANEL
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default n
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@ -43,7 +50,7 @@ config DRM_EXYNOS_DSI
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config DRM_EXYNOS_DP
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bool "EXYNOS DRM DP driver support"
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depends on DRM_EXYNOS_FIMD && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS)
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depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS)
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default DRM_EXYNOS
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select DRM_PANEL
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help
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@ -10,6 +10,7 @@ exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \
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exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
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exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o
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@ -0,0 +1,990 @@
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/* drivers/gpu/drm/exynos/exynos7_drm_decon.c
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*
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* Copyright (C) 2014 Samsung Electronics Co.Ltd
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* Authors:
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* Akshu Agarwal <akshua@gmail.com>
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* Ajay Kumar <ajaykumar.rs@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/exynos_drm.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <video/of_display_timing.h>
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#include <video/of_videomode.h>
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#include <video/exynos7_decon.h>
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_drv.h"
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#include "exynos_drm_fbdev.h"
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#include "exynos_drm_iommu.h"
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/*
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* DECON stands for Display and Enhancement controller.
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*/
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#define DECON_DEFAULT_FRAMERATE 60
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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#define WINDOWS_NR 2
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struct decon_win_data {
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unsigned int ovl_x;
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unsigned int ovl_y;
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unsigned int offset_x;
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unsigned int offset_y;
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unsigned int ovl_width;
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unsigned int ovl_height;
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unsigned int fb_width;
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unsigned int fb_height;
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unsigned int bpp;
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unsigned int pixel_format;
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dma_addr_t dma_addr;
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bool enabled;
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bool resume;
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};
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struct decon_context {
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struct device *dev;
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struct drm_device *drm_dev;
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struct exynos_drm_crtc *crtc;
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struct clk *pclk;
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struct clk *aclk;
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struct clk *eclk;
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struct clk *vclk;
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void __iomem *regs;
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struct decon_win_data win_data[WINDOWS_NR];
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unsigned int default_win;
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unsigned long irq_flags;
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bool i80_if;
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bool suspended;
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int pipe;
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wait_queue_head_t wait_vsync_queue;
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atomic_t wait_vsync_event;
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struct exynos_drm_panel_info panel;
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struct exynos_drm_display *display;
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};
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static const struct of_device_id decon_driver_dt_match[] = {
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{.compatible = "samsung,exynos7-decon"},
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{},
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};
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MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
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static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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if (ctx->suspended)
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return;
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atomic_set(&ctx->wait_vsync_event, 1);
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/*
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* wait for DECON to signal VSYNC interrupt or return after
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* timeout which is set to 50ms (refresh rate of 20).
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*/
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if (!wait_event_timeout(ctx->wait_vsync_queue,
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!atomic_read(&ctx->wait_vsync_event),
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HZ/20))
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DRM_DEBUG_KMS("vblank wait timed out.\n");
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}
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static void decon_clear_channel(struct decon_context *ctx)
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{
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int win, ch_enabled = 0;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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/* Check if any channel is enabled. */
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for (win = 0; win < WINDOWS_NR; win++) {
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u32 val = readl(ctx->regs + WINCON(win));
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if (val & WINCONx_ENWIN) {
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val &= ~WINCONx_ENWIN;
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writel(val, ctx->regs + WINCON(win));
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ch_enabled = 1;
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}
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}
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/* Wait for vsync, as disable channel takes effect at next vsync */
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if (ch_enabled) {
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unsigned int state = ctx->suspended;
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ctx->suspended = 0;
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decon_wait_for_vblank(ctx->crtc);
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ctx->suspended = state;
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}
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}
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static int decon_ctx_initialize(struct decon_context *ctx,
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struct drm_device *drm_dev)
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{
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struct exynos_drm_private *priv = drm_dev->dev_private;
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ctx->drm_dev = drm_dev;
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ctx->pipe = priv->pipe++;
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/* attach this sub driver to iommu mapping if supported. */
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if (is_drm_iommu_supported(ctx->drm_dev)) {
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int ret;
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/*
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* If any channel is already active, iommu will throw
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* a PAGE FAULT when enabled. So clear any channel if enabled.
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*/
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decon_clear_channel(ctx);
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ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
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if (ret) {
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DRM_ERROR("drm_iommu_attach failed.\n");
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return ret;
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}
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}
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return 0;
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}
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static void decon_ctx_remove(struct decon_context *ctx)
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{
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/* detach this sub driver from iommu mapping if supported. */
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if (is_drm_iommu_supported(ctx->drm_dev))
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drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
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}
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static u32 decon_calc_clkdiv(struct decon_context *ctx,
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const struct drm_display_mode *mode)
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{
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unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
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u32 clkdiv;
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/* Find the clock divider value that gets us closest to ideal_clk */
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clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
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return (clkdiv < 0x100) ? clkdiv : 0xff;
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}
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static bool decon_mode_fixup(struct exynos_drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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if (adjusted_mode->vrefresh == 0)
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adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE;
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return true;
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}
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static void decon_commit(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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struct drm_display_mode *mode = &crtc->base.mode;
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u32 val, clkdiv;
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if (ctx->suspended)
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return;
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/* nothing to do if we haven't set the mode yet */
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if (mode->htotal == 0 || mode->vtotal == 0)
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return;
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if (!ctx->i80_if) {
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int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
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/* setup vertical timing values. */
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vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
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vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
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vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
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val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
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writel(val, ctx->regs + VIDTCON0);
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val = VIDTCON1_VSPW(vsync_len - 1);
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writel(val, ctx->regs + VIDTCON1);
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/* setup horizontal timing values. */
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hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
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hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
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hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
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/* setup horizontal timing values. */
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val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
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writel(val, ctx->regs + VIDTCON2);
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val = VIDTCON3_HSPW(hsync_len - 1);
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writel(val, ctx->regs + VIDTCON3);
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}
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/* setup horizontal and vertical display size. */
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val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
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VIDTCON4_HOZVAL(mode->hdisplay - 1);
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writel(val, ctx->regs + VIDTCON4);
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writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
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/*
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* fields of register with prefix '_F' would be updated
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* at vsync(same as dma start)
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*/
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val = VIDCON0_ENVID | VIDCON0_ENVID_F;
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writel(val, ctx->regs + VIDCON0);
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clkdiv = decon_calc_clkdiv(ctx, mode);
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if (clkdiv > 1) {
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val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
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writel(val, ctx->regs + VCLKCON1);
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writel(val, ctx->regs + VCLKCON2);
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}
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val = readl(ctx->regs + DECON_UPDATE);
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val |= DECON_UPDATE_STANDALONE_F;
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writel(val, ctx->regs + DECON_UPDATE);
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}
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static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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u32 val;
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if (ctx->suspended)
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return -EPERM;
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if (!test_and_set_bit(0, &ctx->irq_flags)) {
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val = readl(ctx->regs + VIDINTCON0);
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val |= VIDINTCON0_INT_ENABLE;
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if (!ctx->i80_if) {
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val |= VIDINTCON0_INT_FRAME;
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val &= ~VIDINTCON0_FRAMESEL0_MASK;
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val |= VIDINTCON0_FRAMESEL0_VSYNC;
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}
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writel(val, ctx->regs + VIDINTCON0);
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}
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return 0;
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}
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static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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u32 val;
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if (ctx->suspended)
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return;
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if (test_and_clear_bit(0, &ctx->irq_flags)) {
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val = readl(ctx->regs + VIDINTCON0);
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val &= ~VIDINTCON0_INT_ENABLE;
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if (!ctx->i80_if)
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val &= ~VIDINTCON0_INT_FRAME;
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writel(val, ctx->regs + VIDINTCON0);
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}
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}
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static void decon_win_mode_set(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct decon_context *ctx = crtc->ctx;
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struct decon_win_data *win_data;
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int win, padding;
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if (!plane) {
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DRM_ERROR("plane is NULL\n");
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return;
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}
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win = plane->zpos;
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if (win == DEFAULT_ZPOS)
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win = ctx->default_win;
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if (win < 0 || win >= WINDOWS_NR)
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return;
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win_data = &ctx->win_data[win];
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padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width;
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win_data->offset_x = plane->fb_x;
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win_data->offset_y = plane->fb_y;
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win_data->fb_width = plane->fb_width + padding;
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win_data->fb_height = plane->fb_height;
|
||||
win_data->ovl_x = plane->crtc_x;
|
||||
win_data->ovl_y = plane->crtc_y;
|
||||
win_data->ovl_width = plane->crtc_width;
|
||||
win_data->ovl_height = plane->crtc_height;
|
||||
win_data->dma_addr = plane->dma_addr[0];
|
||||
win_data->bpp = plane->bpp;
|
||||
win_data->pixel_format = plane->pixel_format;
|
||||
|
||||
DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
|
||||
win_data->offset_x, win_data->offset_y);
|
||||
DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
|
||||
win_data->ovl_width, win_data->ovl_height);
|
||||
DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
|
||||
DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
|
||||
plane->fb_width, plane->crtc_width);
|
||||
}
|
||||
|
||||
static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win)
|
||||
{
|
||||
struct decon_win_data *win_data = &ctx->win_data[win];
|
||||
unsigned long val;
|
||||
|
||||
val = readl(ctx->regs + WINCON(win));
|
||||
val &= ~WINCONx_BPPMODE_MASK;
|
||||
|
||||
switch (win_data->pixel_format) {
|
||||
case DRM_FORMAT_RGB565:
|
||||
val |= WINCONx_BPPMODE_16BPP_565;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_XRGB8888:
|
||||
val |= WINCONx_BPPMODE_24BPP_xRGB;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_XBGR8888:
|
||||
val |= WINCONx_BPPMODE_24BPP_xBGR;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_RGBX8888:
|
||||
val |= WINCONx_BPPMODE_24BPP_RGBx;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_BGRX8888:
|
||||
val |= WINCONx_BPPMODE_24BPP_BGRx;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_ARGB8888:
|
||||
val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
|
||||
WINCONx_ALPHA_SEL;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_ABGR8888:
|
||||
val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
|
||||
WINCONx_ALPHA_SEL;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_RGBA8888:
|
||||
val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
|
||||
WINCONx_ALPHA_SEL;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
case DRM_FORMAT_BGRA8888:
|
||||
val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
|
||||
WINCONx_ALPHA_SEL;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
|
||||
|
||||
val |= WINCONx_BPPMODE_24BPP_xRGB;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
|
||||
|
||||
/*
|
||||
* In case of exynos, setting dma-burst to 16Word causes permanent
|
||||
* tearing for very small buffers, e.g. cursor buffer. Burst Mode
|
||||
* switching which is based on plane size is not recommended as
|
||||
* plane size varies a lot towards the end of the screen and rapid
|
||||
* movement causes unstable DMA which results into iommu crash/tear.
|
||||
*/
|
||||
|
||||
if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
|
||||
val &= ~WINCONx_BURSTLEN_MASK;
|
||||
val |= WINCONx_BURSTLEN_8WORD;
|
||||
}
|
||||
|
||||
writel(val, ctx->regs + WINCON(win));
|
||||
}
|
||||
|
||||
static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
|
||||
{
|
||||
unsigned int keycon0 = 0, keycon1 = 0;
|
||||
|
||||
keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
|
||||
WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
|
||||
|
||||
keycon1 = WxKEYCON1_COLVAL(0xffffffff);
|
||||
|
||||
writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
|
||||
writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
|
||||
}
|
||||
|
||||
/**
|
||||
* shadow_protect_win() - disable updating values from shadow registers at vsync
|
||||
*
|
||||
* @win: window to protect registers for
|
||||
* @protect: 1 to protect (disable updates)
|
||||
*/
|
||||
static void decon_shadow_protect_win(struct decon_context *ctx,
|
||||
int win, bool protect)
|
||||
{
|
||||
u32 bits, val;
|
||||
|
||||
bits = SHADOWCON_WINx_PROTECT(win);
|
||||
|
||||
val = readl(ctx->regs + SHADOWCON);
|
||||
if (protect)
|
||||
val |= bits;
|
||||
else
|
||||
val &= ~bits;
|
||||
writel(val, ctx->regs + SHADOWCON);
|
||||
}
|
||||
|
||||
static void decon_win_commit(struct exynos_drm_crtc *crtc, int zpos)
|
||||
{
|
||||
struct decon_context *ctx = crtc->ctx;
|
||||
struct drm_display_mode *mode = &crtc->base.mode;
|
||||
struct decon_win_data *win_data;
|
||||
int win = zpos;
|
||||
unsigned long val, alpha;
|
||||
unsigned int last_x;
|
||||
unsigned int last_y;
|
||||
|
||||
if (ctx->suspended)
|
||||
return;
|
||||
|
||||
if (win == DEFAULT_ZPOS)
|
||||
win = ctx->default_win;
|
||||
|
||||
if (win < 0 || win >= WINDOWS_NR)
|
||||
return;
|
||||
|
||||
win_data = &ctx->win_data[win];
|
||||
|
||||
/* If suspended, enable this on resume */
|
||||
if (ctx->suspended) {
|
||||
win_data->resume = true;
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* SHADOWCON/PRTCON register is used for enabling timing.
|
||||
*
|
||||
* for example, once only width value of a register is set,
|
||||
* if the dma is started then decon hardware could malfunction so
|
||||
* with protect window setting, the register fields with prefix '_F'
|
||||
* wouldn't be updated at vsync also but updated once unprotect window
|
||||
* is set.
|
||||
*/
|
||||
|
||||
/* protect windows */
|
||||
decon_shadow_protect_win(ctx, win, true);
|
||||
|
||||
/* buffer start address */
|
||||
val = (unsigned long)win_data->dma_addr;
|
||||
writel(val, ctx->regs + VIDW_BUF_START(win));
|
||||
|
||||
/* buffer size */
|
||||
writel(win_data->fb_width, ctx->regs + VIDW_WHOLE_X(win));
|
||||
writel(win_data->fb_height, ctx->regs + VIDW_WHOLE_Y(win));
|
||||
|
||||
/* offset from the start of the buffer to read */
|
||||
writel(win_data->offset_x, ctx->regs + VIDW_OFFSET_X(win));
|
||||
writel(win_data->offset_y, ctx->regs + VIDW_OFFSET_Y(win));
|
||||
|
||||
DRM_DEBUG_KMS("start addr = 0x%lx\n",
|
||||
(unsigned long)win_data->dma_addr);
|
||||
DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
|
||||
win_data->ovl_width, win_data->ovl_height);
|
||||
|
||||
/*
|
||||
* OSD position.
|
||||
* In case the window layout goes of LCD layout, DECON fails.
|
||||
*/
|
||||
if ((win_data->ovl_x + win_data->ovl_width) > mode->hdisplay)
|
||||
win_data->ovl_x = mode->hdisplay - win_data->ovl_width;
|
||||
if ((win_data->ovl_y + win_data->ovl_height) > mode->vdisplay)
|
||||
win_data->ovl_y = mode->vdisplay - win_data->ovl_height;
|
||||
|
||||
val = VIDOSDxA_TOPLEFT_X(win_data->ovl_x) |
|
||||
VIDOSDxA_TOPLEFT_Y(win_data->ovl_y);
|
||||
writel(val, ctx->regs + VIDOSD_A(win));
|
||||
|
||||
last_x = win_data->ovl_x + win_data->ovl_width;
|
||||
if (last_x)
|
||||
last_x--;
|
||||
last_y = win_data->ovl_y + win_data->ovl_height;
|
||||
if (last_y)
|
||||
last_y--;
|
||||
|
||||
val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
|
||||
|
||||
writel(val, ctx->regs + VIDOSD_B(win));
|
||||
|
||||
DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
|
||||
win_data->ovl_x, win_data->ovl_y, last_x, last_y);
|
||||
|
||||
/* OSD alpha */
|
||||
alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
|
||||
VIDOSDxC_ALPHA0_G_F(0x0) |
|
||||
VIDOSDxC_ALPHA0_B_F(0x0);
|
||||
|
||||
writel(alpha, ctx->regs + VIDOSD_C(win));
|
||||
|
||||
alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
|
||||
VIDOSDxD_ALPHA1_G_F(0xff) |
|
||||
VIDOSDxD_ALPHA1_B_F(0xff);
|
||||
|
||||
writel(alpha, ctx->regs + VIDOSD_D(win));
|
||||
|
||||
decon_win_set_pixfmt(ctx, win);
|
||||
|
||||
/* hardware window 0 doesn't support color key. */
|
||||
if (win != 0)
|
||||
decon_win_set_colkey(ctx, win);
|
||||
|
||||
/* wincon */
|
||||
val = readl(ctx->regs + WINCON(win));
|
||||
val |= WINCONx_TRIPLE_BUF_MODE;
|
||||
val |= WINCONx_ENWIN;
|
||||
writel(val, ctx->regs + WINCON(win));
|
||||
|
||||
/* Enable DMA channel and unprotect windows */
|
||||
decon_shadow_protect_win(ctx, win, false);
|
||||
|
||||
val = readl(ctx->regs + DECON_UPDATE);
|
||||
val |= DECON_UPDATE_STANDALONE_F;
|
||||
writel(val, ctx->regs + DECON_UPDATE);
|
||||
|
||||
win_data->enabled = true;
|
||||
}
|
||||
|
||||
static void decon_win_disable(struct exynos_drm_crtc *crtc, int zpos)
|
||||
{
|
||||
struct decon_context *ctx = crtc->ctx;
|
||||
struct decon_win_data *win_data;
|
||||
int win = zpos;
|
||||
u32 val;
|
||||
|
||||
if (win == DEFAULT_ZPOS)
|
||||
win = ctx->default_win;
|
||||
|
||||
if (win < 0 || win >= WINDOWS_NR)
|
||||
return;
|
||||
|
||||
win_data = &ctx->win_data[win];
|
||||
|
||||
if (ctx->suspended) {
|
||||
/* do not resume this window*/
|
||||
win_data->resume = false;
|
||||
return;
|
||||
}
|
||||
|
||||
/* protect windows */
|
||||
decon_shadow_protect_win(ctx, win, true);
|
||||
|
||||
/* wincon */
|
||||
val = readl(ctx->regs + WINCON(win));
|
||||
val &= ~WINCONx_ENWIN;
|
||||
writel(val, ctx->regs + WINCON(win));
|
||||
|
||||
/* unprotect windows */
|
||||
decon_shadow_protect_win(ctx, win, false);
|
||||
|
||||
val = readl(ctx->regs + DECON_UPDATE);
|
||||
val |= DECON_UPDATE_STANDALONE_F;
|
||||
writel(val, ctx->regs + DECON_UPDATE);
|
||||
|
||||
win_data->enabled = false;
|
||||
}
|
||||
|
||||
static void decon_window_suspend(struct decon_context *ctx)
|
||||
{
|
||||
struct decon_win_data *win_data;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < WINDOWS_NR; i++) {
|
||||
win_data = &ctx->win_data[i];
|
||||
win_data->resume = win_data->enabled;
|
||||
if (win_data->enabled)
|
||||
decon_win_disable(ctx->crtc, i);
|
||||
}
|
||||
}
|
||||
|
||||
static void decon_window_resume(struct decon_context *ctx)
|
||||
{
|
||||
struct decon_win_data *win_data;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < WINDOWS_NR; i++) {
|
||||
win_data = &ctx->win_data[i];
|
||||
win_data->enabled = win_data->resume;
|
||||
win_data->resume = false;
|
||||
}
|
||||
}
|
||||
|
||||
static void decon_apply(struct decon_context *ctx)
|
||||
{
|
||||
struct decon_win_data *win_data;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < WINDOWS_NR; i++) {
|
||||
win_data = &ctx->win_data[i];
|
||||
if (win_data->enabled)
|
||||
decon_win_commit(ctx->crtc, i);
|
||||
else
|
||||
decon_win_disable(ctx->crtc, i);
|
||||
}
|
||||
|
||||
decon_commit(ctx->crtc);
|
||||
}
|
||||
|
||||
static void decon_init(struct decon_context *ctx)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
|
||||
|
||||
val = VIDOUTCON0_DISP_IF_0_ON;
|
||||
if (!ctx->i80_if)
|
||||
val |= VIDOUTCON0_RGBIF;
|
||||
writel(val, ctx->regs + VIDOUTCON0);
|
||||
|
||||
writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
|
||||
|
||||
if (!ctx->i80_if)
|
||||
writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
|
||||
}
|
||||
|
||||
static int decon_poweron(struct decon_context *ctx)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!ctx->suspended)
|
||||
return 0;
|
||||
|
||||
ctx->suspended = false;
|
||||
|
||||
pm_runtime_get_sync(ctx->dev);
|
||||
|
||||
ret = clk_prepare_enable(ctx->pclk);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
|
||||
goto pclk_err;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(ctx->aclk);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
|
||||
goto aclk_err;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(ctx->eclk);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
|
||||
goto eclk_err;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(ctx->vclk);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
|
||||
goto vclk_err;
|
||||
}
|
||||
|
||||
decon_init(ctx);
|
||||
|
||||
/* if vblank was enabled status, enable it again. */
|
||||
if (test_and_clear_bit(0, &ctx->irq_flags)) {
|
||||
ret = decon_enable_vblank(ctx->crtc);
|
||||
if (ret) {
|
||||
DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
decon_window_resume(ctx);
|
||||
|
||||
decon_apply(ctx);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
clk_disable_unprepare(ctx->vclk);
|
||||
vclk_err:
|
||||
clk_disable_unprepare(ctx->eclk);
|
||||
eclk_err:
|
||||
clk_disable_unprepare(ctx->aclk);
|
||||
aclk_err:
|
||||
clk_disable_unprepare(ctx->pclk);
|
||||
pclk_err:
|
||||
ctx->suspended = true;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int decon_poweroff(struct decon_context *ctx)
|
||||
{
|
||||
if (ctx->suspended)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* We need to make sure that all windows are disabled before we
|
||||
* suspend that connector. Otherwise we might try to scan from
|
||||
* a destroyed buffer later.
|
||||
*/
|
||||
decon_window_suspend(ctx);
|
||||
|
||||
clk_disable_unprepare(ctx->vclk);
|
||||
clk_disable_unprepare(ctx->eclk);
|
||||
clk_disable_unprepare(ctx->aclk);
|
||||
clk_disable_unprepare(ctx->pclk);
|
||||
|
||||
pm_runtime_put_sync(ctx->dev);
|
||||
|
||||
ctx->suspended = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void decon_dpms(struct exynos_drm_crtc *crtc, int mode)
|
||||
{
|
||||
DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
|
||||
|
||||
switch (mode) {
|
||||
case DRM_MODE_DPMS_ON:
|
||||
decon_poweron(crtc->ctx);
|
||||
break;
|
||||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
decon_poweroff(crtc->ctx);
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG_KMS("unspecified mode %d\n", mode);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static struct exynos_drm_crtc_ops decon_crtc_ops = {
|
||||
.dpms = decon_dpms,
|
||||
.mode_fixup = decon_mode_fixup,
|
||||
.commit = decon_commit,
|
||||
.enable_vblank = decon_enable_vblank,
|
||||
.disable_vblank = decon_disable_vblank,
|
||||
.wait_for_vblank = decon_wait_for_vblank,
|
||||
.win_mode_set = decon_win_mode_set,
|
||||
.win_commit = decon_win_commit,
|
||||
.win_disable = decon_win_disable,
|
||||
};
|
||||
|
||||
|
||||
static irqreturn_t decon_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct decon_context *ctx = (struct decon_context *)dev_id;
|
||||
u32 val, clear_bit;
|
||||
|
||||
val = readl(ctx->regs + VIDINTCON1);
|
||||
|
||||
clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
|
||||
if (val & clear_bit)
|
||||
writel(clear_bit, ctx->regs + VIDINTCON1);
|
||||
|
||||
/* check the crtc is detached already from encoder */
|
||||
if (ctx->pipe < 0 || !ctx->drm_dev)
|
||||
goto out;
|
||||
|
||||
if (!ctx->i80_if) {
|
||||
drm_handle_vblank(ctx->drm_dev, ctx->pipe);
|
||||
exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
|
||||
|
||||
/* set wait vsync event to zero and wake up queue. */
|
||||
if (atomic_read(&ctx->wait_vsync_event)) {
|
||||
atomic_set(&ctx->wait_vsync_event, 0);
|
||||
wake_up(&ctx->wait_vsync_queue);
|
||||
}
|
||||
}
|
||||
out:
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int decon_bind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
struct decon_context *ctx = dev_get_drvdata(dev);
|
||||
struct drm_device *drm_dev = data;
|
||||
int ret;
|
||||
|
||||
ret = decon_ctx_initialize(ctx, drm_dev);
|
||||
if (ret) {
|
||||
DRM_ERROR("decon_ctx_initialize failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
|
||||
EXYNOS_DISPLAY_TYPE_LCD,
|
||||
&decon_crtc_ops, ctx);
|
||||
if (IS_ERR(ctx->crtc)) {
|
||||
decon_ctx_remove(ctx);
|
||||
return PTR_ERR(ctx->crtc);
|
||||
}
|
||||
|
||||
if (ctx->display)
|
||||
exynos_drm_create_enc_conn(drm_dev, ctx->display);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static void decon_unbind(struct device *dev, struct device *master,
|
||||
void *data)
|
||||
{
|
||||
struct decon_context *ctx = dev_get_drvdata(dev);
|
||||
|
||||
decon_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
|
||||
|
||||
if (ctx->display)
|
||||
exynos_dpi_remove(ctx->display);
|
||||
|
||||
decon_ctx_remove(ctx);
|
||||
}
|
||||
|
||||
static const struct component_ops decon_component_ops = {
|
||||
.bind = decon_bind,
|
||||
.unbind = decon_unbind,
|
||||
};
|
||||
|
||||
static int decon_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct decon_context *ctx;
|
||||
struct device_node *i80_if_timings;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
if (!dev->of_node)
|
||||
return -ENODEV;
|
||||
|
||||
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
|
||||
EXYNOS_DISPLAY_TYPE_LCD);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ctx->dev = dev;
|
||||
ctx->suspended = true;
|
||||
|
||||
i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
|
||||
if (i80_if_timings)
|
||||
ctx->i80_if = true;
|
||||
of_node_put(i80_if_timings);
|
||||
|
||||
ctx->regs = of_iomap(dev->of_node, 0);
|
||||
if (IS_ERR(ctx->regs)) {
|
||||
ret = PTR_ERR(ctx->regs);
|
||||
goto err_del_component;
|
||||
}
|
||||
|
||||
ctx->pclk = devm_clk_get(dev, "pclk_decon0");
|
||||
if (IS_ERR(ctx->pclk)) {
|
||||
dev_err(dev, "failed to get bus clock pclk\n");
|
||||
ret = PTR_ERR(ctx->pclk);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
ctx->aclk = devm_clk_get(dev, "aclk_decon0");
|
||||
if (IS_ERR(ctx->aclk)) {
|
||||
dev_err(dev, "failed to get bus clock aclk\n");
|
||||
ret = PTR_ERR(ctx->aclk);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
ctx->eclk = devm_clk_get(dev, "decon0_eclk");
|
||||
if (IS_ERR(ctx->eclk)) {
|
||||
dev_err(dev, "failed to get eclock\n");
|
||||
ret = PTR_ERR(ctx->eclk);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
ctx->vclk = devm_clk_get(dev, "decon0_vclk");
|
||||
if (IS_ERR(ctx->vclk)) {
|
||||
dev_err(dev, "failed to get vclock\n");
|
||||
ret = PTR_ERR(ctx->vclk);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
|
||||
ctx->i80_if ? "lcd_sys" : "vsync");
|
||||
if (!res) {
|
||||
dev_err(dev, "irq request failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, res->start, decon_irq_handler,
|
||||
0, "drm_decon", ctx);
|
||||
if (ret) {
|
||||
dev_err(dev, "irq request failed.\n");
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
init_waitqueue_head(&ctx->wait_vsync_queue);
|
||||
atomic_set(&ctx->wait_vsync_event, 0);
|
||||
|
||||
platform_set_drvdata(pdev, ctx);
|
||||
|
||||
ctx->display = exynos_dpi_probe(dev);
|
||||
if (IS_ERR(ctx->display)) {
|
||||
ret = PTR_ERR(ctx->display);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = component_add(dev, &decon_component_ops);
|
||||
if (ret)
|
||||
goto err_disable_pm_runtime;
|
||||
|
||||
return ret;
|
||||
|
||||
err_disable_pm_runtime:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
err_iounmap:
|
||||
iounmap(ctx->regs);
|
||||
|
||||
err_del_component:
|
||||
exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int decon_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
iounmap(ctx->regs);
|
||||
|
||||
component_del(&pdev->dev, &decon_component_ops);
|
||||
exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct platform_driver decon_driver = {
|
||||
.probe = decon_probe,
|
||||
.remove = decon_remove,
|
||||
.driver = {
|
||||
.name = "exynos-decon",
|
||||
.of_match_table = decon_driver_dt_match,
|
||||
},
|
||||
};
|
||||
|
|
@ -556,6 +556,9 @@ static struct platform_driver *const exynos_drm_kms_drivers[] = {
|
|||
#ifdef CONFIG_DRM_EXYNOS_FIMD
|
||||
&fimd_driver,
|
||||
#endif
|
||||
#ifdef CONFIG_DRM_EXYNOS7_DECON
|
||||
&decon_driver,
|
||||
#endif
|
||||
#ifdef CONFIG_DRM_EXYNOS_DP
|
||||
&dp_driver,
|
||||
#endif
|
||||
|
|
@ -612,6 +615,7 @@ static const char * const strings[] = {
|
|||
"samsung,exynos3",
|
||||
"samsung,exynos4",
|
||||
"samsung,exynos5",
|
||||
"samsung,exynos7",
|
||||
};
|
||||
|
||||
static struct platform_driver exynos_drm_platform_driver = {
|
||||
|
|
|
|||
|
|
@ -344,6 +344,7 @@ void exynos_drm_component_del(struct device *dev,
|
|||
enum exynos_drm_device_type dev_type);
|
||||
|
||||
extern struct platform_driver fimd_driver;
|
||||
extern struct platform_driver decon_driver;
|
||||
extern struct platform_driver dp_driver;
|
||||
extern struct platform_driver dsi_driver;
|
||||
extern struct platform_driver mixer_driver;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,349 @@
|
|||
/* include/video/exynos7_decon.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Ajay Kumar <ajaykumar.rs@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/* VIDCON0 */
|
||||
#define VIDCON0 0x00
|
||||
|
||||
#define VIDCON0_SWRESET (1 << 28)
|
||||
#define VIDCON0_DECON_STOP_STATUS (1 << 2)
|
||||
#define VIDCON0_ENVID (1 << 1)
|
||||
#define VIDCON0_ENVID_F (1 << 0)
|
||||
|
||||
/* VIDOUTCON0 */
|
||||
#define VIDOUTCON0 0x4
|
||||
|
||||
#define VIDOUTCON0_DUAL_MASK (0x3 << 24)
|
||||
#define VIDOUTCON0_DUAL_ON (0x3 << 24)
|
||||
#define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
|
||||
#define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
|
||||
#define VIDOUTCON0_DUAL_OFF (0x0 << 24)
|
||||
#define VIDOUTCON0_IF_SHIFT 23
|
||||
#define VIDOUTCON0_IF_MASK (0x1 << 23)
|
||||
#define VIDOUTCON0_RGBIF (0x0 << 23)
|
||||
#define VIDOUTCON0_I80IF (0x1 << 23)
|
||||
|
||||
/* VIDCON3 */
|
||||
#define VIDCON3 0x8
|
||||
|
||||
/* VIDCON4 */
|
||||
#define VIDCON4 0xC
|
||||
#define VIDCON4_FIFOCNT_START_EN (1 << 0)
|
||||
|
||||
/* VCLKCON0 */
|
||||
#define VCLKCON0 0x10
|
||||
#define VCLKCON0_CLKVALUP (1 << 8)
|
||||
#define VCLKCON0_VCLKFREE (1 << 0)
|
||||
|
||||
/* VCLKCON */
|
||||
#define VCLKCON1 0x14
|
||||
#define VCLKCON1_CLKVAL_NUM_VCLK(val) (((val) & 0xff) << 0)
|
||||
#define VCLKCON2 0x18
|
||||
|
||||
/* SHADOWCON */
|
||||
#define SHADOWCON 0x30
|
||||
|
||||
#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
|
||||
|
||||
/* WINCONx */
|
||||
#define WINCON(_win) (0x50 + ((_win) * 4))
|
||||
|
||||
#define WINCONx_BUFSTATUS (0x3 << 30)
|
||||
#define WINCONx_BUFSEL_MASK (0x3 << 28)
|
||||
#define WINCONx_BUFSEL_SHIFT 28
|
||||
#define WINCONx_TRIPLE_BUF_MODE (0x1 << 18)
|
||||
#define WINCONx_DOUBLE_BUF_MODE (0x0 << 18)
|
||||
#define WINCONx_BURSTLEN_16WORD (0x0 << 11)
|
||||
#define WINCONx_BURSTLEN_8WORD (0x1 << 11)
|
||||
#define WINCONx_BURSTLEN_MASK (0x1 << 11)
|
||||
#define WINCONx_BURSTLEN_SHIFT 11
|
||||
#define WINCONx_BLD_PLANE (0 << 8)
|
||||
#define WINCONx_BLD_PIX (1 << 8)
|
||||
#define WINCONx_ALPHA_MUL (1 << 7)
|
||||
|
||||
#define WINCONx_BPPMODE_MASK (0xf << 2)
|
||||
#define WINCONx_BPPMODE_SHIFT 2
|
||||
#define WINCONx_BPPMODE_16BPP_565 (0x8 << 2)
|
||||
#define WINCONx_BPPMODE_24BPP_BGRx (0x7 << 2)
|
||||
#define WINCONx_BPPMODE_24BPP_RGBx (0x6 << 2)
|
||||
#define WINCONx_BPPMODE_24BPP_xBGR (0x5 << 2)
|
||||
#define WINCONx_BPPMODE_24BPP_xRGB (0x4 << 2)
|
||||
#define WINCONx_BPPMODE_32BPP_BGRA (0x3 << 2)
|
||||
#define WINCONx_BPPMODE_32BPP_RGBA (0x2 << 2)
|
||||
#define WINCONx_BPPMODE_32BPP_ABGR (0x1 << 2)
|
||||
#define WINCONx_BPPMODE_32BPP_ARGB (0x0 << 2)
|
||||
#define WINCONx_ALPHA_SEL (1 << 1)
|
||||
#define WINCONx_ENWIN (1 << 0)
|
||||
|
||||
#define WINCON1_ALPHA_MUL_F (1 << 7)
|
||||
#define WINCON2_ALPHA_MUL_F (1 << 7)
|
||||
#define WINCON3_ALPHA_MUL_F (1 << 7)
|
||||
#define WINCON4_ALPHA_MUL_F (1 << 7)
|
||||
|
||||
/* VIDOSDxH: The height for the OSD image(READ ONLY)*/
|
||||
#define VIDOSD_H(_x) (0x80 + ((_x) * 4))
|
||||
|
||||
/* Frame buffer start addresses: VIDWxxADD0n */
|
||||
#define VIDW_BUF_START(_win) (0x80 + ((_win) * 0x10))
|
||||
#define VIDW_BUF_START1(_win) (0x84 + ((_win) * 0x10))
|
||||
#define VIDW_BUF_START2(_win) (0x88 + ((_win) * 0x10))
|
||||
|
||||
#define VIDW_WHOLE_X(_win) (0x0130 + ((_win) * 8))
|
||||
#define VIDW_WHOLE_Y(_win) (0x0134 + ((_win) * 8))
|
||||
#define VIDW_OFFSET_X(_win) (0x0170 + ((_win) * 8))
|
||||
#define VIDW_OFFSET_Y(_win) (0x0174 + ((_win) * 8))
|
||||
#define VIDW_BLKOFFSET(_win) (0x01B0 + ((_win) * 4))
|
||||
#define VIDW_BLKSIZE(win) (0x0200 + ((_win) * 4))
|
||||
|
||||
/* Interrupt controls register */
|
||||
#define VIDINTCON2 0x228
|
||||
|
||||
#define VIDINTCON1_INTEXTRA1_EN (1 << 1)
|
||||
#define VIDINTCON1_INTEXTRA0_EN (1 << 0)
|
||||
|
||||
/* Interrupt controls and status register */
|
||||
#define VIDINTCON3 0x22C
|
||||
|
||||
#define VIDINTCON1_INTEXTRA1_PEND (1 << 1)
|
||||
#define VIDINTCON1_INTEXTRA0_PEND (1 << 0)
|
||||
|
||||
/* VIDOSDxA ~ VIDOSDxE */
|
||||
#define VIDOSD_BASE 0x230
|
||||
|
||||
#define OSD_STRIDE 0x20
|
||||
|
||||
#define VIDOSD_A(_win) (VIDOSD_BASE + \
|
||||
((_win) * OSD_STRIDE) + 0x00)
|
||||
#define VIDOSD_B(_win) (VIDOSD_BASE + \
|
||||
((_win) * OSD_STRIDE) + 0x04)
|
||||
#define VIDOSD_C(_win) (VIDOSD_BASE + \
|
||||
((_win) * OSD_STRIDE) + 0x08)
|
||||
#define VIDOSD_D(_win) (VIDOSD_BASE + \
|
||||
((_win) * OSD_STRIDE) + 0x0C)
|
||||
#define VIDOSD_E(_win) (VIDOSD_BASE + \
|
||||
((_win) * OSD_STRIDE) + 0x10)
|
||||
|
||||
#define VIDOSDxA_TOPLEFT_X_MASK (0x1fff << 13)
|
||||
#define VIDOSDxA_TOPLEFT_X_SHIFT 13
|
||||
#define VIDOSDxA_TOPLEFT_X_LIMIT 0x1fff
|
||||
#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x1fff) << 13)
|
||||
|
||||
#define VIDOSDxA_TOPLEFT_Y_MASK (0x1fff << 0)
|
||||
#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
|
||||
#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x1fff
|
||||
#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x1fff) << 0)
|
||||
|
||||
#define VIDOSDxB_BOTRIGHT_X_MASK (0x1fff << 13)
|
||||
#define VIDOSDxB_BOTRIGHT_X_SHIFT 13
|
||||
#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x1fff
|
||||
#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x1fff) << 13)
|
||||
|
||||
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x1fff << 0)
|
||||
#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
|
||||
#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x1fff
|
||||
#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x1fff) << 0)
|
||||
|
||||
#define VIDOSDxC_ALPHA0_R_F(_x) (((_x) & 0xFF) << 16)
|
||||
#define VIDOSDxC_ALPHA0_G_F(_x) (((_x) & 0xFF) << 8)
|
||||
#define VIDOSDxC_ALPHA0_B_F(_x) (((_x) & 0xFF) << 0)
|
||||
|
||||
#define VIDOSDxD_ALPHA1_R_F(_x) (((_x) & 0xFF) << 16)
|
||||
#define VIDOSDxD_ALPHA1_G_F(_x) (((_x) & 0xFF) << 8)
|
||||
#define VIDOSDxD_ALPHA1_B_F(_x) (((_x) & 0xFF) >> 0)
|
||||
|
||||
/* Window MAP (Color map) */
|
||||
#define WINxMAP(_win) (0x340 + ((_win) * 4))
|
||||
|
||||
#define WINxMAP_MAP (1 << 24)
|
||||
#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
|
||||
#define WINxMAP_MAP_COLOUR_SHIFT 0
|
||||
#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
|
||||
#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
|
||||
|
||||
/* Window colour-key control registers */
|
||||
#define WKEYCON 0x370
|
||||
|
||||
#define WKEYCON0 0x00
|
||||
#define WKEYCON1 0x04
|
||||
#define WxKEYCON0_KEYBL_EN (1 << 26)
|
||||
#define WxKEYCON0_KEYEN_F (1 << 25)
|
||||
#define WxKEYCON0_DIRCON (1 << 24)
|
||||
#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
|
||||
#define WxKEYCON0_COMPKEY_SHIFT 0
|
||||
#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
|
||||
#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
|
||||
#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
|
||||
#define WxKEYCON1_COLVAL_SHIFT 0
|
||||
#define WxKEYCON1_COLVAL_LIMIT 0xffffff
|
||||
#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
|
||||
|
||||
/* color key control register for hardware window 1 ~ 4. */
|
||||
#define WKEYCON0_BASE(x) ((WKEYCON + WKEYCON0) + ((x - 1) * 8))
|
||||
/* color key value register for hardware window 1 ~ 4. */
|
||||
#define WKEYCON1_BASE(x) ((WKEYCON + WKEYCON1) + ((x - 1) * 8))
|
||||
|
||||
/* Window KEY Alpha value */
|
||||
#define WxKEYALPHA(_win) (0x3A0 + (((_win) - 1) * 0x4))
|
||||
|
||||
#define Wx_KEYALPHA_R_F_SHIFT 16
|
||||
#define Wx_KEYALPHA_G_F_SHIFT 8
|
||||
#define Wx_KEYALPHA_B_F_SHIFT 0
|
||||
|
||||
/* Blending equation */
|
||||
#define BLENDE(_win) (0x03C0 + ((_win) * 4))
|
||||
#define BLENDE_COEF_ZERO 0x0
|
||||
#define BLENDE_COEF_ONE 0x1
|
||||
#define BLENDE_COEF_ALPHA_A 0x2
|
||||
#define BLENDE_COEF_ONE_MINUS_ALPHA_A 0x3
|
||||
#define BLENDE_COEF_ALPHA_B 0x4
|
||||
#define BLENDE_COEF_ONE_MINUS_ALPHA_B 0x5
|
||||
#define BLENDE_COEF_ALPHA0 0x6
|
||||
#define BLENDE_COEF_A 0xA
|
||||
#define BLENDE_COEF_ONE_MINUS_A 0xB
|
||||
#define BLENDE_COEF_B 0xC
|
||||
#define BLENDE_COEF_ONE_MINUS_B 0xD
|
||||
#define BLENDE_Q_FUNC(_v) ((_v) << 18)
|
||||
#define BLENDE_P_FUNC(_v) ((_v) << 12)
|
||||
#define BLENDE_B_FUNC(_v) ((_v) << 6)
|
||||
#define BLENDE_A_FUNC(_v) ((_v) << 0)
|
||||
|
||||
/* Blending equation control */
|
||||
#define BLENDCON 0x3D8
|
||||
#define BLENDCON_NEW_MASK (1 << 0)
|
||||
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
|
||||
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
|
||||
|
||||
/* Interrupt control register */
|
||||
#define VIDINTCON0 0x500
|
||||
|
||||
#define VIDINTCON0_WAKEUP_MASK (0x3f << 26)
|
||||
#define VIDINTCON0_INTEXTRAEN (1 << 21)
|
||||
|
||||
#define VIDINTCON0_FRAMESEL0_SHIFT 15
|
||||
#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
|
||||
#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
|
||||
#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
|
||||
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
|
||||
#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
|
||||
|
||||
#define VIDINTCON0_INT_FRAME (1 << 11)
|
||||
|
||||
#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 3)
|
||||
#define VIDINTCON0_FIFOLEVEL_SHIFT 3
|
||||
#define VIDINTCON0_FIFOLEVEL_EMPTY (0x0 << 3)
|
||||
#define VIDINTCON0_FIFOLEVEL_TO25PC (0x1 << 3)
|
||||
#define VIDINTCON0_FIFOLEVEL_TO50PC (0x2 << 3)
|
||||
#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 3)
|
||||
|
||||
#define VIDINTCON0_FIFOSEL_MAIN_EN (1 << 1)
|
||||
#define VIDINTCON0_INT_FIFO (1 << 1)
|
||||
|
||||
#define VIDINTCON0_INT_ENABLE (1 << 0)
|
||||
|
||||
/* Interrupt controls and status register */
|
||||
#define VIDINTCON1 0x504
|
||||
|
||||
#define VIDINTCON1_INT_EXTRA (1 << 3)
|
||||
#define VIDINTCON1_INT_I80 (1 << 2)
|
||||
#define VIDINTCON1_INT_FRAME (1 << 1)
|
||||
#define VIDINTCON1_INT_FIFO (1 << 0)
|
||||
|
||||
/* VIDCON1 */
|
||||
#define VIDCON1(_x) (0x0600 + ((_x) * 0x50))
|
||||
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 17) & 0x1fff)
|
||||
#define VIDCON1_VCLK_MASK (0x3 << 9)
|
||||
#define VIDCON1_VCLK_HOLD (0x0 << 9)
|
||||
#define VIDCON1_VCLK_RUN (0x1 << 9)
|
||||
#define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9)
|
||||
#define VIDCON1_RGB_ORDER_O_MASK (0x7 << 4)
|
||||
#define VIDCON1_RGB_ORDER_O_RGB (0x0 << 4)
|
||||
#define VIDCON1_RGB_ORDER_O_GBR (0x1 << 4)
|
||||
#define VIDCON1_RGB_ORDER_O_BRG (0x2 << 4)
|
||||
#define VIDCON1_RGB_ORDER_O_BGR (0x4 << 4)
|
||||
#define VIDCON1_RGB_ORDER_O_RBG (0x5 << 4)
|
||||
#define VIDCON1_RGB_ORDER_O_GRB (0x6 << 4)
|
||||
|
||||
/* VIDTCON0 */
|
||||
#define VIDTCON0 0x610
|
||||
|
||||
#define VIDTCON0_VBPD_MASK (0xffff << 16)
|
||||
#define VIDTCON0_VBPD_SHIFT 16
|
||||
#define VIDTCON0_VBPD_LIMIT 0xffff
|
||||
#define VIDTCON0_VBPD(_x) ((_x) << 16)
|
||||
|
||||
#define VIDTCON0_VFPD_MASK (0xffff << 0)
|
||||
#define VIDTCON0_VFPD_SHIFT 0
|
||||
#define VIDTCON0_VFPD_LIMIT 0xffff
|
||||
#define VIDTCON0_VFPD(_x) ((_x) << 0)
|
||||
|
||||
/* VIDTCON1 */
|
||||
#define VIDTCON1 0x614
|
||||
|
||||
#define VIDTCON1_VSPW_MASK (0xffff << 16)
|
||||
#define VIDTCON1_VSPW_SHIFT 16
|
||||
#define VIDTCON1_VSPW_LIMIT 0xffff
|
||||
#define VIDTCON1_VSPW(_x) ((_x) << 16)
|
||||
|
||||
/* VIDTCON2 */
|
||||
#define VIDTCON2 0x618
|
||||
|
||||
#define VIDTCON2_HBPD_MASK (0xffff << 16)
|
||||
#define VIDTCON2_HBPD_SHIFT 16
|
||||
#define VIDTCON2_HBPD_LIMIT 0xffff
|
||||
#define VIDTCON2_HBPD(_x) ((_x) << 16)
|
||||
|
||||
#define VIDTCON2_HFPD_MASK (0xffff << 0)
|
||||
#define VIDTCON2_HFPD_SHIFT 0
|
||||
#define VIDTCON2_HFPD_LIMIT 0xffff
|
||||
#define VIDTCON2_HFPD(_x) ((_x) << 0)
|
||||
|
||||
/* VIDTCON3 */
|
||||
#define VIDTCON3 0x61C
|
||||
|
||||
#define VIDTCON3_HSPW_MASK (0xffff << 16)
|
||||
#define VIDTCON3_HSPW_SHIFT 16
|
||||
#define VIDTCON3_HSPW_LIMIT 0xffff
|
||||
#define VIDTCON3_HSPW(_x) ((_x) << 16)
|
||||
|
||||
/* VIDTCON4 */
|
||||
#define VIDTCON4 0x620
|
||||
|
||||
#define VIDTCON4_LINEVAL_MASK (0xfff << 16)
|
||||
#define VIDTCON4_LINEVAL_SHIFT 16
|
||||
#define VIDTCON4_LINEVAL_LIMIT 0xfff
|
||||
#define VIDTCON4_LINEVAL(_x) (((_x) & 0xfff) << 16)
|
||||
|
||||
#define VIDTCON4_HOZVAL_MASK (0xfff << 0)
|
||||
#define VIDTCON4_HOZVAL_SHIFT 0
|
||||
#define VIDTCON4_HOZVAL_LIMIT 0xfff
|
||||
#define VIDTCON4_HOZVAL(_x) (((_x) & 0xfff) << 0)
|
||||
|
||||
/* LINECNT OP THRSHOLD*/
|
||||
#define LINECNT_OP_THRESHOLD 0x630
|
||||
|
||||
/* CRCCTRL */
|
||||
#define CRCCTRL 0x6C8
|
||||
#define CRCCTRL_CRCCLKEN (0x1 << 2)
|
||||
#define CRCCTRL_CRCSTART_F (0x1 << 1)
|
||||
#define CRCCTRL_CRCEN (0x1 << 0)
|
||||
|
||||
/* DECON_CMU */
|
||||
#define DECON_CMU 0x704
|
||||
|
||||
#define DECON_CMU_ALL_CLKGATE_ENABLE 0x3
|
||||
#define DECON_CMU_SE_CLKGATE_ENABLE (0x1 << 2)
|
||||
#define DECON_CMU_SFR_CLKGATE_ENABLE (0x1 << 1)
|
||||
#define DECON_CMU_MEM_CLKGATE_ENABLE (0x1 << 0)
|
||||
|
||||
/* DECON_UPDATE */
|
||||
#define DECON_UPDATE 0x710
|
||||
|
||||
#define DECON_UPDATE_SLAVE_SYNC (1 << 4)
|
||||
#define DECON_UPDATE_STANDALONE_F (1 << 0)
|
||||
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