MIPS: Alchemy: add sysdev for DBDMA PM.
Add a sysdev for DBDMA PM. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1119/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
Родитель
0f0d85bcc3
Коммит
96d660c482
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@ -36,6 +36,7 @@
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/sysdev.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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@ -174,10 +175,6 @@ static dbdev_tab_t dbdev_tab[] = {
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#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
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#ifdef CONFIG_PM
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static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6];
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#endif
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static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
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@ -960,29 +957,37 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
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return nbytes;
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}
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#ifdef CONFIG_PM
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void au1xxx_dbdma_suspend(void)
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struct alchemy_dbdma_sysdev {
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struct sys_device sysdev;
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u32 pm_regs[NUM_DBDMA_CHANS + 1][6];
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};
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static int alchemy_dbdma_suspend(struct sys_device *dev,
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pm_message_t state)
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{
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struct alchemy_dbdma_sysdev *sdev =
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container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
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int i;
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u32 addr;
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addr = DDMA_GLOBAL_BASE;
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au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00);
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au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04);
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au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08);
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au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c);
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sdev->pm_regs[0][0] = au_readl(addr + 0x00);
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sdev->pm_regs[0][1] = au_readl(addr + 0x04);
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sdev->pm_regs[0][2] = au_readl(addr + 0x08);
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sdev->pm_regs[0][3] = au_readl(addr + 0x0c);
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/* save channel configurations */
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for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
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au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00);
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au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04);
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au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08);
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au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c);
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au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10);
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au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14);
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sdev->pm_regs[i][0] = au_readl(addr + 0x00);
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sdev->pm_regs[i][1] = au_readl(addr + 0x04);
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sdev->pm_regs[i][2] = au_readl(addr + 0x08);
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sdev->pm_regs[i][3] = au_readl(addr + 0x0c);
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sdev->pm_regs[i][4] = au_readl(addr + 0x10);
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sdev->pm_regs[i][5] = au_readl(addr + 0x14);
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/* halt channel */
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au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00);
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au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00);
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au_sync();
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while (!(au_readl(addr + 0x14) & 1))
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au_sync();
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@ -992,32 +997,65 @@ void au1xxx_dbdma_suspend(void)
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/* disable channel interrupts */
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au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
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au_sync();
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return 0;
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}
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void au1xxx_dbdma_resume(void)
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static int alchemy_dbdma_resume(struct sys_device *dev)
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{
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struct alchemy_dbdma_sysdev *sdev =
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container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
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int i;
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u32 addr;
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addr = DDMA_GLOBAL_BASE;
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au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00);
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au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04);
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au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08);
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au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c);
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au_writel(sdev->pm_regs[0][0], addr + 0x00);
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au_writel(sdev->pm_regs[0][1], addr + 0x04);
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au_writel(sdev->pm_regs[0][2], addr + 0x08);
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au_writel(sdev->pm_regs[0][3], addr + 0x0c);
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/* restore channel configurations */
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for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
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au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00);
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au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04);
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au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08);
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au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c);
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au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10);
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au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14);
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au_writel(sdev->pm_regs[i][0], addr + 0x00);
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au_writel(sdev->pm_regs[i][1], addr + 0x04);
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au_writel(sdev->pm_regs[i][2], addr + 0x08);
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au_writel(sdev->pm_regs[i][3], addr + 0x0c);
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au_writel(sdev->pm_regs[i][4], addr + 0x10);
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au_writel(sdev->pm_regs[i][5], addr + 0x14);
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au_sync();
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addr += 0x100; /* next channel base */
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}
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return 0;
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}
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static struct sysdev_class alchemy_dbdma_sysdev_class = {
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.name = "dbdma",
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.suspend = alchemy_dbdma_suspend,
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.resume = alchemy_dbdma_resume,
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};
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static int __init alchemy_dbdma_sysdev_init(void)
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{
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struct alchemy_dbdma_sysdev *sdev;
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int ret;
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ret = sysdev_class_register(&alchemy_dbdma_sysdev_class);
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if (ret)
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return ret;
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sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL);
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if (!sdev)
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return -ENOMEM;
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sdev->sysdev.id = -1;
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sdev->sysdev.cls = &alchemy_dbdma_sysdev_class;
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ret = sysdev_register(&sdev->sysdev);
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if (ret)
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kfree(sdev);
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return ret;
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}
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#endif /* CONFIG_PM */
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static int __init au1xxx_dbdma_init(void)
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{
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@ -1046,6 +1084,11 @@ static int __init au1xxx_dbdma_init(void)
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else {
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dbdma_initialized = 1;
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printk(KERN_INFO "Alchemy DBDMA initialized\n");
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ret = alchemy_dbdma_sysdev_init();
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if (ret) {
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printk(KERN_ERR "DBDMA PM init failed\n");
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ret = 0;
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}
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}
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return ret;
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@ -36,9 +36,6 @@
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#include <asm/uaccess.h>
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#include <asm/mach-au1x00/au1000.h>
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#endif
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#ifdef CONFIG_PM
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@ -129,10 +126,6 @@ static void save_core_regs(void)
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sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
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sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
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sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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au1xxx_dbdma_suspend();
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#endif
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}
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static void restore_core_regs(void)
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@ -196,10 +189,6 @@ static void restore_core_regs(void)
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au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
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au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
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}
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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au1xxx_dbdma_resume();
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#endif
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}
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void au_sleep(void)
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@ -358,10 +358,6 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
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u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
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extern void au1xxx_ddma_del_device(u32 devid);
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void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
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#ifdef CONFIG_PM
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void au1xxx_dbdma_suspend(void);
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void au1xxx_dbdma_resume(void);
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#endif
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/*
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* Flags for the put_source/put_dest functions.
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