Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
This commit is contained in:
Коммит
973c1fabc7
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@ -707,7 +707,7 @@ config FORCE_MAX_ZONEORDER
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config MATH_EMULATION
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bool "Math emulation"
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depends on 4xx || 8xx || E200 || E500
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depends on 4xx || 8xx || E200 || PPC_83xx || E500
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---help---
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Some PowerPC chips designed for embedded applications do not have
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a floating-point unit and therefore do not implement the
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@ -833,7 +833,7 @@ static struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0x7fff0000,
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.pvr_value = 0x00840000,
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.cpu_name = "e300c2",
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.cpu_features = CPU_FTRS_E300,
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.cpu_features = CPU_FTRS_E300C2,
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.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@ -1136,8 +1136,7 @@ static struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xff000fff,
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.pvr_value = 0x53000890,
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.cpu_name = "440SPe Rev. A",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB,
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.cpu_features = CPU_FTRS_44X,
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.cpu_user_features = COMMON_USER_BOOKE,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@ -437,6 +437,13 @@ Alignment:
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/* Floating-point unavailable */
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. = 0x800
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FPUnavailable:
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BEGIN_FTR_SECTION
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/*
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* Certain Freescale cores don't have a FPU and treat fp instructions
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* as a FP Unavailable exception. Redirect to illegal/emulation handling.
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*/
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b ProgramCheck
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END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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EXCEPTION_PROLOG
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bne load_up_fpu /* if from user, just load it up */
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addi r3,r1,STACK_FRAME_OVERHEAD
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@ -109,9 +109,7 @@ int of_device_register(struct of_device *ofdev)
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if (rc)
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return rc;
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device_create_file(&ofdev->dev, &dev_attr_devspec);
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return 0;
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return device_create_file(&ofdev->dev, &dev_attr_devspec);
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}
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void of_device_unregister(struct of_device *ofdev)
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@ -208,7 +208,7 @@ EXPORT_SYMBOL(mmu_hash_lock); /* For MOL */
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extern long *intercept_table;
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EXPORT_SYMBOL(intercept_table);
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#endif /* CONFIG_PPC_STD_MMU_32 */
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#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
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#ifdef CONFIG_PPC_DCR_NATIVE
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EXPORT_SYMBOL(__mtdcr);
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EXPORT_SYMBOL(__mfdcr);
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#endif
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@ -782,6 +782,8 @@ void __kprobes program_check_exception(struct pt_regs *regs)
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unsigned int reason = get_reason(regs);
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extern int do_mathemu(struct pt_regs *regs);
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/* We can now get here via a FP Unavailable exception if the core
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* has no FPU, in that case no reason flags will be set */
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#ifdef CONFIG_MATH_EMULATION
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/* (reason & REASON_ILLEGAL) would be the obvious thing here,
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* but there seems to be a hardware bug on the 405GP (RevD)
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@ -5,7 +5,8 @@ endif
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obj-$(CONFIG_MPIC) += mpic.o
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obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
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obj-$(CONFIG_PPC_MPC106) += grackle.o
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obj-$(CONFIG_PPC_DCR) += dcr.o dcr-low.o
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obj-$(CONFIG_PPC_DCR) += dcr.o
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obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
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obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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@ -126,6 +126,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
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#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
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#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
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#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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@ -296,6 +297,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
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CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_COMMON)
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#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
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CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
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#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
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#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
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@ -366,7 +370,8 @@ enum {
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CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
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CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
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CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
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CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
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CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
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CPU_FTRS_CLASSIC32 |
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#else
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CPU_FTRS_GENERIC_32 |
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#endif
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@ -405,7 +410,8 @@ enum {
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CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
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CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
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CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
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CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
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CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
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CPU_FTRS_CLASSIC32 &
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#else
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CPU_FTRS_GENERIC_32 &
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#endif
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@ -20,8 +20,7 @@
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#ifndef _ASM_POWERPC_DCR_NATIVE_H
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#define _ASM_POWERPC_DCR_NATIVE_H
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#ifdef __KERNEL__
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#include <asm/reg.h>
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#ifndef __ASSEMBLY__
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typedef struct {} dcr_host_t;
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@ -32,7 +31,41 @@ typedef struct {} dcr_host_t;
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#define dcr_read(host, dcr_n) mfdcr(dcr_n)
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#define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value)
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/* Device Control Registers */
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void __mtdcr(int reg, unsigned int val);
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unsigned int __mfdcr(int reg);
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#define mfdcr(rn) \
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({unsigned int rval; \
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if (__builtin_constant_p(rn)) \
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asm volatile("mfdcr %0," __stringify(rn) \
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: "=r" (rval)); \
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else \
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rval = __mfdcr(rn); \
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rval;})
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#define mtdcr(rn, v) \
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do { \
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if (__builtin_constant_p(rn)) \
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asm volatile("mtdcr " __stringify(rn) ",%0" \
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: : "r" (v)); \
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else \
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__mtdcr(rn, v); \
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} while (0)
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/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
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#define mfdcri(base, reg) \
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({ \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mfdcr(base ## _CFGDATA); \
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})
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#define mtdcri(base, reg, data) \
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do { \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mtdcr(base ## _CFGDATA, data); \
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} while (0)
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_DCR_NATIVE_H */
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@ -20,6 +20,7 @@
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#ifndef _ASM_POWERPC_DCR_H
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#define _ASM_POWERPC_DCR_H
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC_DCR
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#ifdef CONFIG_PPC_DCR_NATIVE
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#include <asm/dcr-native.h>
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@ -38,5 +39,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
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unsigned int index);
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#endif /* CONFIG_PPC_MERGE */
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#endif /* CONFIG_PPC_DCR */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_DCR_H */
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@ -9,41 +9,9 @@
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#ifndef __ASM_PPC_REG_BOOKE_H__
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#define __ASM_PPC_REG_BOOKE_H__
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#include <asm/dcr.h>
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#ifndef __ASSEMBLY__
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/* Device Control Registers */
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void __mtdcr(int reg, unsigned int val);
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unsigned int __mfdcr(int reg);
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#define mfdcr(rn) \
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({unsigned int rval; \
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if (__builtin_constant_p(rn)) \
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asm volatile("mfdcr %0," __stringify(rn) \
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: "=r" (rval)); \
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else \
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rval = __mfdcr(rn); \
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rval;})
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#define mtdcr(rn, v) \
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do { \
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if (__builtin_constant_p(rn)) \
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asm volatile("mtdcr " __stringify(rn) ",%0" \
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: : "r" (v)); \
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else \
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__mtdcr(rn, v); \
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} while (0)
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/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
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#define mfdcri(base, reg) \
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({ \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mfdcr(base ## _CFGDATA); \
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})
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#define mtdcri(base, reg, data) \
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do { \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mtdcr(base ## _CFGDATA, data); \
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} while (0)
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/* Performance Monitor Registers */
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#define mfpmr(rn) ({unsigned int rval; \
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asm volatile("mfpmr %0," __stringify(rn) \
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@ -19,6 +19,7 @@
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#define _FSL_DEVICE_H_
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#include <linux/types.h>
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#include <linux/phy.h>
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/*
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* Some conventions on how we handle peripherals on Freescale chips
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