ARM: dts: imx7d: move ARM platform peripherals inside soc node
Since we have a SoC level node we should make use of it and have all nodes which are within the SoC, inside that node. This also saves an extra interrupt-parent properties. While at it, also order the Coresight nodes according to register addresses. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Stefan Agner
Shawn Guo
Родитель
2a8e583c09
Коммит
974a3abcff
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@ -52,6 +52,7 @@
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};
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};
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soc {
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etm@3007d000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x3007d000 0x1000>;
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@ -72,6 +73,7 @@
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};
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};
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};
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};
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};
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&aips3 {
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@ -95,16 +95,6 @@
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};
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};
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intc: interrupt-controller@31001000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x31001000 0x1000>,
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<0x31002000 0x1000>,
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<0x31004000 0x2000>,
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<0x31006000 0x2000>;
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};
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ckil: clock-cki {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@ -119,13 +109,120 @@
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clock-output-names = "osc";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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funnel@30041000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x30041000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ca_funnel_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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ca_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out_port>;
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};
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};
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/* funnel output port */
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port@2 {
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reg = <0>;
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ca_funnel_out_port0: endpoint {
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remote-endpoint = <&hugo_funnel_in_port0>;
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};
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};
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/* the other input ports are not connect to anything */
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};
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};
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etm@3007c000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x3007c000 0x1000>;
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cpu = <&cpu0>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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port {
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etm0_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port0>;
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};
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};
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};
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funnel@30083000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x30083000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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hugo_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&ca_funnel_out_port0>;
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};
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};
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port@1 {
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reg = <1>;
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hugo_funnel_in_port1: endpoint {
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slave-mode; /* M4 input */
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};
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};
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port@2 {
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reg = <0>;
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hugo_funnel_out_port0: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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/* the other input ports are not connect to anything */
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};
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};
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etf@30084000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x30084000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etf_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&hugo_funnel_out_port0>;
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};
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};
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port@1 {
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reg = <0>;
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etf_out_port: endpoint {
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remote-endpoint = <&replicator_in_port0>;
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};
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};
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};
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};
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etr@30086000 {
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@ -193,121 +290,23 @@
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};
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};
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etf@30084000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x30084000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etf_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&hugo_funnel_out_port0>;
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};
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intc: interrupt-controller@31001000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x31001000 0x1000>,
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<0x31002000 0x1000>,
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<0x31004000 0x2000>,
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<0x31006000 0x2000>;
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};
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port@1 {
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reg = <0>;
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etf_out_port: endpoint {
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remote-endpoint = <&replicator_in_port0>;
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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};
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};
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funnel@30083000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x30083000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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hugo_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&ca_funnel_out_port0>;
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};
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};
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port@1 {
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reg = <1>;
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hugo_funnel_in_port1: endpoint {
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slave-mode; /* M4 input */
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};
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};
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port@2 {
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reg = <0>;
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hugo_funnel_out_port0: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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/* the other input ports are not connect to anything */
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};
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};
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funnel@30041000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x30041000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ca_funnel_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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ca_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out_port>;
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};
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};
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/* funnel output port */
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port@2 {
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reg = <0>;
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ca_funnel_out_port0: endpoint {
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remote-endpoint = <&hugo_funnel_in_port0>;
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};
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};
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/* the other input ports are not connect to anything */
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};
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};
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etm@3007c000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x3007c000 0x1000>;
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cpu = <&cpu0>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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port {
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etm0_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port0>;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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aips1: aips-bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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