clk: ti: add composite clock support
This is a multipurpose clock node, which contains support for multiple sub-clocks. Uses basic composite clock type to implement the actual functionality, and TI specific gate, mux and divider clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tero Kristo
Mike Turquette
Родитель
b1a07b478b
Коммит
975e15487d
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@ -0,0 +1,54 @@
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Binding for TI composite clock.
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. It assumes a
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register-mapped composite clock with multiple different sub-types;
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a multiplexer clock with multiple input clock signals or parents, one
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of which can be selected as output, this behaves exactly as [2]
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an adjustable clock rate divider, this behaves exactly as [3]
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a gating function which can be used to enable and disable the output
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clock, this behaves exactly as [4]
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The binding must provide a list of the component clocks that shall be
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merged to this clock. The component clocks shall be of one of the
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"ti,*composite*-clock" types.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/ti/mux.txt
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[3] Documentation/devicetree/bindings/clock/ti/divider.txt
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[4] Documentation/devicetree/bindings/clock/ti/gate.txt
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Required properties:
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- compatible : shall be: "ti,composite-clock"
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- clocks : link phandles of component clocks
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- #clock-cells : from common clock binding; shall be set to 0.
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Examples:
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usb_l4_gate_ick: usb_l4_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <5>;
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reg = <0x0a10>;
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};
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usb_l4_div_ick: usb_l4_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <4>;
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ti,max-div = <1>;
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reg = <0x0a40>;
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ti,index-starts-at-one;
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};
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usb_l4_ick: usb_l4_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
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};
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@ -240,9 +240,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
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int omap2_dflt_clk_enable(struct clk_hw *hw);
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void omap2_dflt_clk_disable(struct clk_hw *hw);
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int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
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void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
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void __iomem **other_reg,
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u8 *other_bit);
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@ -1,4 +1,4 @@
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ifneq ($(CONFIG_OF),)
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obj-y += clk.o autoidle.o
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clk-common = dpll.o
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clk-common = dpll.o composite.o
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endif
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@ -0,0 +1,269 @@
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/*
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* TI composite clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#include <linux/list.h>
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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return -EINVAL;
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}
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static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return -EINVAL;
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}
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static const struct clk_ops ti_composite_divider_ops = {
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.recalc_rate = &ti_composite_recalc_rate,
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.round_rate = &ti_composite_round_rate,
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.set_rate = &ti_composite_set_rate,
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};
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static const struct clk_ops ti_composite_gate_ops = {
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.enable = &omap2_dflt_clk_enable,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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};
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struct component_clk {
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int num_parents;
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const char **parent_names;
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struct device_node *node;
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int type;
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struct clk_hw *hw;
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struct list_head link;
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};
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static const char * __initconst component_clk_types[] = {
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"gate", "divider", "mux"
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};
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static LIST_HEAD(component_clks);
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static struct device_node *_get_component_node(struct device_node *node, int i)
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{
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int rc;
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struct of_phandle_args clkspec;
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rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
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&clkspec);
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if (rc)
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return NULL;
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return clkspec.np;
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}
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static struct component_clk *_lookup_component(struct device_node *node)
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{
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struct component_clk *comp;
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list_for_each_entry(comp, &component_clks, link) {
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if (comp->node == node)
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return comp;
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}
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return NULL;
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}
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struct clk_hw_omap_comp {
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struct clk_hw hw;
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struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
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struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
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};
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static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
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{
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if (!clk)
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return NULL;
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if (!clk->comp_clks[idx])
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return NULL;
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return clk->comp_clks[idx]->hw;
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}
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#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
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static void __init ti_clk_register_composite(struct clk_hw *hw,
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struct device_node *node)
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{
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struct clk *clk;
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struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
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struct component_clk *comp;
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int num_parents = 0;
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const char **parent_names = NULL;
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int i;
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/* Check for presence of each component clock */
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for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
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if (!cclk->comp_nodes[i])
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continue;
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comp = _lookup_component(cclk->comp_nodes[i]);
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if (!comp) {
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pr_debug("component %s not ready for %s, retry\n",
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cclk->comp_nodes[i]->name, node->name);
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if (!ti_clk_retry_init(node, hw,
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ti_clk_register_composite))
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return;
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goto cleanup;
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}
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if (cclk->comp_clks[comp->type] != NULL) {
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pr_err("duplicate component types for %s (%s)!\n",
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node->name, component_clk_types[comp->type]);
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goto cleanup;
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}
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cclk->comp_clks[comp->type] = comp;
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/* Mark this node as found */
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cclk->comp_nodes[i] = NULL;
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}
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/* All components exists, proceed with registration */
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for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
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comp = cclk->comp_clks[i];
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if (!comp)
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continue;
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if (comp->num_parents) {
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num_parents = comp->num_parents;
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parent_names = comp->parent_names;
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break;
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}
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}
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if (!num_parents) {
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pr_err("%s: no parents found for %s!\n", __func__, node->name);
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goto cleanup;
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}
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clk = clk_register_composite(NULL, node->name,
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parent_names, num_parents,
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_get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
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&clk_mux_ops,
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_get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
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&ti_composite_divider_ops,
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_get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
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&ti_composite_gate_ops, 0);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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cleanup:
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/* Free component clock list entries */
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for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
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if (!cclk->comp_clks[i])
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continue;
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list_del(&cclk->comp_clks[i]->link);
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kfree(cclk->comp_clks[i]);
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}
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kfree(cclk);
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}
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static void __init of_ti_composite_clk_setup(struct device_node *node)
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{
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int num_clks;
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int i;
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struct clk_hw_omap_comp *cclk;
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/* Number of component clocks to be put inside this clock */
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num_clks = of_clk_get_parent_count(node);
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if (num_clks < 1) {
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pr_err("composite clk %s must have component(s)\n", node->name);
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return;
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}
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cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
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if (!cclk)
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return;
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/* Get device node pointers for each component clock */
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for (i = 0; i < num_clks; i++)
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cclk->comp_nodes[i] = _get_component_node(node, i);
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ti_clk_register_composite(&cclk->hw, node);
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}
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CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
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of_ti_composite_clk_setup);
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/**
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* ti_clk_add_component - add a component clock to the pool
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* @node: device node of the component clock
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* @hw: hardware clock definition for the component clock
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* @type: type of the component clock
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*
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* Adds a component clock to the list of available components, so that
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* it can be registered by a composite clock.
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*/
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int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
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int type)
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{
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int num_parents;
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const char **parent_names;
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struct component_clk *clk;
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int i;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 1) {
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pr_err("component-clock %s must have parent(s)\n", node->name);
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return -EINVAL;
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}
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parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
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if (!parent_names)
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return -ENOMEM;
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for (i = 0; i < num_parents; i++)
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parent_names[i] = of_clk_get_parent_name(node, i);
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clk = kzalloc(sizeof(*clk), GFP_KERNEL);
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if (!clk) {
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kfree(parent_names);
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return -ENOMEM;
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}
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clk->num_parents = num_parents;
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clk->parent_names = parent_names;
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clk->hw = hw;
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clk->node = node;
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clk->type = type;
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list_add(&clk->link, &component_clks);
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return 0;
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}
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@ -164,6 +164,14 @@ struct clk_hw_omap {
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/* DPLL Type and DCO Selection Flags */
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#define DPLL_J_TYPE 0x1
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/* Composite clock component types */
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enum {
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CLK_COMPONENT_TYPE_GATE = 0,
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CLK_COMPONENT_TYPE_DIVIDER,
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CLK_COMPONENT_TYPE_MUX,
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CLK_COMPONENT_TYPE_MAX,
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};
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/**
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* struct ti_dt_clk - OMAP DT clock alias declarations
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* @lk: clock lookup definition
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@ -236,6 +244,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
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unsigned long parent_rate);
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int omap2_dflt_clk_enable(struct clk_hw *hw);
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void omap2_dflt_clk_disable(struct clk_hw *hw);
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int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
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void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
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void ti_dt_clocks_register(struct ti_dt_clk *oclks);
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@ -243,6 +254,7 @@ void ti_dt_clk_init_provider(struct device_node *np, int index);
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int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
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ti_of_clk_init_cb_t func);
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int of_ti_clk_autoidle_setup(struct device_node *node);
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int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
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#ifdef CONFIG_OF
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void of_ti_clk_allow_autoidle_all(void);
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