Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu updates from Greg Ungerer: "The bulk of the changes are generalizing the ColdFire v3 core support and adding in 537x CPU support. Also a couple of other bug fixes, one to fix a reintroduction of a past bug in the romfs filesystem nommu support." * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68knommu: enable Timer on coldfire 532x m68knommu: fix ColdFire 5373/5329 QSPI base address m68knommu: add support for configuring a Freescale M5373EVB board m68knommu: add support for the ColdFire 537x family of CPUs m68knommu: make ColdFire M532x platform support more v3 generic m68knommu: create and use a common M53xx ColdFire class of CPUs m68k: remove unused asm/dbg.h m68k: Set ColdFire ACR1 cache mode depending on kernel configuration romfs: fix nommu map length to keep inside filesystem m68k: clean up unused "config ROMVECSIZE"
This commit is contained in:
Linus Torvalds
Коммит
977b58e1dd
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@ -223,13 +223,25 @@ config M5307
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help
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Motorola ColdFire 5307 processor support.
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config M53xx
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bool
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config M532x
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bool "MCF532x"
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depends on !MMU
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select M53xx
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select HAVE_CACHE_CB
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help
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Freescale (Motorola) ColdFire 532x processor support.
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config M537x
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bool "MCF537x"
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depends on !MMU
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select M53xx
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select HAVE_CACHE_CB
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help
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Freescale ColdFire 537x processor support.
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config M5407
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bool "MCF5407"
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depends on !MMU
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@ -358,6 +358,13 @@ config COBRA5329
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help
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Support for the senTec COBRA5329 board.
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config M5373EVB
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bool "Freescale M5373EVB board support"
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depends on M537x
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select FREESCALE
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help
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Support for the Freescale M5373EVB board.
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config M5407C3
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bool "Motorola M5407C3 board support"
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depends on M5407
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@ -539,15 +546,6 @@ config ROMVEC
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68000 type variants the vectors are at the base of the boot device
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on system startup.
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config ROMVECSIZE
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hex "Size of ROM vector region (in bytes)"
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default "0x400"
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depends on ROM
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help
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Define the size of the vector region in ROM. For most 68000
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variants this would be 0x400 bytes in size. Set to 0 if you do
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not want a vector region at the start of the ROM.
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config ROMSTART
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hex "Address of the base of system image in ROM"
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default "0x400"
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@ -45,6 +45,7 @@ cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e)
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cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
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cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
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cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
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cpuflags-$(CONFIG_M537x) := $(call cc-option,-mcpu=537x,-m5307)
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cpuflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200)
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cpuflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307)
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cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
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@ -1,6 +0,0 @@
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#define DEBUG 1
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#ifdef CONFIG_COLDFIRE
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#define BREAK asm volatile ("halt")
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#else
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#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
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#endif
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@ -39,7 +39,7 @@
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#define MAX_M68K_DMA_CHANNELS 4
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#elif defined(CONFIG_M5272)
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#define MAX_M68K_DMA_CHANNELS 1
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#elif defined(CONFIG_M532x)
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#elif defined(CONFIG_M53xx)
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#define MAX_M68K_DMA_CHANNELS 0
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#else
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#define MAX_M68K_DMA_CHANNELS 2
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@ -55,8 +55,8 @@
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#define CACHE_SIZE 0x2000 /* 8k of unified cache */
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#define ICACHE_SIZE CACHE_SIZE
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#define DCACHE_SIZE CACHE_SIZE
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#elif defined(CONFIG_M532x)
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#define CACHE_SIZE 0x4000 /* 32k of unified cache */
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#elif defined(CONFIG_M53xx)
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#define CACHE_SIZE 0x4000 /* 16k of unified cache */
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#define ICACHE_SIZE CACHE_SIZE
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#define DCACHE_SIZE CACHE_SIZE
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#endif
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@ -1,15 +1,15 @@
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/****************************************************************************/
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/*
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* m532xsim.h -- ColdFire 5329 registers
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* m53xxsim.h -- ColdFire 5329 registers
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*/
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/****************************************************************************/
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#ifndef m532xsim_h
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#define m532xsim_h
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#ifndef m53xxsim_h
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#define m53xxsim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m532x)"
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#define CPU_NAME "COLDFIRE(m53xx)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 3)
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@ -107,7 +107,7 @@
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
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#define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
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#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
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#define MCFQSPI_CS0 84
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@ -1238,4 +1238,4 @@
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#define MCFEPORT_EPFR (0xFC094006)
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/********************************************************************/
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#endif /* m532xsim_h */
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#endif /* m53xxsim_h */
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@ -96,8 +96,13 @@
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*/
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#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
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ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
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#if defined(CONFIG_CACHE_COPYBACK)
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#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_SP)
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ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
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#else
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#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
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#endif
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#define ACR2_MODE 0
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#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
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ACR_ENABLE+ACR_SUPER+ACR_SP)
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@ -104,7 +104,7 @@ static inline void gpio_free(unsigned gpio)
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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/* These parts have GPIO organized by 8 bit ports */
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@ -139,7 +139,7 @@ static inline void gpio_free(unsigned gpio)
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#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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/*
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* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
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* read-modify-write to change an output and a GPIO module which has separate
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@ -195,7 +195,7 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
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return MCFSIM2_GPIO1READ;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPPDR;
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@ -237,7 +237,7 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
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return MCFSIM2_GPIO1WRITE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPDR;
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@ -279,7 +279,7 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
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return MCFSIM2_GPIO1ENABLE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPDDR;
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@ -36,8 +36,8 @@
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#elif defined(CONFIG_M5307)
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#include <asm/m5307sim.h>
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#include <asm/mcfintc.h>
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#elif defined(CONFIG_M532x)
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#include <asm/m532xsim.h>
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#elif defined(CONFIG_M53xx)
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#include <asm/m53xxsim.h>
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#elif defined(CONFIG_M5407)
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#include <asm/m5407sim.h>
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#include <asm/mcfintc.h>
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@ -19,7 +19,7 @@
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#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
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#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
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#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
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#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
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#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
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#else
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#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
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@ -25,7 +25,7 @@ obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
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obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
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obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
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obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
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obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
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obj-$(CONFIG_M53xx) += m53xx.o timers.o intc-simr.o reset.o
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obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
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obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
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obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
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@ -1,7 +1,7 @@
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/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/532x/config.c
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* m53xx.c -- platform support for ColdFire 53xx based boards
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*
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* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2000, Lineo (www.lineo.com)
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@ -118,7 +118,8 @@ static struct clk * const enable_clks[] __initconst = {
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&__clk_0_24, /* mcfuart.0 */
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&__clk_0_25, /* mcfuart.1 */
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&__clk_0_26, /* mcfuart.2 */
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&__clk_0_28, /* mcftmr.0 */
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&__clk_0_29, /* mcftmr.1 */
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&__clk_0_32, /* mcfpit.0 */
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&__clk_0_33, /* mcfpit.1 */
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&__clk_0_37, /* mcfeport.0 */
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@ -134,8 +135,6 @@ static struct clk * const disable_clks[] __initconst = {
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&__clk_0_17, /* edma */
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&__clk_0_22, /* mcfi2c.0 */
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&__clk_0_23, /* mcfqspi.0 */
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&__clk_0_28, /* mcftmr.0 */
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&__clk_0_29, /* mcftmr.1 */
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&__clk_0_30, /* mcftmr.2 */
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&__clk_0_31, /* mcftmr.3 */
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&__clk_0_34, /* mcfpit.2 */
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@ -153,7 +152,7 @@ static struct clk * const disable_clks[] __initconst = {
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};
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static void __init m532x_clk_init(void)
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static void __init m53xx_clk_init(void)
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{
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unsigned i;
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@ -169,7 +168,7 @@ static void __init m532x_clk_init(void)
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m532x_qspi_init(void)
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static void __init m53xx_qspi_init(void)
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{
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/* setup QSPS pins for QSPI with gpio CS control */
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writew(0x01f0, MCFGPIO_PAR_QSPI);
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@ -179,7 +178,7 @@ static void __init m532x_qspi_init(void)
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/***************************************************************************/
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static void __init m532x_uarts_init(void)
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static void __init m53xx_uarts_init(void)
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{
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/* UART GPIO initialization */
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writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
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@ -187,7 +186,7 @@ static void __init m532x_uarts_init(void)
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/***************************************************************************/
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static void __init m532x_fec_init(void)
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static void __init m53xx_fec_init(void)
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{
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u8 v;
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@ -217,11 +216,11 @@ void __init config_BSP(char *commandp, int size)
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}
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#endif
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mach_sched_init = hw_timer_init;
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m532x_clk_init();
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m532x_uarts_init();
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m532x_fec_init();
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m53xx_clk_init();
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m53xx_uarts_init();
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m53xx_fec_init();
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m532x_qspi_init();
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m53xx_qspi_init();
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#endif
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#ifdef CONFIG_BDM_DISABLE
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@ -36,7 +36,7 @@
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*/
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void coldfire_profile_init(void);
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#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
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#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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#define __raw_readtrr __raw_readl
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#define __raw_writetrr __raw_writel
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#else
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@ -14,7 +14,6 @@
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* 2.4/2.5 port David McCullough
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*/
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#include <asm/dbg.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/serial.h>
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@ -49,8 +49,11 @@ static unsigned long romfs_get_unmapped_area(struct file *file,
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return (unsigned long) -EINVAL;
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offset += ROMFS_I(inode)->i_dataoffset;
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if (offset > mtd->size - len)
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if (offset >= mtd->size)
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return (unsigned long) -EINVAL;
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/* the mapping mustn't extend beyond the EOF */
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if ((offset + len) > mtd->size)
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len = mtd->size - offset;
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ret = mtd_get_unmapped_area(mtd, len, offset, flags);
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if (ret == -EOPNOTSUPP)
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