staging: rtl8821ae: Fix C99 style comments in efuse.c
Fix C99 style comments in efuse.c. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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fc4d82c057
Коммит
977d68c320
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@ -149,7 +149,7 @@ u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address)
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return 0xFF;
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}
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//EXPORT_SYMBOL(efuse_read_1byte);
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/* EXPORT_SYMBOL(efuse_read_1byte); */
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void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value)
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{
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@ -517,7 +517,7 @@ void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw)
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rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
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}
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//EXPORT_SYMBOL(rtl_efuse_shadow_map_update);
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/* EXPORT_SYMBOL(rtl_efuse_shadow_map_update); */
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void efuse_force_write_vendor_Id(struct ieee80211_hw *hw)
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{
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@ -628,7 +628,7 @@ int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data)
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}
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return bresult;
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}
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//EXPORT_SYMBOL(efuse_one_byte_read);
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/* EXPORT_SYMBOL(efuse_one_byte_read); */
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static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr, u8 data)
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{
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@ -1120,16 +1120,16 @@ static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite, u8 pwrstate)
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{
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rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_ACCESS], 0x69);
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// 1.2V Power: From VDDON with Power Cut(0x0000h[15]), default valid
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/* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), default valid */
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tmpV16 = rtl_read_word(rtlpriv,
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rtlpriv->cfg->maps[SYS_ISO_CTRL]);
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printk("SYS_ISO_CTRL=%04x.\n",tmpV16);
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if( ! (tmpV16 & PWC_EV12V ) ){
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tmpV16 |= PWC_EV12V ;
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//PlatformEFIOWrite2Byte(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
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/* PlatformEFIOWrite2Byte(pAdapter,REG_SYS_ISO_CTRL,tmpV16); */
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}
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// Reset: 0x0000h[28], default valid
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/* Reset: 0x0000h[28], default valid */
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tmpV16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN]);
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printk("SYS_FUNC_EN=%04x.\n",tmpV16);
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if( !(tmpV16 & FEN_ELDR) ){
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@ -1137,7 +1137,7 @@ static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite, u8 pwrstate)
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rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN], tmpV16);
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}
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// Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid
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/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
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tmpV16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_CLK] );
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printk("SYS_CLK=%04x.\n",tmpV16);
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if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) )
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@ -1148,7 +1148,7 @@ static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite, u8 pwrstate)
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if(bwrite == true)
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{
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// Enable LDO 2.5V before read/write action
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/* Enable LDO 2.5V before read/write action */
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tempval = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
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printk("EFUSE_TEST=%04x.\n",tmpV16);
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tempval &= ~(BIT(3) | BIT(4) |BIT(5) | BIT(6));
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@ -1161,7 +1161,7 @@ static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite, u8 pwrstate)
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{
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rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_ACCESS], 0x00);
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if(bwrite == true){
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// Disable LDO 2.5V after read/write action
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/* Disable LDO 2.5V after read/write action */
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tempval = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
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rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3, (tempval & 0x7F));
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}
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