mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip
Add support for the Altera Arria10 Development Kit System Resource chip which is implemented using a MAX5 as a external gpio extender with the regmap framework over a SPI bus. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Thor Thayer
Lee Jones
Родитель
8ce064bfe7
Коммит
9787f5e28b
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@ -18,6 +18,17 @@ config MFD_CS5535
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This is the core driver for CS5535/CS5536 MFD functions. This is
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This is the core driver for CS5535/CS5536 MFD functions. This is
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necessary for using the board's GPIO and MFGPT functionality.
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necessary for using the board's GPIO and MFGPT functionality.
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config MFD_ALTERA_A10SR
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bool "Altera Arria10 DevKit System Resource chip"
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depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
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select REGMAP_SPI
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select MFD_CORE
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help
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Support for the Altera Arria10 DevKit MAX5 System Resource chip
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using the SPI interface. This driver provides common support for
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accessing the external gpio extender (LEDs & buttons) and
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power supply alarms (hwmon).
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config MFD_ACT8945A
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config MFD_ACT8945A
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tristate "Active-semi ACT8945A"
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tristate "Active-semi ACT8945A"
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select MFD_CORE
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select MFD_CORE
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@ -205,3 +205,5 @@ intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
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intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o
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intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o
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obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
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obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
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obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
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obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
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obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
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@ -0,0 +1,169 @@
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/*
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* Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* SPI access for Altera Arria10 MAX5 System Resource Chip
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*
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* Adapted from DA9052
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*/
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#include <linux/mfd/altera-a10sr.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/spi/spi.h>
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static const struct mfd_cell altr_a10sr_subdev_info[] = {
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{
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.name = "altr_a10sr_gpio",
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.of_compatible = "altr,a10sr-gpio",
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},
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};
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static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ALTR_A10SR_VERSION_READ:
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case ALTR_A10SR_LED_REG:
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case ALTR_A10SR_PBDSW_REG:
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case ALTR_A10SR_PBDSW_IRQ_REG:
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case ALTR_A10SR_PWR_GOOD1_REG:
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case ALTR_A10SR_PWR_GOOD2_REG:
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case ALTR_A10SR_PWR_GOOD3_REG:
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case ALTR_A10SR_FMCAB_REG:
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case ALTR_A10SR_HPS_RST_REG:
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case ALTR_A10SR_USB_QSPI_REG:
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case ALTR_A10SR_SFPA_REG:
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case ALTR_A10SR_SFPB_REG:
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case ALTR_A10SR_I2C_M_REG:
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case ALTR_A10SR_WARM_RST_REG:
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case ALTR_A10SR_WR_KEY_REG:
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case ALTR_A10SR_PMBUS_REG:
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return true;
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default:
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return false;
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}
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}
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static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ALTR_A10SR_LED_REG:
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case ALTR_A10SR_PBDSW_IRQ_REG:
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case ALTR_A10SR_FMCAB_REG:
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case ALTR_A10SR_HPS_RST_REG:
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case ALTR_A10SR_USB_QSPI_REG:
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case ALTR_A10SR_SFPA_REG:
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case ALTR_A10SR_SFPB_REG:
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case ALTR_A10SR_WARM_RST_REG:
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case ALTR_A10SR_WR_KEY_REG:
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case ALTR_A10SR_PMBUS_REG:
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return true;
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default:
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return false;
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}
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}
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static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ALTR_A10SR_PBDSW_REG:
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case ALTR_A10SR_PBDSW_IRQ_REG:
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case ALTR_A10SR_PWR_GOOD1_REG:
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case ALTR_A10SR_PWR_GOOD2_REG:
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case ALTR_A10SR_PWR_GOOD3_REG:
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case ALTR_A10SR_HPS_RST_REG:
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case ALTR_A10SR_I2C_M_REG:
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case ALTR_A10SR_WARM_RST_REG:
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case ALTR_A10SR_WR_KEY_REG:
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case ALTR_A10SR_PMBUS_REG:
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return true;
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default:
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return false;
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}
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}
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const struct regmap_config altr_a10sr_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_NONE,
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.use_single_rw = true,
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.read_flag_mask = 1,
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.write_flag_mask = 0,
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.max_register = ALTR_A10SR_WR_KEY_REG,
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.readable_reg = altr_a10sr_reg_readable,
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.writeable_reg = altr_a10sr_reg_writeable,
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.volatile_reg = altr_a10sr_reg_volatile,
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};
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static int altr_a10sr_spi_probe(struct spi_device *spi)
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{
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int ret;
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struct altr_a10sr *a10sr;
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a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
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GFP_KERNEL);
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if (!a10sr)
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return -ENOMEM;
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spi->mode = SPI_MODE_3;
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spi->bits_per_word = 8;
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spi_setup(spi);
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a10sr->dev = &spi->dev;
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spi_set_drvdata(spi, a10sr);
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a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
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if (IS_ERR(a10sr->regmap)) {
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ret = PTR_ERR(a10sr->regmap);
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dev_err(&spi->dev, "Failed to allocate register map: %d\n",
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ret);
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return ret;
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}
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ret = devm_mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
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altr_a10sr_subdev_info,
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ARRAY_SIZE(altr_a10sr_subdev_info),
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NULL, 0, NULL);
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if (ret)
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dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
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ret);
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return ret;
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}
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static const struct of_device_id altr_a10sr_spi_of_match[] = {
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{ .compatible = "altr,a10sr" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
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static struct spi_driver altr_a10sr_spi_driver = {
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.probe = altr_a10sr_spi_probe,
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.driver = {
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.name = "altr_a10sr",
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.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
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},
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};
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module_spi_driver(altr_a10sr_spi_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
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MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
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@ -0,0 +1,85 @@
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/*
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* Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Declarations for Altera Arria10 MAX5 System Resource Chip
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*
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* Adapted from DA9052
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*/
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#ifndef __MFD_ALTERA_A10SR_H
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#define __MFD_ALTERA_A10SR_H
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#include <linux/completion.h>
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#include <linux/list.h>
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#include <linux/mfd/core.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* Write registers are always on even addresses */
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#define WRITE_REG_MASK 0xFE
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/* Odd registers are always on odd addresses */
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#define READ_REG_MASK 0x01
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#define ALTR_A10SR_BITS_PER_REGISTER 8
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/*
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* To find the correct register, we divide the input GPIO by
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* the number of GPIO in each register. We then need to multiply
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* by 2 because the reads are at odd addresses.
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*/
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#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
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#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER)
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#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
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#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X))
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/* Arria10 System Controller Register Defines */
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#define ALTR_A10SR_NOP 0x00 /* No Change */
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#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */
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#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
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/* LED register Bit Definitions */
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#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
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#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT
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#define ALTR_A10SR_OUT_VALID_RANGE_HI 7
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#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
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#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */
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/* Pushbutton & DIP Switch Bit Definitions */
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#define ALTR_A10SR_IN_VALID_RANGE_LO 8
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#define ALTR_A10SR_IN_VALID_RANGE_HI 15
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#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */
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#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */
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#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */
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#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */
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#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */
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#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */
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#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */
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#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */
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#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */
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#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */
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#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */
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#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */
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/**
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* struct altr_a10sr - Altera Max5 MFD device private data structure
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* @dev: : this device
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* @regmap: the regmap assigned to the parent device.
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*/
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struct altr_a10sr {
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struct device *dev;
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struct regmap *regmap;
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};
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#endif /* __MFD_ALTERA_A10SR_H */
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