atm: [iphase] 64-bit cleanup
This fixes the most obvious 64-bit problems, but it is still very very broken in other aspects. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Chas Williams <chas@cmf.nrl.navy.mil> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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61c33e0129
Коммит
97928f7021
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@ -294,7 +294,7 @@ config ATM_HORIZON_DEBUG
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config ATM_IA
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tristate "Interphase ATM PCI x575/x525/x531"
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depends on PCI && !64BIT
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depends on PCI
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---help---
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This is a driver for the Interphase (i)ChipSAR adapter cards
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which include a variety of variants in term of the size of the
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@ -89,10 +89,6 @@ module_param(IADebugFlag, uint, 0644);
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MODULE_LICENSE("GPL");
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#if BITS_PER_LONG != 32
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# error FIXME: this driver only works on 32-bit platforms
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#endif
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/**************************** IA_LIB **********************************/
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static void ia_init_rtn_q (IARTN_Q *que)
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@ -1406,7 +1402,6 @@ static int rx_init(struct atm_dev *dev)
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struct abr_vc_table *abr_vc_table;
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u16 *vc_table;
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u16 *reass_table;
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u16 *ptr16;
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int i,j, vcsize_sel;
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u_short freeq_st_adr;
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u_short *freeq_start;
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@ -1421,14 +1416,15 @@ static int rx_init(struct atm_dev *dev)
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printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
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goto err_out;
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}
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iadev->rx_dle_q.start = (struct dle*)dle_addr;
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iadev->rx_dle_q.start = (struct dle *)dle_addr;
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iadev->rx_dle_q.read = iadev->rx_dle_q.start;
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iadev->rx_dle_q.write = iadev->rx_dle_q.start;
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iadev->rx_dle_q.end = (struct dle*)((u32)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
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iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
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/* the end of the dle q points to the entry after the last
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DLE that can be used. */
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/* write the upper 20 bits of the start address to rx list address register */
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/* We know this is 32bit bus addressed so the following is safe */
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writel(iadev->rx_dle_dma & 0xfffff000,
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iadev->dma + IPHASE5575_RX_LIST_ADDR);
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IF_INIT(printk("Tx Dle list addr: 0x%08x value: 0x%0x\n",
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@ -1582,11 +1578,12 @@ static int rx_init(struct atm_dev *dev)
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Set Packet Aging Interval count register to overflow in about 4 us
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*/
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writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
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ptr16 = (u16*)j;
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i = ((u32)ptr16 >> 6) & 0xff;
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ptr16 += j - 1;
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i |=(((u32)ptr16 << 2) & 0xff00);
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i = (j >> 6) & 0xFF;
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j += 2 * (j - 1);
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i |= ((j << 2) & 0xFF00);
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writew(i, iadev->reass_reg+TMOUT_RANGE);
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/* initiate the desc_tble */
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for(i=0; i<iadev->num_tx_desc;i++)
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iadev->desc_tbl[i].timestamp = 0;
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@ -1909,7 +1906,7 @@ static int tx_init(struct atm_dev *dev)
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iadev->tx_dle_q.start = (struct dle*)dle_addr;
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iadev->tx_dle_q.read = iadev->tx_dle_q.start;
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iadev->tx_dle_q.write = iadev->tx_dle_q.start;
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iadev->tx_dle_q.end = (struct dle*)((u32)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
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iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
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/* write the upper 20 bits of the start address to tx list address register */
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writel(iadev->tx_dle_dma & 0xfffff000,
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@ -2902,7 +2899,7 @@ static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
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dev_kfree_skb_any(skb);
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return 0;
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}
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if ((u32)skb->data & 3) {
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if ((unsigned long)skb->data & 3) {
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printk("Misaligned SKB\n");
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if (vcc->pop)
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vcc->pop(vcc, skb);
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