ARM: arm-soc platform updates for 3.10, part 1
This branch contains platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRgg+LAAoJEIwa5zzehBx3ePcP/3NUsSOTRQ2SZIVpyjnWOhkf RMZiRaVsxrY0BPfDB9E2Vcb6lannKmACTujs/Ux7kJC22BreuFM1PnZoDfhkRuSE n/nVB1981XJS82z2uONRSZGlUPSGWYzhTTUDJ0nHiBGmIGf5ctnC0iYWp3As3lv9 kNY14H7NkwQ4zBVNEMu7WfW8d2IJgqZJgR9xhZPv5fOZ+LlQmK6VaHWTmQtjyea1 bG1qoJ0dPbfJB4Vnr3a49rBkSJxZUiv8xQucw9+vo+ADRi64M4sZ1Jj2vVyDpqZp F4fxBNMVvg7xM0TcBbItFFYJBXlUjeT4z+UI5iYjkbnE7EV9ndFeZXHCWX1qzOSy X/nrJKuoe7ISQanBE9SHS9DpDGlkPDO0Mn0vb1f2VUQOY513pt/D1iFYEucZ6WCN fWUYtvt5GayidUr55D1U8ssbE0oGt2rizd9x7GUk4KbRVAnUUNopIQAhXrefTrZm jfdZNDckJ2F3aq8IPjsKuyJTpe61xD4Wvb3P/pEE3Q8fowPF5WIxXV+qjqHQ9vtt Tz4LkP/YdynVFGmhOwz3QZmPaQItaabaYyCcZ5cVCvt5mdxx5VuHYppafhCPJz+V KCQpKi1azuIv+sDR+nlGOl6+Ideea3s7TsRudfbmQFp5GsqkqOdJzR9gbbKmJauQ 4JPpRd+4W8wC8zXQnhVY =HXX3 -----END PGP SIGNATURE----- Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "This branch contains part 1 of the platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits) ARM: tegra: pm: fix build error w/o PM_SLEEP ARM: davinci: ensure global variables are declared ARM: davinci: sram.c: fix incorrect type in assignment ARM: davinci: da8xx dt: make file local symbols static ARM: davinci: da8xx: add remoteproc support ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries ARM: socfpga: Add clock entries into device tree ARM: socfpga: Enable soft reset ARM: EXYNOS: replace cpumask by the corresponding macro ARM: EXYNOS: handle properly the return values ARM: EXYNOS: factor out the idle states ARM: OMAP4: Enable fix for Cortex-A9 erratas ARM: OMAP2+: Export SoC information to userspace ARM: OMAP2+: SoC name and revision unification ARM: OMAP2+: Move common part of late init into common function ARM: tegra: pm: remove duplicated include from pm.c ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: SAMSUNG: check processor type before cache restoration in resume ...
This commit is contained in:
Коммит
97b1007a29
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@ -0,0 +1,11 @@
|
|||
Altera SOCFPGA Clock Manager
|
||||
|
||||
Required properties:
|
||||
- compatible : "altr,clk-mgr"
|
||||
- reg : Should contain base address and length for Clock Manager
|
||||
|
||||
Example:
|
||||
clkmgr@ffd04000 {
|
||||
compatible = "altr,clk-mgr";
|
||||
reg = <0xffd04000 0x1000>;
|
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};
|
|
@ -0,0 +1,19 @@
|
|||
Broadcom Kona Family timer
|
||||
-----------------------------------------------------
|
||||
This timer is used in the following Broadcom SoCs:
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
|
||||
|
||||
Required properties:
|
||||
- compatible : "bcm,kona-timer"
|
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- reg : Register range for the timer
|
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- interrupts : interrupt for the timer
|
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- clock-frequency: frequency that the clock operates
|
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|
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Example:
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timer@35006000 {
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compatible = "bcm,kona-timer";
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reg = <0x35006000 0x1000>;
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interrupts = <0x0 7 0x4>;
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clock-frequency = <32768>;
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};
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|
|
@ -3,36 +3,35 @@
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Properties:
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- compatible : Should at least contain "qcom,msm-timer". More specific
|
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properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
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purpose timer and a debug timer respectively.
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properties specify which subsystem the timers are paired with.
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- interrupts : Interrupt indicating a match event.
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"qcom,kpss-timer" - krait subsystem
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"qcom,scss-timer" - scorpion subsystem
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- reg : Specifies the base address of the timer registers. The second region
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specifies an optional register used to configure the clock divider.
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- interrupts : Interrupts for the the debug timer, the first general purpose
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timer, and optionally a second general purpose timer in that
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order.
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- clock-frequency : The frequency of the timer in Hz.
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- reg : Specifies the base address of the timer registers.
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- clock-frequency : The frequency of the debug timer and the general purpose
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timer(s) in Hz in that order.
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Optional:
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- cpu-offset : per-cpu offset used when the timer is accessed without the
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CPU remapping facilities. The offset is cpu-offset * cpu-nr.
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CPU remapping facilities. The offset is
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cpu-offset + (0x10000 * cpu-nr).
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|
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Example:
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 3 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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timer@200a000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <19200000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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|
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|
@ -1,19 +1,84 @@
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NVIDIA Tegra Power Management Controller (PMC)
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Properties:
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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|
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Required properties:
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- name : Should be pmc
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- compatible : Should contain "nvidia,tegra<chip>-pmc".
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- reg : Offset and length of the register set for the device
|
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- clocks : Must contain an entry for each entry in clock-names.
|
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- clock-names : Must include the following entries:
|
||||
"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
|
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|
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Optional properties:
|
||||
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
|
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The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and then
|
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fed into the ARM GIC. The PMC is not involved in the detection or
|
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handling of this interrupt signal, merely its inversion.
|
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- nvidia,suspend-mode : The suspend mode that the platform should use.
|
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
|
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1 (LP1): CPU voltage off and DRAM in self-refresh
|
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2 (LP2): CPU voltage off
|
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
|
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
|
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
|
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
|
||||
is enabled.
|
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|
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Required properties when nvidia,suspend-mode is specified:
|
||||
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
|
||||
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
|
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Core power good time in uS.
|
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- nvidia,core-pwr-off-time : Core power off time in uS.
|
||||
|
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Required properties when nvidia,suspend-mode=<0>:
|
||||
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
|
||||
The LP0 vector contains the warm boot code that is executed by AVP when
|
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
|
||||
processor and always being the first boot processor when chip is power on
|
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or resume from deep sleep mode. When the system is resumed from the deep
|
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sleep mode, the warm boot code will restore some PLLs, clocks and then
|
||||
bring up CPU0 for resuming the system.
|
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|
||||
Example:
|
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/ SoC dts including file
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pmc@7000f400 {
|
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compatible = "nvidia,tegra20-pmc";
|
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reg = <0x7000e400 0x400>;
|
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clocks = <&tegra_car 110>, <&clk32k_in>;
|
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clock-names = "pclk", "clk32k_in";
|
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nvidia,invert-interrupt;
|
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nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
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nvidia,cpu-pwr-off-time = <100>;
|
||||
nvidia,core-pwr-good-time = <3845 3845>;
|
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nvidia,core-pwr-off-time = <458>;
|
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nvidia,core-power-req-active-high;
|
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nvidia,sys-clock-req-active-high;
|
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
|
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};
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|
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/ Tegra board dts file
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{
|
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...
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clocks {
|
||||
compatible = "simple-bus";
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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|
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clk32k_in: clock {
|
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compatible = "fixed-clock";
|
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reg=<0>;
|
||||
#clock-cells = <0>;
|
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clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
...
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||||
};
|
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|
|
|
@ -0,0 +1,18 @@
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Device Tree Clock bindings for Altera's SoCFPGA platform
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"altr,socfpga-pll-clock" - for a PLL clock
|
||||
"altr,socfpga-perip-clock" - The peripheral clock divided from the
|
||||
PLL clock.
|
||||
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
|
||||
- clocks : shall be the input parent clock phandle for the clock. This is
|
||||
either an oscillator or a pll output.
|
||||
- #clock-cells : from common clock binding, shall be set to 0.
|
||||
|
||||
Optional properties:
|
||||
- fixed-divider : If clocks have a fixed divider value, use this property.
|
|
@ -0,0 +1,33 @@
|
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* TI Highspeed MMC host controller for DaVinci
|
||||
|
||||
The Highspeed MMC Host Controller on TI DaVinci family
|
||||
provides an interface for MMC, SD and SDIO types of memory cards.
|
||||
|
||||
This file documents the properties used by the davinci_mmc driver.
|
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|
||||
Required properties:
|
||||
- compatible:
|
||||
Should be "ti,da830-mmc": for da830, da850, dm365
|
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Should be "ti,dm355-mmc": for dm355, dm644x
|
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|
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Optional properties:
|
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- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
|
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- max-frequency: Maximum operating clock frequency, default 25MHz.
|
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- dmas: List of DMA specifiers with the controller specific format
|
||||
as described in the generic DMA client binding. A tx and rx
|
||||
specifier is required.
|
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- dma-names: RX and TX DMA request names. These strings correspond
|
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1:1 with the DMA specifiers listed in dmas.
|
||||
|
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Example:
|
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mmc0: mmc@1c40000 {
|
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compatible = "ti,da830-mmc",
|
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reg = <0x40000 0x1000>;
|
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interrupts = <16>;
|
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status = "okay";
|
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bus-width = <4>;
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max-frequency = <50000000>;
|
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dmas = <&edma 16
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&edma 17>;
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dma-names = "rx", "tx";
|
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};
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@ -45,6 +45,7 @@ parameter is applicable:
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AX25 Appropriate AX.25 support is enabled.
|
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BLACKFIN Blackfin architecture is enabled.
|
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CLK Common clock infrastructure is enabled.
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CMA Contiguous Memory Area support is enabled.
|
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DRM Direct Rendering Management support is enabled.
|
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DYNAMIC_DEBUG Build in debug messages and enable them at runtime
|
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EDD BIOS Enhanced Disk Drive Services (EDD) is enabled
|
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|
@ -2724,6 +2725,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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Useful for devices that are detected asynchronously
|
||||
(e.g. USB and MMC devices).
|
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rproc_mem=nn[KMG][@address]
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[KNL,ARM,CMA] Remoteproc physical memory block.
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Memory area to be used by remote processor image,
|
||||
managed by CMA.
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||||
|
||||
rw [KNL] Mount root device read-write on boot
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S [KNL] Run init in single mode
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|
|
|
@ -671,6 +671,7 @@ config ARCH_TEGRA
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select HAVE_CLK
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select SOC_BUS
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select SPARSE_IRQ
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select USE_OF
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||||
help
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|
@ -1666,7 +1667,7 @@ config ARCH_NR_GPIO
|
|||
int
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default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
|
||||
default 512 if SOC_OMAP5
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default 355 if ARCH_U8500
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||||
default 392 if ARCH_U8500
|
||||
default 288 if ARCH_VT8500 || ARCH_SUNXI
|
||||
default 264 if MACH_H4700
|
||||
default 0
|
||||
|
|
|
@ -33,6 +33,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
|
|||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
|
||||
# sama5d3
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
|
||||
|
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* DTS file for CSR SiRFatlas6 Evaluation Board
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "atlas6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CSR SiRFatlas6 Evaluation Board";
|
||||
compatible = "sirf,atlas6-cb", "sirf,atlas6";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
axi {
|
||||
peri-iobg {
|
||||
uart@b0060000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins_a>;
|
||||
};
|
||||
spi@b00d0000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins_a>;
|
||||
spi@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
spi@b0170000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
};
|
||||
i2c0: i2c@b00e0000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
lcd@40 {
|
||||
compatible = "sirf,lcd";
|
||||
reg = <0x40>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
disp-iobg {
|
||||
lcd@90010000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_24pins_a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
display: display@0 {
|
||||
panels {
|
||||
panel0: panel@0 {
|
||||
panel-name = "Innolux TFT";
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
left_margin = <20>;
|
||||
right_margin = <234>;
|
||||
upper_margin = <3>;
|
||||
lower_margin = <41>;
|
||||
hsync_len = <3>;
|
||||
vsync_len = <2>;
|
||||
pixclock = <33264000>;
|
||||
sync = <3>;
|
||||
timing = <0x88>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,668 @@
|
|||
/*
|
||||
* DTS file for CSR SiRFatlas6 SoC
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
compatible = "sirf,atlas6";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
/* from bootloader */
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0x80000000>;
|
||||
|
||||
intc: interrupt-controller@80020000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "sirf,prima2-intc";
|
||||
reg = <0x80020000 0x1000>;
|
||||
};
|
||||
|
||||
sys-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x88000000 0x88000000 0x40000>;
|
||||
|
||||
clks: clock-controller@88000000 {
|
||||
compatible = "sirf,atlas6-clkc";
|
||||
reg = <0x88000000 0x1000>;
|
||||
interrupts = <3>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
reset-controller@88010000 {
|
||||
compatible = "sirf,prima2-rstc";
|
||||
reg = <0x88010000 0x1000>;
|
||||
};
|
||||
|
||||
rsc-controller@88020000 {
|
||||
compatible = "sirf,prima2-rsc";
|
||||
reg = <0x88020000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
mem-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90000000 0x90000000 0x10000>;
|
||||
|
||||
memory-controller@90000000 {
|
||||
compatible = "sirf,prima2-memc";
|
||||
reg = <0x90000000 0x10000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&clks 5>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90010000 0x90010000 0x30000>;
|
||||
|
||||
lcd@90010000 {
|
||||
compatible = "sirf,prima2-lcd";
|
||||
reg = <0x90010000 0x20000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 34>;
|
||||
display=<&display>;
|
||||
/* later transfer to pwm */
|
||||
bl-gpio = <&gpio 7 0>;
|
||||
default-panel = <&panel0>;
|
||||
};
|
||||
|
||||
vpp@90020000 {
|
||||
compatible = "sirf,prima2-vpp";
|
||||
reg = <0x90020000 0x10000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks 35>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x98000000 0x98000000 0x8000000>;
|
||||
|
||||
graphics@98000000 {
|
||||
compatible = "powervr,sgx510";
|
||||
reg = <0x98000000 0x8000000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 32>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa8000000 0xa8000000 0x2000000>;
|
||||
|
||||
dspif@a8000000 {
|
||||
compatible = "sirf,prima2-dspif";
|
||||
reg = <0xa8000000 0x10000>;
|
||||
interrupts = <9>;
|
||||
};
|
||||
|
||||
gps@a8010000 {
|
||||
compatible = "sirf,prima2-gps";
|
||||
reg = <0xa8010000 0x10000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&clks 9>;
|
||||
};
|
||||
|
||||
dsp@a9000000 {
|
||||
compatible = "sirf,prima2-dsp";
|
||||
reg = <0xa9000000 0x1000000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 8>;
|
||||
};
|
||||
};
|
||||
|
||||
peri-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0xb0000000 0x180000>,
|
||||
<0x56000000 0x56000000 0x1b00000>;
|
||||
|
||||
timer@b0020000 {
|
||||
compatible = "sirf,prima2-tick";
|
||||
reg = <0xb0020000 0x1000>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
nand@b0030000 {
|
||||
compatible = "sirf,prima2-nand";
|
||||
reg = <0xb0030000 0x10000>;
|
||||
interrupts = <41>;
|
||||
clocks = <&clks 26>;
|
||||
};
|
||||
|
||||
audio@b0040000 {
|
||||
compatible = "sirf,prima2-audio";
|
||||
reg = <0xb0040000 0x10000>;
|
||||
interrupts = <35>;
|
||||
clocks = <&clks 27>;
|
||||
};
|
||||
|
||||
uart0: uart@b0050000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0050000 0x1000>;
|
||||
interrupts = <17>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 13>;
|
||||
};
|
||||
|
||||
uart1: uart@b0060000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0060000 0x1000>;
|
||||
interrupts = <18>;
|
||||
fifosize = <32>;
|
||||
clocks = <&clks 14>;
|
||||
};
|
||||
|
||||
uart2: uart@b0070000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0070000 0x1000>;
|
||||
interrupts = <19>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 15>;
|
||||
};
|
||||
|
||||
usp0: usp@b0080000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0080000 0x10000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 28>;
|
||||
};
|
||||
|
||||
usp1: usp@b0090000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0090000 0x10000>;
|
||||
interrupts = <21>;
|
||||
clocks = <&clks 29>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@b00b0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb00b0000 0x10000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&clks 24>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@b0160000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb0160000 0x10000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks 25>;
|
||||
};
|
||||
|
||||
vip@b00C0000 {
|
||||
compatible = "sirf,prima2-vip";
|
||||
reg = <0xb00C0000 0x10000>;
|
||||
clocks = <&clks 31>;
|
||||
};
|
||||
|
||||
spi0: spi@b00d0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb00d0000 0x10000>;
|
||||
interrupts = <15>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio 0 0>;
|
||||
sirf,spi-dma-rx-channel = <25>;
|
||||
sirf,spi-dma-tx-channel = <20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 19>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@b0170000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb0170000 0x10000>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@b00e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00e0000 0x10000>;
|
||||
interrupts = <24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 17>;
|
||||
};
|
||||
|
||||
i2c1: i2c@b00f0000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00f0000 0x10000>;
|
||||
interrupts = <25>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 18>;
|
||||
};
|
||||
|
||||
tsc@b0110000 {
|
||||
compatible = "sirf,prima2-tsc";
|
||||
reg = <0xb0110000 0x10000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks 16>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@b0120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas6-pinctrl";
|
||||
reg = <0xb0120000 0x10000>;
|
||||
interrupts = <43 44 45 46 47>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
||||
lcd_16pins_a: lcd0@0 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_16bitsgrp";
|
||||
sirf,function = "lcd_16bits";
|
||||
};
|
||||
};
|
||||
lcd_18pins_a: lcd0@1 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_18bitsgrp";
|
||||
sirf,function = "lcd_18bits";
|
||||
};
|
||||
};
|
||||
lcd_24pins_a: lcd0@2 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_24bitsgrp";
|
||||
sirf,function = "lcd_24bits";
|
||||
};
|
||||
};
|
||||
lcdrom_pins_a: lcdrom0@0 {
|
||||
lcd {
|
||||
sirf,pins = "lcdromgrp";
|
||||
sirf,function = "lcdrom";
|
||||
};
|
||||
};
|
||||
uart0_pins_a: uart0@0 {
|
||||
uart {
|
||||
sirf,pins = "uart0grp";
|
||||
sirf,function = "uart0";
|
||||
};
|
||||
};
|
||||
uart1_pins_a: uart1@0 {
|
||||
uart {
|
||||
sirf,pins = "uart1grp";
|
||||
sirf,function = "uart1";
|
||||
};
|
||||
};
|
||||
uart2_pins_a: uart2@0 {
|
||||
uart {
|
||||
sirf,pins = "uart2grp";
|
||||
sirf,function = "uart2";
|
||||
};
|
||||
};
|
||||
uart2_noflow_pins_a: uart2@1 {
|
||||
uart {
|
||||
sirf,pins = "uart2_nostreamctrlgrp";
|
||||
sirf,function = "uart2_nostreamctrl";
|
||||
};
|
||||
};
|
||||
spi0_pins_a: spi0@0 {
|
||||
spi {
|
||||
sirf,pins = "spi0grp";
|
||||
sirf,function = "spi0";
|
||||
};
|
||||
};
|
||||
spi1_pins_a: spi1@0 {
|
||||
spi {
|
||||
sirf,pins = "spi1grp";
|
||||
sirf,function = "spi1";
|
||||
};
|
||||
};
|
||||
i2c0_pins_a: i2c0@0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c0grp";
|
||||
sirf,function = "i2c0";
|
||||
};
|
||||
};
|
||||
i2c1_pins_a: i2c1@0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c1grp";
|
||||
sirf,function = "i2c1";
|
||||
};
|
||||
};
|
||||
pwm0_pins_a: pwm0@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm0grp";
|
||||
sirf,function = "pwm0";
|
||||
};
|
||||
};
|
||||
pwm1_pins_a: pwm1@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm1grp";
|
||||
sirf,function = "pwm1";
|
||||
};
|
||||
};
|
||||
pwm2_pins_a: pwm2@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm2grp";
|
||||
sirf,function = "pwm2";
|
||||
};
|
||||
};
|
||||
pwm3_pins_a: pwm3@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm3grp";
|
||||
sirf,function = "pwm3";
|
||||
};
|
||||
};
|
||||
pwm4_pins_a: pwm4@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm4grp";
|
||||
sirf,function = "pwm4";
|
||||
};
|
||||
};
|
||||
gps_pins_a: gps@0 {
|
||||
gps {
|
||||
sirf,pins = "gpsgrp";
|
||||
sirf,function = "gps";
|
||||
};
|
||||
};
|
||||
vip_pins_a: vip@0 {
|
||||
vip {
|
||||
sirf,pins = "vipgrp";
|
||||
sirf,function = "vip";
|
||||
};
|
||||
};
|
||||
sdmmc0_pins_a: sdmmc0@0 {
|
||||
sdmmc0 {
|
||||
sirf,pins = "sdmmc0grp";
|
||||
sirf,function = "sdmmc0";
|
||||
};
|
||||
};
|
||||
sdmmc1_pins_a: sdmmc1@0 {
|
||||
sdmmc1 {
|
||||
sirf,pins = "sdmmc1grp";
|
||||
sirf,function = "sdmmc1";
|
||||
};
|
||||
};
|
||||
sdmmc2_pins_a: sdmmc2@0 {
|
||||
sdmmc2 {
|
||||
sirf,pins = "sdmmc2grp";
|
||||
sirf,function = "sdmmc2";
|
||||
};
|
||||
};
|
||||
sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
|
||||
sdmmc2_nowp {
|
||||
sirf,pins = "sdmmc2_nowpgrp";
|
||||
sirf,function = "sdmmc2_nowp";
|
||||
};
|
||||
};
|
||||
sdmmc3_pins_a: sdmmc3@0 {
|
||||
sdmmc3 {
|
||||
sirf,pins = "sdmmc3grp";
|
||||
sirf,function = "sdmmc3";
|
||||
};
|
||||
};
|
||||
sdmmc5_pins_a: sdmmc5@0 {
|
||||
sdmmc5 {
|
||||
sirf,pins = "sdmmc5grp";
|
||||
sirf,function = "sdmmc5";
|
||||
};
|
||||
};
|
||||
i2s_pins_a: i2s@0 {
|
||||
i2s {
|
||||
sirf,pins = "i2sgrp";
|
||||
sirf,function = "i2s";
|
||||
};
|
||||
};
|
||||
i2s_no_din_pins_a: i2s_no_din@0 {
|
||||
i2s_no_din {
|
||||
sirf,pins = "i2s_no_dingrp";
|
||||
sirf,function = "i2s_no_din";
|
||||
};
|
||||
};
|
||||
i2s_6chn_pins_a: i2s_6chn@0 {
|
||||
i2s_6chn {
|
||||
sirf,pins = "i2s_6chngrp";
|
||||
sirf,function = "i2s_6chn";
|
||||
};
|
||||
};
|
||||
ac97_pins_a: ac97@0 {
|
||||
ac97 {
|
||||
sirf,pins = "ac97grp";
|
||||
sirf,function = "ac97";
|
||||
};
|
||||
};
|
||||
nand_pins_a: nand@0 {
|
||||
nand {
|
||||
sirf,pins = "nandgrp";
|
||||
sirf,function = "nand";
|
||||
};
|
||||
};
|
||||
usp0_pins_a: usp0@0 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0grp";
|
||||
sirf,function = "usp0";
|
||||
};
|
||||
};
|
||||
usp1_pins_a: usp1@0 {
|
||||
usp1 {
|
||||
sirf,pins = "usp1grp";
|
||||
sirf,function = "usp1";
|
||||
};
|
||||
};
|
||||
usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
|
||||
usb0_upli_drvbus {
|
||||
sirf,pins = "usb0_upli_drvbusgrp";
|
||||
sirf,function = "usb0_upli_drvbus";
|
||||
};
|
||||
};
|
||||
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
|
||||
usb1_utmi_drvbus {
|
||||
sirf,pins = "usb1_utmi_drvbusgrp";
|
||||
sirf,function = "usb1_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
warm_rst_pins_a: warm_rst@0 {
|
||||
warm_rst {
|
||||
sirf,pins = "warm_rstgrp";
|
||||
sirf,function = "warm_rst";
|
||||
};
|
||||
};
|
||||
pulse_count_pins_a: pulse_count@0 {
|
||||
pulse_count {
|
||||
sirf,pins = "pulse_countgrp";
|
||||
sirf,function = "pulse_count";
|
||||
};
|
||||
};
|
||||
cko0_rst_pins_a: cko0_rst@0 {
|
||||
cko0_rst {
|
||||
sirf,pins = "cko0_rstgrp";
|
||||
sirf,function = "cko0_rst";
|
||||
};
|
||||
};
|
||||
cko1_rst_pins_a: cko1_rst@0 {
|
||||
cko1_rst {
|
||||
sirf,pins = "cko1_rstgrp";
|
||||
sirf,function = "cko1_rst";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@b0130000 {
|
||||
compatible = "sirf,prima2-pwm";
|
||||
reg = <0xb0130000 0x10000>;
|
||||
clocks = <&clks 21>;
|
||||
};
|
||||
|
||||
efusesys@b0140000 {
|
||||
compatible = "sirf,prima2-efuse";
|
||||
reg = <0xb0140000 0x10000>;
|
||||
clocks = <&clks 22>;
|
||||
};
|
||||
|
||||
pulsec@b0150000 {
|
||||
compatible = "sirf,prima2-pulsec";
|
||||
reg = <0xb0150000 0x10000>;
|
||||
interrupts = <48>;
|
||||
clocks = <&clks 23>;
|
||||
};
|
||||
|
||||
pci-iobg {
|
||||
compatible = "sirf,prima2-pciiobg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x56000000 0x56000000 0x1b00000>;
|
||||
|
||||
sd0: sdhci@56000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56000000 0x100000>;
|
||||
interrupts = <38>;
|
||||
bus-width = <8>;
|
||||
clocks = <&clks 36>;
|
||||
};
|
||||
|
||||
sd1: sdhci@56100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56100000 0x100000>;
|
||||
interrupts = <38>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 36>;
|
||||
};
|
||||
|
||||
sd2: sdhci@56200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56200000 0x100000>;
|
||||
interrupts = <23>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 37>;
|
||||
};
|
||||
|
||||
sd3: sdhci@56300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56300000 0x100000>;
|
||||
interrupts = <23>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 37>;
|
||||
};
|
||||
|
||||
sd5: sdhci@56500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56500000 0x100000>;
|
||||
interrupts = <39>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 38>;
|
||||
};
|
||||
|
||||
pci-copy@57900000 {
|
||||
compatible = "sirf,prima2-pcicp";
|
||||
reg = <0x57900000 0x100000>;
|
||||
interrupts = <40>;
|
||||
};
|
||||
|
||||
rom-interface@57a00000 {
|
||||
compatible = "sirf,prima2-romif";
|
||||
reg = <0x57a00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80030000 0x10000>;
|
||||
|
||||
gpsrtc@1000 {
|
||||
compatible = "sirf,prima2-gpsrtc";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <55 56 57>;
|
||||
};
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,prima2-sysrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <52 53 54>;
|
||||
};
|
||||
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,prima2-pwrc";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
uus-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb8000000 0xb8000000 0x40000>;
|
||||
|
||||
usb0: usb@b00e0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8000000 0x10000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clks 40>;
|
||||
};
|
||||
|
||||
usb1: usb@b00f0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8010000 0x10000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&clks 41>;
|
||||
};
|
||||
|
||||
security@b00f0000 {
|
||||
compatible = "sirf,prima2-security";
|
||||
reg = <0xb8030000 0x10000>;
|
||||
interrupts = <42>;
|
||||
clocks = <&clks 7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -47,4 +47,12 @@
|
|||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
timer@35006000 {
|
||||
compatible = "bcm,kona-timer";
|
||||
reg = <0x35006000 0x1000>;
|
||||
interrupts = <0x0 7 0x4>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
@ -35,14 +35,84 @@
|
|||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
tps: tps@48 {
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
wdt: wdt@1c21000 {
|
||||
status = "okay";
|
||||
};
|
||||
mmc0: mmc@1c40000 {
|
||||
max-frequency = <50000000>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins>;
|
||||
};
|
||||
};
|
||||
nand_cs3@62000000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_cs3_pins>;
|
||||
};
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps6507x.dtsi"
|
||||
|
||||
&tps {
|
||||
vdcdc1_2-supply = <&vbat>;
|
||||
vdcdc3-supply = <&vbat>;
|
||||
vldo1_2-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vdcdc1_reg: regulator@0 {
|
||||
regulator-name = "VDCDC1_3.3V";
|
||||
regulator-min-microvolt = <3150000>;
|
||||
regulator-max-microvolt = <3450000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdcdc2_reg: regulator@1 {
|
||||
regulator-name = "VDCDC2_3.3V";
|
||||
regulator-min-microvolt = <1710000>;
|
||||
regulator-max-microvolt = <3450000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
ti,defdcdc_default = <1>;
|
||||
};
|
||||
|
||||
vdcdc3_reg: regulator@2 {
|
||||
regulator-name = "VDCDC3_1.2V";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
ti,defdcdc_default = <1>;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-name = "LDO1_1.8V";
|
||||
regulator-min-microvolt = <1710000>;
|
||||
regulator-max-microvolt = <1890000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-name = "LDO2_1.2V";
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1320000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -62,6 +62,15 @@
|
|||
0x10 0x00002200 0x0000ff00
|
||||
>;
|
||||
};
|
||||
mmc0_pins: pinmux_mmc_pins {
|
||||
pinctrl-single,bits = <
|
||||
/* MMCSD0_DAT[3] MMCSD0_DAT[2]
|
||||
* MMCSD0_DAT[1] MMCSD0_DAT[0]
|
||||
* MMCSD0_CMD MMCSD0_CLK
|
||||
*/
|
||||
0x28 0x00222222 0x00ffffff
|
||||
>;
|
||||
};
|
||||
};
|
||||
serial0: serial@1c42000 {
|
||||
compatible = "ns16550a";
|
||||
|
@ -107,6 +116,12 @@
|
|||
reg = <0x21000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
mmc0: mmc@1c40000 {
|
||||
compatible = "ti,da830-mmc";
|
||||
reg = <0x40000 0x1000>;
|
||||
interrupts = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
nand_cs3@62000000 {
|
||||
compatible = "ti,davinci-nand";
|
||||
|
|
|
@ -16,19 +16,13 @@
|
|||
};
|
||||
|
||||
timer@2000004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>;
|
||||
reg = <0x02000004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
timer@2000024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 0 0x301>;
|
||||
reg = <0x02000024 0x10>,
|
||||
<0x02000034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
compatible = "qcom,scss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 0 0x301>,
|
||||
<1 1 0x301>,
|
||||
<1 2 0x301>;
|
||||
reg = <0x02000000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
|
|
|
@ -15,20 +15,14 @@
|
|||
< 0x02002000 0x1000 >;
|
||||
};
|
||||
|
||||
timer@200a004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 2 0x301>;
|
||||
reg = <0x0200a004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
timer@200a024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>;
|
||||
reg = <0x0200a024 0x10>,
|
||||
<0x0200a034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
|
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Device Tree Source for Renesas r8a7779
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7779";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f0001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xf0001000 0x1000>,
|
||||
<0xf0000100 0x100>;
|
||||
};
|
||||
|
||||
i2c0: i2c@0xffc70000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 79 0x4>;
|
||||
};
|
||||
|
||||
i2c1: i2c@0xffc71000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 82 0x4>;
|
||||
};
|
||||
|
||||
i2c2: i2c@0xffc72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 80 0x4>;
|
||||
};
|
||||
|
||||
i2c3: i2c@0xffc73000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 81 0x4>;
|
||||
};
|
||||
|
||||
thermal@ffc48000 {
|
||||
compatible = "renesas,rcar-thermal";
|
||||
reg = <0xffc48000 0x38>;
|
||||
};
|
||||
|
||||
sata: sata@fc600000 {
|
||||
compatible = "renesas,rcar-sata";
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 100 0x4>;
|
||||
};
|
||||
};
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* sama5d31ek.dts - Device Tree file for SAMA5D31-EK board
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "sama5d3xmb.dtsi"
|
||||
/include/ "sama5d3xdm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel SAMA5D31-EK";
|
||||
compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
spi0: spi@f0004000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssc0: ssc@f0008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f0014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb1: ethernet@f802c000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
d3 {
|
||||
label = "d3";
|
||||
gpios = <&pioE 24 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* sama5d33ek.dts - Device Tree file for SAMA5D33-EK board
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "sama5d3xmb.dtsi"
|
||||
/include/ "sama5d3xdm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel SAMA5D33-EK";
|
||||
compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
spi0: spi@f0004000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssc0: ssc@f0008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f0014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f0028000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* sama5d34ek.dts - Device Tree file for SAMA5D34-EK board
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "sama5d3xmb.dtsi"
|
||||
/include/ "sama5d3xdm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel SAMA5D34-EK";
|
||||
compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
spi0: spi@f0004000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssc0: ssc@f0008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
can0: can@f000c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f0014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
|
||||
24c256@50 {
|
||||
compatible = "24c256";
|
||||
reg = <0x50>;
|
||||
pagesize = <64>;
|
||||
};
|
||||
};
|
||||
|
||||
macb0: ethernet@f0028000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
d3 {
|
||||
label = "d3";
|
||||
gpios = <&pioE 24 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* sama5d35ek.dts - Device Tree file for SAMA5D35-EK board
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "sama5d3xmb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel SAMA5D35-EK";
|
||||
compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
spi0: spi@f0004000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
can0: can@f000c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f0028000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
isi: isi@f0034000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb1: ethernet@f802c000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pb_user1 {
|
||||
label = "pb_user1";
|
||||
gpios = <&pioE 27 0>;
|
||||
linux,code = <0x100>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/include/ "sama5d3.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x20000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@f0028000 {
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@60000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
atmel,has-pmecc;
|
||||
atmel,pmecc-cap = <4>;
|
||||
atmel,pmecc-sector-size = <512>;
|
||||
atmel,has-nfc;
|
||||
atmel,use-nfc-sram;
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
bootloader@40000 {
|
||||
label = "bootloader";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
bootloaderenv@c0000 {
|
||||
label = "bootloader env";
|
||||
reg = <0xc0000 0xc0000>;
|
||||
};
|
||||
|
||||
dtb@180000 {
|
||||
label = "device tree";
|
||||
reg = <0x180000 0x80000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d2 {
|
||||
label = "d2";
|
||||
gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* sama5d3dm.dtsi - Device Tree file for SAMA5 display module
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
apb {
|
||||
i2c1: i2c@f0018000 {
|
||||
qt1070: keyboard@1b {
|
||||
compatible = "qt1070";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&pioE>;
|
||||
interrupts = <31 0x0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qt1070_irq>;
|
||||
};
|
||||
};
|
||||
|
||||
adc0: adc@f8018000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsadcc: tsadcc@f8018000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
board {
|
||||
pinctrl_qt1070_irq: qt1070_irq {
|
||||
atmel,pins =
|
||||
<4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/include/ "sama5d3xcm.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
mmc0: mmc@f0000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 17 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f0004000 {
|
||||
m25p80@0 {
|
||||
compatible = "atmel,at25df321a";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* i2c0 conflicts with ISI:
|
||||
* disable it to allow the use of ISI
|
||||
* can not enable audio when i2c0 disabled
|
||||
*/
|
||||
i2c0: i2c@f0014000 {
|
||||
wm8904: wm8904@1a {
|
||||
compatible = "wm8904";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@f0020000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
isi: isi@f0034000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
|
||||
};
|
||||
|
||||
mmc1: mmc@f8000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 18 0>;
|
||||
};
|
||||
};
|
||||
|
||||
adc0: adc@f8018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&pinctrl_adc0_adtrg
|
||||
&pinctrl_adc0_ad0
|
||||
&pinctrl_adc0_ad1
|
||||
&pinctrl_adc0_ad2
|
||||
&pinctrl_adc0_ad3
|
||||
&pinctrl_adc0_ad4
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb1: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
board {
|
||||
pinctrl_mmc0_cd: mmc0_cd {
|
||||
atmel,pins =
|
||||
<3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
|
||||
};
|
||||
|
||||
pinctrl_mmc1_cd: mmc1_cd {
|
||||
atmel,pins =
|
||||
<3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
|
||||
};
|
||||
|
||||
pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
|
||||
atmel,pins =
|
||||
<3 30 0x2 0x0>; /* PD30 periph B */
|
||||
};
|
||||
|
||||
pinctrl_isi_reset: isi_reset-0 {
|
||||
atmel,pins =
|
||||
<4 24 0x0 0x0>; /* PE24 gpio */
|
||||
};
|
||||
|
||||
pinctrl_isi_power: isi_power-0 {
|
||||
atmel,pins =
|
||||
<4 29 0x0 0x0>; /* PE29 gpio */
|
||||
};
|
||||
|
||||
pinctrl_usba_vbus: usba_vbus {
|
||||
atmel,pins =
|
||||
<3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: gadget@00500000 {
|
||||
atmel,vbus-gpio = <&pioD 29 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usba_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: ohci@00600000 {
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <&pioD 25 0
|
||||
&pioD 26 1
|
||||
&pioD 27 1
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "atmel,sama5d3ek-wm8904";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
|
||||
|
||||
atmel,model = "wm8904 @ SAMA5D3EK";
|
||||
atmel,audio-routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"IN2L", "Line In Jack",
|
||||
"IN2R", "Line In Jack",
|
||||
"IN1L", "Mic";
|
||||
|
||||
atmel,ssc-controller = <&ssc0>;
|
||||
atmel,audio-codec = <&wm8904>;
|
||||
};
|
||||
};
|
|
@ -81,6 +81,163 @@
|
|||
};
|
||||
};
|
||||
|
||||
clkmgr@ffd04000 {
|
||||
compatible = "altr,clk-mgr";
|
||||
reg = <0xffd04000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: osc1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
main_pll: main_pll {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x40>;
|
||||
|
||||
mpuclk: mpuclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
fixed-divider = <2>;
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
mainclk: mainclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
fixed-divider = <4>;
|
||||
reg = <0x4C>;
|
||||
};
|
||||
|
||||
dbg_base_clk: dbg_base_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
fixed-divider = <4>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
main_qspi_clk: main_qspi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
main_nand_sdmmc_clk: main_nand_sdmmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
reg = <0x58>;
|
||||
};
|
||||
|
||||
cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
reg = <0x5C>;
|
||||
};
|
||||
};
|
||||
|
||||
periph_pll: periph_pll {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x80>;
|
||||
|
||||
emac0_clk: emac0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x88>;
|
||||
};
|
||||
|
||||
emac1_clk: emac1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x8C>;
|
||||
};
|
||||
|
||||
per_qspi_clk: per_qsi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x90>;
|
||||
};
|
||||
|
||||
per_nand_mmc_clk: per_nand_mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x94>;
|
||||
};
|
||||
|
||||
per_base_clk: per_base_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x98>;
|
||||
};
|
||||
|
||||
s2f_usr1_clk: s2f_usr1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x9C>;
|
||||
};
|
||||
};
|
||||
|
||||
sdram_pll: sdram_pll {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0xC0>;
|
||||
|
||||
ddr_dqs_clk: ddr_dqs_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xC8>;
|
||||
};
|
||||
|
||||
ddr_2x_dqs_clk: ddr_2x_dqs_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xCC>;
|
||||
};
|
||||
|
||||
ddr_dq_clk: ddr_dq_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xD0>;
|
||||
};
|
||||
|
||||
s2f_usr2_clk: s2f_usr2_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xD4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: stmmac@ff700000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
||||
reg = <0xff700000 0x2000>;
|
||||
|
|
|
@ -33,6 +33,14 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
clkmgr@ffd04000 {
|
||||
clocks {
|
||||
osc1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer0@ffc08000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
|
|
@ -33,6 +33,14 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
clkmgr@ffd04000 {
|
||||
clocks {
|
||||
osc1 {
|
||||
clock-frequency = <10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer0@ffc08000 {
|
||||
clock-frequency = <7000000>;
|
||||
};
|
||||
|
|
|
@ -18,4 +18,17 @@
|
|||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -18,4 +18,17 @@
|
|||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -101,6 +101,8 @@
|
|||
pmc {
|
||||
compatible = "nvidia,tegra114-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 261>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
iommu {
|
||||
|
|
|
@ -447,6 +447,19 @@
|
|||
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
|
||||
"nvidia,tegra-audio-wm9712";
|
||||
|
|
|
@ -451,6 +451,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
|
|
|
@ -447,6 +447,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
|
@ -595,6 +595,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
|
@ -471,6 +471,19 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
|
|
|
@ -330,6 +330,19 @@
|
|||
bus-width = <4>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio 191 1>; /* gpio PX7, active low */
|
||||
|
|
|
@ -531,6 +531,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -520,6 +520,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
|
|
|
@ -418,6 +418,8 @@
|
|||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller@7000f000 {
|
||||
|
|
|
@ -268,6 +268,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -322,6 +322,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -427,6 +427,8 @@
|
|||
pmc {
|
||||
compatible = "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 218>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller {
|
||||
|
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
* http://www.ti.com/lit/ds/symlink/tps65070.pdf
|
||||
*/
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps6507x";
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "VDCDC1";
|
||||
};
|
||||
|
||||
vdcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "VDCDC2";
|
||||
};
|
||||
|
||||
vdcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "VDCDC3";
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "LDO1";
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "LDO2";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
|
@ -0,0 +1,95 @@
|
|||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLOCK is not set
|
||||
CONFIG_ARCH_SHMOBILE=y
|
||||
CONFIG_ARCH_R8A73A4=y
|
||||
CONFIG_MACH_APE6EVM=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_CPU_BPREDICT_DISABLE=y
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
||||
CONFIG_NR_CPUS=8
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
# CONFIG_HW_PERF_EVENTS is not set
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FW_LOADER_USER_HELPER is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_SERIAL_NONSTANDARD=y
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=12
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
CONFIG_GPIO_SH_PFC=y
|
||||
CONFIG_GPIOLIB=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_RCAR_THERMAL=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC7=y
|
||||
CONFIG_LIBCRC32C=y
|
|
@ -20,15 +20,19 @@ CONFIG_ARCH_R8A7740=y
|
|||
CONFIG_MACH_ARMADILLO800EVA=y
|
||||
# CONFIG_SH_TIMER_TMU is not set
|
||||
CONFIG_ARM_THUMB=y
|
||||
CONFIG_CPU_BPREDICT_DISABLE=y
|
||||
CONFIG_CACHE_L2X0=y
|
||||
CONFIG_ARM_ERRATA_430973=y
|
||||
CONFIG_ARM_ERRATA_458693=y
|
||||
CONFIG_ARM_ERRATA_460075=y
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_ARM_ERRATA_720789=y
|
||||
CONFIG_PL310_ERRATA_727915=y
|
||||
CONFIG_ARM_ERRATA_743622=y
|
||||
CONFIG_ARM_ERRATA_751472=y
|
||||
CONFIG_PL310_ERRATA_753970=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_PL310_ERRATA_769419=y
|
||||
CONFIG_ARM_ERRATA_775420=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_FORCE_MAX_ZONEORDER=13
|
||||
|
@ -37,6 +41,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
|
|||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
|
@ -88,6 +93,7 @@ CONFIG_I2C=y
|
|||
CONFIG_I2C_GPIO=y
|
||||
CONFIG_I2C_SH_MOBILE=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
|
|
|
@ -59,10 +59,13 @@ CONFIG_DEVTMPFS_MOUNT=y
|
|||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_TTY_PRINTK=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_BCM2835=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_BCM2835=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BCM2835=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
|
@ -108,9 +111,5 @@ CONFIG_TEST_KSTRTOX=y
|
|||
CONFIG_STRICT_DEVMEM=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARM is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
|
|
|
@ -33,7 +33,6 @@ CONFIG_NO_HZ=y
|
|||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_HIGHMEM=y
|
||||
|
@ -86,7 +85,6 @@ CONFIG_I2C_SH_MOBILE=y
|
|||
CONFIG_GPIO_PCF857X=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_DUMMY=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SH_MOBILE_LCDC=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
|
@ -18,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_ARCH_LPC32XX=y
|
||||
CONFIG_GPIO_PCA953X=y
|
||||
CONFIG_KEYBOARD_GPIO_POLLED=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
|
@ -48,6 +48,8 @@ CONFIG_IPV6=y
|
|||
CONFIG_IPV6_PRIVACY=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
|
@ -55,7 +57,6 @@ CONFIG_MTD_CHAR=y
|
|||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_MUSEUM_IDS=y
|
||||
CONFIG_MTD_NAND_SLC_LPC32XX=y
|
||||
CONFIG_MTD_NAND_MLC_LPC32XX=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
|
@ -70,7 +71,6 @@ CONFIG_BLK_DEV_SD=y
|
|||
CONFIG_NETDEVICES=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
|
@ -84,7 +84,6 @@ CONFIG_LPC_ENET=y
|
|||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
|
||||
|
@ -108,6 +107,19 @@ CONFIG_I2C_PNX=y
|
|||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_EM=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
CONFIG_GPIO_MAX7300=y
|
||||
CONFIG_GPIO_MAX732X=y
|
||||
CONFIG_GPIO_PCF857X=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_GPIO_ADP5588=y
|
||||
CONFIG_GPIO_ADNP=y
|
||||
CONFIG_GPIO_MAX7301=y
|
||||
CONFIG_GPIO_MCP23S08=y
|
||||
CONFIG_GPIO_MC33880=y
|
||||
CONFIG_GPIO_74X164=y
|
||||
CONFIG_SENSORS_DS620=y
|
||||
CONFIG_SENSORS_MAX6639=y
|
||||
CONFIG_WATCHDOG=y
|
||||
|
@ -144,6 +156,7 @@ CONFIG_USB_G_SERIAL=m
|
|||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_PCA9532=y
|
||||
|
|
|
@ -75,6 +75,7 @@ CONFIG_I2C=y
|
|||
CONFIG_I2C_SH_MOBILE=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_MFD_SUPPORT is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_SH_MOBILE_LCDC=y
|
||||
|
@ -94,6 +95,9 @@ CONFIG_USB_RENESAS_USBHS=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_RENESAS_USBHS_UDC=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHI=y
|
||||
CONFIG_MMC_SH_MMCIF=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_SH_DMAE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
|
|
|
@ -49,6 +49,10 @@ CONFIG_DEVTMPFS_MOUNT=y
|
|||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_ATA_SFF=y
|
||||
CONFIG_ATA_BMDMA=y
|
||||
CONFIG_SATA_RCAR=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
|
@ -75,6 +79,7 @@ CONFIG_I2C_RCAR=y
|
|||
CONFIG_SPI=y
|
||||
CONFIG_SPI_SH_HSPI=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_RCAR=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_RCAR_THERMAL=y
|
||||
|
@ -88,6 +93,9 @@ CONFIG_USB_OHCI_HCD=y
|
|||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_UIO=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
|
|
|
@ -75,7 +75,7 @@ CONFIG_REALTEK_PHY=y
|
|||
CONFIG_MICREL_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=m
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
|
@ -99,6 +99,8 @@ CONFIG_SPI_MXS=y
|
|||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_STMP3XXX_RTC_WATCHDOG=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_FB=y
|
||||
|
@ -123,6 +125,7 @@ CONFIG_USB_STORAGE=y
|
|||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_MXS_PHY=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_MXS=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
|
|
|
@ -0,0 +1,181 @@
|
|||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SOC_SAM_V7=y
|
||||
CONFIG_SOC_SAMA5D3=y
|
||||
CONFIG_MACH_SAMA5_DT=y
|
||||
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_UACCESS_WITH_MEMCPY=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_VFP=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_ADVANCED_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
CONFIG_IPV6_SIT_6RD=y
|
||||
CONFIG_CAN=y
|
||||
CONFIG_CAN_AT91=y
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_MAC80211_LEDS=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ATMEL=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=4
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_ATMEL_TCLIB=y
|
||||
CONFIG_ATMEL_SSC=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MACB=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_MICREL_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_QT1070=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_LEGACY_PTY_COUNT=4
|
||||
CONFIG_SERIAL_ATMEL=y
|
||||
CONFIG_SERIAL_ATMEL_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_AT91=y
|
||||
CONFIG_I2C_GPIO=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_ATMEL=y
|
||||
CONFIG_SPI_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_SSB=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
# CONFIG_HID_GENERIC is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_AT91=y
|
||||
CONFIG_USB_MASS_STORAGE=m
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_ATMELMCI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_AT91RM9200=y
|
||||
CONFIG_DMADEVICES=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_IIO=y
|
||||
CONFIG_AT91_ADC=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_SUMMARY=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_850=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_USER_API_HASH=m
|
||||
CONFIG_CRYPTO_USER_API_SKCIPHER=m
|
||||
CONFIG_CRYPTO_DEV_ATMEL_AES=y
|
||||
CONFIG_CRYPTO_DEV_ATMEL_TDES=y
|
||||
CONFIG_CRYPTO_DEV_ATMEL_SHA=y
|
||||
CONFIG_CRC_CCITT=m
|
||||
CONFIG_CRC_ITU_T=m
|
|
@ -1,4 +1,3 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
|
@ -20,15 +19,14 @@ CONFIG_MODULE_UNLOAD=y
|
|||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_TEGRA=y
|
||||
CONFIG_GPIO_PCA953X=y
|
||||
CONFIG_ARCH_TEGRA_2x_SOC=y
|
||||
CONFIG_ARCH_TEGRA_3x_SOC=y
|
||||
CONFIG_ARCH_TEGRA_114_SOC=y
|
||||
CONFIG_TEGRA_PCI=y
|
||||
CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
|
||||
CONFIG_TEGRA_EMC_SCALING_ENABLE=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_PREEMPT=y
|
||||
|
@ -37,8 +35,8 @@ CONFIG_AEABI=y
|
|||
CONFIG_HIGHMEM=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
|
@ -108,6 +106,7 @@ CONFIG_RT2X00=y
|
|||
CONFIG_RT2800USB=m
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_TEGRA=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_MPU3050=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
|
@ -117,7 +116,6 @@ CONFIG_SERIAL_8250_CONSOLE=y
|
|||
CONFIG_SERIAL_TEGRA=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_I2C_COMPAT is not set
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PINCTRL=y
|
||||
|
@ -126,6 +124,7 @@ CONFIG_SPI=y
|
|||
CONFIG_SPI_TEGRA20_SFLASH=y
|
||||
CONFIG_SPI_TEGRA20_SLINK=y
|
||||
CONFIG_GPIO_PCA953X_IRQ=y
|
||||
CONFIG_GPIO_PALMAS=y
|
||||
CONFIG_GPIO_TPS6586X=y
|
||||
CONFIG_GPIO_TPS65910=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
|
@ -136,12 +135,17 @@ CONFIG_SENSORS_LM90=y
|
|||
CONFIG_MFD_TPS6586X=y
|
||||
CONFIG_MFD_TPS65910=y
|
||||
CONFIG_MFD_MAX8907=y
|
||||
CONFIG_MFD_TPS65090=y
|
||||
CONFIG_MFD_PALMAS=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_MAX8907=y
|
||||
CONFIG_REGULATOR_PALMAS=y
|
||||
CONFIG_REGULATOR_TPS51632=y
|
||||
CONFIG_REGULATOR_TPS62360=y
|
||||
CONFIG_REGULATOR_TPS65090=y
|
||||
CONFIG_REGULATOR_TPS6586X=y
|
||||
CONFIG_REGULATOR_TPS65910=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
|
@ -187,10 +191,8 @@ CONFIG_LEDS_GPIO=y
|
|||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_INTF_SYSFS=y
|
||||
CONFIG_RTC_INTF_PROC=y
|
||||
CONFIG_RTC_INTF_DEV=y
|
||||
CONFIG_RTC_DRV_MAX8907=y
|
||||
CONFIG_RTC_DRV_PALMAS=y
|
||||
CONFIG_RTC_DRV_TPS6586X=y
|
||||
CONFIG_RTC_DRV_TPS65910=y
|
||||
CONFIG_RTC_DRV_EM3027=y
|
||||
|
|
|
@ -5,7 +5,6 @@ CONFIG_BLK_DEV_INITRD=y
|
|||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_ARCH_U8500=y
|
||||
CONFIG_MACH_HREFV60=y
|
||||
|
@ -90,6 +89,8 @@ CONFIG_LEDS_CLASS=y
|
|||
CONFIG_LEDS_LM3530=y
|
||||
CONFIG_LEDS_LP5521=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_AB8500=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
|
@ -103,6 +104,7 @@ CONFIG_EXT2_FS_XATTR=y
|
|||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT2_FS_SECURITY=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
|
|
|
@ -6,6 +6,10 @@ config HAVE_AT91_DBGU0
|
|||
config HAVE_AT91_DBGU1
|
||||
bool
|
||||
|
||||
config AT91_PMC_UNIT
|
||||
bool
|
||||
default !ARCH_AT91X40
|
||||
|
||||
config AT91_SAM9_ALT_RESET
|
||||
bool
|
||||
default !ARCH_AT91X40
|
||||
|
@ -14,17 +18,59 @@ config AT91_SAM9G45_RESET
|
|||
bool
|
||||
default !ARCH_AT91X40
|
||||
|
||||
config AT91_SAM9_TIME
|
||||
bool
|
||||
|
||||
config SOC_AT91SAM9
|
||||
bool
|
||||
select AT91_SAM9_TIME
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select SPARSE_IRQ
|
||||
|
||||
config SOC_SAMA5
|
||||
bool
|
||||
select AT91_SAM9_TIME
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select SPARSE_IRQ
|
||||
|
||||
menu "Atmel AT91 System-on-Chip"
|
||||
|
||||
choice
|
||||
|
||||
prompt "Core type"
|
||||
|
||||
config SOC_SAM_V4_V5
|
||||
bool "ARM7/ARM9"
|
||||
help
|
||||
Select this if you are using one of Atmel's AT91SAM9, AT91RM9200
|
||||
or AT91X40 SoC.
|
||||
|
||||
config SOC_SAM_V7
|
||||
bool "Cortex A5"
|
||||
help
|
||||
Select this if you are using one of Atmel's SAMA5D3 SoC.
|
||||
|
||||
endchoice
|
||||
|
||||
comment "Atmel AT91 Processor"
|
||||
|
||||
if SOC_SAM_V7
|
||||
config SOC_SAMA5D3
|
||||
bool "SAMA5D3 family"
|
||||
depends on SOC_SAM_V7
|
||||
select SOC_SAMA5
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_DBGU1
|
||||
help
|
||||
Select this if you are using one of Atmel's SAMA5D3 family SoC.
|
||||
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
|
||||
endif
|
||||
|
||||
if SOC_SAM_V4_V5
|
||||
config SOC_AT91RM9200
|
||||
bool "AT91RM9200"
|
||||
select CPU_ARM920T
|
||||
|
@ -90,13 +136,10 @@ config SOC_AT91SAM9N12
|
|||
help
|
||||
Select this if you are using Atmel's AT91SAM9N12 SoC.
|
||||
|
||||
config AT91_PMC_UNIT
|
||||
bool
|
||||
default !ARCH_AT91X40
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
source arch/arm/mach-at91/Kconfig.non_dt
|
||||
endif # SOC_SAM_V4_V5
|
||||
|
||||
comment "Generic Board Type"
|
||||
|
||||
|
@ -116,6 +159,14 @@ config MACH_AT91SAM9_DT
|
|||
Select this if you want to experiment device-tree with
|
||||
an Atmel Evaluation Kit.
|
||||
|
||||
config MACH_SAMA5_DT
|
||||
bool "Atmel SAMA5 Evaluation Kits with device-tree support"
|
||||
depends on SOC_SAMA5
|
||||
select USE_OF
|
||||
help
|
||||
Select this if you want to experiment device-tree with
|
||||
an Atmel Evaluation Kit.
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
comment "AT91 Feature Selections"
|
||||
|
|
|
@ -10,7 +10,8 @@ obj- :=
|
|||
obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
|
||||
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o
|
||||
obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
|
||||
|
||||
# CPU-specific support
|
||||
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o
|
||||
|
@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o
|
|||
obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
|
||||
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
|
||||
|
||||
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
|
||||
|
@ -90,6 +92,9 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
|
|||
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
|
||||
obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
|
||||
|
||||
# SAMA5 board with device-tree
|
||||
obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
|
||||
|
||||
# AT91X40 board-specific support
|
||||
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
|
||||
|
||||
|
|
|
@ -385,7 +385,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0 /* Advanced Interrupt Controller (IRQ6) */
|
||||
};
|
||||
|
||||
AT91_SOC_START(rm9200)
|
||||
AT91_SOC_START(at91rm9200)
|
||||
.map_io = at91rm9200_map_io,
|
||||
.default_irq_priority = at91rm9200_default_irq_priority,
|
||||
.ioremap_registers = at91rm9200_ioremap_registers,
|
||||
|
|
|
@ -397,7 +397,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
AT91_SOC_START(sam9260)
|
||||
AT91_SOC_START(at91sam9260)
|
||||
.map_io = at91sam9260_map_io,
|
||||
.default_irq_priority = at91sam9260_default_irq_priority,
|
||||
.ioremap_registers = at91sam9260_ioremap_registers,
|
||||
|
|
|
@ -337,7 +337,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
AT91_SOC_START(sam9261)
|
||||
AT91_SOC_START(at91sam9261)
|
||||
.map_io = at91sam9261_map_io,
|
||||
.default_irq_priority = at91sam9261_default_irq_priority,
|
||||
.ioremap_registers = at91sam9261_ioremap_registers,
|
||||
|
|
|
@ -374,7 +374,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller (IRQ1) */
|
||||
};
|
||||
|
||||
AT91_SOC_START(sam9263)
|
||||
AT91_SOC_START(at91sam9263)
|
||||
.map_io = at91sam9263_map_io,
|
||||
.default_irq_priority = at91sam9263_default_irq_priority,
|
||||
.ioremap_registers = at91sam9263_ioremap_registers,
|
||||
|
|
|
@ -420,7 +420,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller (IRQ0) */
|
||||
};
|
||||
|
||||
AT91_SOC_START(sam9g45)
|
||||
AT91_SOC_START(at91sam9g45)
|
||||
.map_io = at91sam9g45_map_io,
|
||||
.default_irq_priority = at91sam9g45_default_irq_priority,
|
||||
.ioremap_registers = at91sam9g45_ioremap_registers,
|
||||
|
|
|
@ -228,7 +228,7 @@ void __init at91sam9n12_initialize(void)
|
|||
at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
|
||||
}
|
||||
|
||||
AT91_SOC_START(sam9n12)
|
||||
AT91_SOC_START(at91sam9n12)
|
||||
.map_io = at91sam9n12_map_io,
|
||||
.register_clocks = at91sam9n12_register_clocks,
|
||||
.init = at91sam9n12_initialize,
|
||||
|
|
|
@ -340,7 +340,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
AT91_SOC_START(sam9rl)
|
||||
AT91_SOC_START(at91sam9rl)
|
||||
.map_io = at91sam9rl_map_io,
|
||||
.default_irq_priority = at91sam9rl_default_irq_priority,
|
||||
.ioremap_registers = at91sam9rl_ioremap_registers,
|
||||
|
|
|
@ -322,7 +322,7 @@ static void __init at91sam9x5_map_io(void)
|
|||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
AT91_SOC_START(sam9x5)
|
||||
AT91_SOC_START(at91sam9x5)
|
||||
.map_io = at91sam9x5_map_io,
|
||||
.register_clocks = at91sam9x5_register_clocks,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Setup code for SAMA5 Evaluation Kits with Device Tree support
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "at91_aic.h"
|
||||
#include "generic.h"
|
||||
|
||||
|
||||
static const struct of_device_id irq_of_match[] __initconst = {
|
||||
|
||||
{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
|
||||
{ /*sentinel*/ }
|
||||
};
|
||||
|
||||
static void __init at91_dt_init_irq(void)
|
||||
{
|
||||
of_irq_init(irq_of_match);
|
||||
}
|
||||
|
||||
static int ksz9021rn_phy_fixup(struct phy_device *phy)
|
||||
{
|
||||
int value;
|
||||
|
||||
#define GMII_RCCPSR 260
|
||||
#define GMII_RRDPSR 261
|
||||
#define GMII_ERCR 11
|
||||
#define GMII_ERDWR 12
|
||||
|
||||
/* Set delay values */
|
||||
value = GMII_RCCPSR | 0x8000;
|
||||
phy_write(phy, GMII_ERCR, value);
|
||||
value = 0xF2F4;
|
||||
phy_write(phy, GMII_ERDWR, value);
|
||||
value = GMII_RRDPSR | 0x8000;
|
||||
phy_write(phy, GMII_ERCR, value);
|
||||
value = 0x2222;
|
||||
phy_write(phy, GMII_ERDWR, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init sama5_dt_device_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("atmel,sama5d3xcm"))
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
|
||||
ksz9021rn_phy_fixup);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *sama5_dt_board_compat[] __initdata = {
|
||||
"atmel,sama5",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
|
||||
/* Maintainer: Atmel */
|
||||
.init_time = at91sam926x_pit_init,
|
||||
.map_io = at91_map_io,
|
||||
.handle_irq = at91_aic5_handle_irq,
|
||||
.init_early = at91_dt_initialize,
|
||||
.init_irq = at91_dt_init_irq,
|
||||
.init_machine = sama5_dt_device_init,
|
||||
.dt_compat = sama5_dt_board_compat,
|
||||
MACHINE_END
|
|
@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
|||
*/
|
||||
#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_sama5d3())
|
||||
|
||||
#define cpu_has_1056M_plla() (cpu_is_sama5d3())
|
||||
|
||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|
@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
|||
|| cpu_is_at91sam9n12()))
|
||||
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_sama5d3())
|
||||
|
||||
/* USB host HS & FS */
|
||||
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
||||
|
@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
|||
/* USB device FS only */
|
||||
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_sama5d3()))
|
||||
|
||||
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|| cpu_is_at91sam9n12() \
|
||||
|| cpu_is_sama5d3())
|
||||
|
||||
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|| cpu_is_at91sam9n12() \
|
||||
|| cpu_is_sama5d3())
|
||||
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|| cpu_is_at91sam9n12() \
|
||||
|| cpu_is_sama5d3())
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
@ -210,10 +218,26 @@ struct clk mck = {
|
|||
|
||||
static void pmc_periph_mode(struct clk *clk, int is_on)
|
||||
{
|
||||
if (is_on)
|
||||
at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
|
||||
else
|
||||
at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
|
||||
u32 regval = 0;
|
||||
|
||||
/*
|
||||
* With sama5d3 devices, we are managing clock division so we have to
|
||||
* use the Peripheral Control Register introduced from at91sam9x5
|
||||
* devices.
|
||||
*/
|
||||
if (cpu_is_sama5d3()) {
|
||||
regval |= AT91_PMC_PCR_CMD; /* write command */
|
||||
regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
|
||||
regval |= AT91_PMC_PCR_DIV(clk->div);
|
||||
if (is_on)
|
||||
regval |= AT91_PMC_PCR_EN; /* enable clock */
|
||||
at91_pmc_write(AT91_PMC_PCR, regval);
|
||||
} else {
|
||||
if (is_on)
|
||||
at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
|
||||
else
|
||||
at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
|
||||
}
|
||||
}
|
||||
|
||||
static struct clk __init *at91_css_to_clk(unsigned long css)
|
||||
|
@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk)
|
|||
|
||||
static int at91_clk_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
u32 scsr, pcsr, uckr = 0, sr;
|
||||
u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
|
||||
struct clk *clk;
|
||||
|
||||
scsr = at91_pmc_read(AT91_PMC_SCSR);
|
||||
pcsr = at91_pmc_read(AT91_PMC_PCSR);
|
||||
if (cpu_is_sama5d3())
|
||||
pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
|
||||
sr = at91_pmc_read(AT91_PMC_SR);
|
||||
seq_printf(s, "SCSR = %8x\n", scsr);
|
||||
seq_printf(s, "PCSR = %8x\n", pcsr);
|
||||
if (cpu_is_sama5d3())
|
||||
seq_printf(s, "PCSR1 = %8x\n", pcsr1);
|
||||
seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
|
||||
seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
|
||||
seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
|
||||
|
@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused)
|
|||
list_for_each_entry(clk, &clocks, node) {
|
||||
char *state;
|
||||
|
||||
if (clk->mode == pmc_sys_mode)
|
||||
if (clk->mode == pmc_sys_mode) {
|
||||
state = (scsr & clk->pmc_mask) ? "on" : "off";
|
||||
else if (clk->mode == pmc_periph_mode)
|
||||
state = (pcsr & clk->pmc_mask) ? "on" : "off";
|
||||
else if (clk->mode == pmc_uckr_mode)
|
||||
state = (uckr & clk->pmc_mask) ? "on" : "off";
|
||||
else if (clk->pmc_mask)
|
||||
state = (sr & clk->pmc_mask) ? "on" : "off";
|
||||
else if (clk == &clk32k || clk == &main_clk)
|
||||
state = "on";
|
||||
else
|
||||
state = "";
|
||||
} else if (clk->mode == pmc_periph_mode) {
|
||||
if (cpu_is_sama5d3()) {
|
||||
u32 pmc_mask = 1 << (clk->pid % 32);
|
||||
|
||||
seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
|
||||
if (clk->pid > 31)
|
||||
state = (pcsr1 & pmc_mask) ? "on" : "off";
|
||||
else
|
||||
state = (pcsr & pmc_mask) ? "on" : "off";
|
||||
} else {
|
||||
state = (pcsr & clk->pmc_mask) ? "on" : "off";
|
||||
}
|
||||
} else if (clk->mode == pmc_uckr_mode) {
|
||||
state = (uckr & clk->pmc_mask) ? "on" : "off";
|
||||
} else if (clk->pmc_mask) {
|
||||
state = (sr & clk->pmc_mask) ? "on" : "off";
|
||||
} else if (clk == &clk32k || clk == &main_clk) {
|
||||
state = "on";
|
||||
} else {
|
||||
state = "";
|
||||
}
|
||||
|
||||
seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
|
||||
clk->name, clk->users, state, clk_get_rate(clk),
|
||||
clk->parent ? clk->parent->name : "");
|
||||
}
|
||||
|
@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk)
|
|||
if (clk_is_peripheral(clk)) {
|
||||
if (!clk->parent)
|
||||
clk->parent = &mck;
|
||||
if (cpu_is_sama5d3())
|
||||
clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
|
||||
1 << clk->div);
|
||||
clk->mode = pmc_periph_mode;
|
||||
}
|
||||
else if (clk_is_sys(clk)) {
|
||||
|
@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
|
|||
unsigned mul, div;
|
||||
|
||||
div = reg & 0xff;
|
||||
mul = (reg >> 16) & 0x7ff;
|
||||
if (cpu_is_sama5d3())
|
||||
mul = AT91_PMC3_MUL_GET(reg);
|
||||
else
|
||||
mul = AT91_PMC_MUL_GET(reg);
|
||||
|
||||
if (div && mul) {
|
||||
freq /= div;
|
||||
freq *= mul + 1;
|
||||
|
@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock)
|
|||
|
||||
/* report if PLLA is more than mildly overclocked */
|
||||
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
|
||||
if (cpu_has_300M_plla()) {
|
||||
if (plla.rate_hz > 300000000)
|
||||
if (cpu_has_1056M_plla()) {
|
||||
if (plla.rate_hz > 1056000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_800M_plla()) {
|
||||
if (plla.rate_hz > 800000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_300M_plla()) {
|
||||
if (plla.rate_hz > 300000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_240M_plla()) {
|
||||
if (plla.rate_hz > 240000000)
|
||||
pll_overclock = true;
|
||||
|
@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
static int __init at91_clock_reset(void)
|
||||
{
|
||||
unsigned long pcdr = 0;
|
||||
unsigned long pcdr1 = 0;
|
||||
unsigned long scdr = 0;
|
||||
struct clk *clk;
|
||||
|
||||
|
@ -879,8 +928,17 @@ static int __init at91_clock_reset(void)
|
|||
if (clk->users > 0)
|
||||
continue;
|
||||
|
||||
if (clk->mode == pmc_periph_mode)
|
||||
pcdr |= clk->pmc_mask;
|
||||
if (clk->mode == pmc_periph_mode) {
|
||||
if (cpu_is_sama5d3()) {
|
||||
u32 pmc_mask = 1 << (clk->pid % 32);
|
||||
|
||||
if (clk->pid > 31)
|
||||
pcdr1 |= pmc_mask;
|
||||
else
|
||||
pcdr |= pmc_mask;
|
||||
} else
|
||||
pcdr |= clk->pmc_mask;
|
||||
}
|
||||
|
||||
if (clk->mode == pmc_sys_mode)
|
||||
scdr |= clk->pmc_mask;
|
||||
|
@ -888,8 +946,9 @@ static int __init at91_clock_reset(void)
|
|||
pr_debug("Clocks: disable unused %s\n", clk->name);
|
||||
}
|
||||
|
||||
at91_pmc_write(AT91_PMC_PCDR, pcdr);
|
||||
at91_pmc_write(AT91_PMC_SCDR, scdr);
|
||||
if (cpu_is_sama5d3())
|
||||
at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -20,7 +20,9 @@ struct clk {
|
|||
const char *name; /* unique clock name */
|
||||
struct clk_lookup cl;
|
||||
unsigned long rate_hz;
|
||||
unsigned div; /* parent clock divider */
|
||||
struct clk *parent;
|
||||
unsigned pid; /* peripheral ID */
|
||||
u32 pmc_mask;
|
||||
void (*mode)(struct clk *, int);
|
||||
unsigned id:3; /* PCK0..4, or 32k/main/a/b */
|
||||
|
|
|
@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base;
|
|||
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
||||
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
|
||||
#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff)
|
||||
#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
|
||||
#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f)
|
||||
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
|
||||
#define AT91_PMC_USBDIV_1 (0 << 28)
|
||||
#define AT91_PMC_USBDIV_2 (1 << 28)
|
||||
|
@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base;
|
|||
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||
|
||||
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */
|
||||
#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
|
||||
#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
|
||||
#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
|
||||
|
||||
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
|
||||
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
|
||||
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
|
||||
#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
|
||||
#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV)
|
||||
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
|
||||
#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */
|
||||
#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
|
||||
#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */
|
||||
#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */
|
||||
#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */
|
||||
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -36,6 +36,8 @@
|
|||
#define ARCH_ID_AT91M40807 0x14080745
|
||||
#define ARCH_ID_AT91R40008 0x44000840
|
||||
|
||||
#define ARCH_ID_SAMA5D3 0x8A5C07C0
|
||||
|
||||
#define ARCH_EXID_AT91SAM9M11 0x00000001
|
||||
#define ARCH_EXID_AT91SAM9M10 0x00000002
|
||||
#define ARCH_EXID_AT91SAM9G46 0x00000003
|
||||
|
@ -47,6 +49,11 @@
|
|||
#define ARCH_EXID_AT91SAM9G25 0x00000003
|
||||
#define ARCH_EXID_AT91SAM9X25 0x00000004
|
||||
|
||||
#define ARCH_EXID_SAMA5D31 0x00444300
|
||||
#define ARCH_EXID_SAMA5D33 0x00414300
|
||||
#define ARCH_EXID_SAMA5D34 0x00414301
|
||||
#define ARCH_EXID_SAMA5D35 0x00584300
|
||||
|
||||
#define ARCH_FAMILY_AT91X92 0x09200000
|
||||
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
||||
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
||||
|
@ -75,6 +82,9 @@ enum at91_soc_type {
|
|||
/* SAM9N12 */
|
||||
AT91_SOC_SAM9N12,
|
||||
|
||||
/* SAMA5D3 */
|
||||
AT91_SOC_SAMA5D3,
|
||||
|
||||
/* Unknown type */
|
||||
AT91_SOC_NONE
|
||||
};
|
||||
|
@ -93,6 +103,10 @@ enum at91_soc_subtype {
|
|||
AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
|
||||
AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
|
||||
|
||||
/* SAMA5D3 */
|
||||
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
|
||||
AT91_SOC_SAMA5D35,
|
||||
|
||||
/* Unknown subtype */
|
||||
AT91_SOC_SUBTYPE_NONE
|
||||
};
|
||||
|
@ -187,6 +201,12 @@ static inline int at91_soc_is_detected(void)
|
|||
#define cpu_is_at91sam9n12() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_SAMA5D3
|
||||
#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
|
||||
#else
|
||||
#define cpu_is_sama5d3() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
* definitions may reduce clutter in common drivers.
|
||||
|
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Chip-specific header file for the SAMA5D3 family
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on SAMA5D3 datasheet.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef SAMA5D3_H
|
||||
#define SAMA5D3_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
|
||||
#define AT91_ID_PIT 3 /* PIT */
|
||||
#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */
|
||||
#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */
|
||||
#define SAMA5D3_ID_PIOA 6 /* PIOA */
|
||||
#define SAMA5D3_ID_PIOB 7 /* PIOB */
|
||||
#define SAMA5D3_ID_PIOC 8 /* PIOC */
|
||||
#define SAMA5D3_ID_PIOD 9 /* PIOD */
|
||||
#define SAMA5D3_ID_PIOE 10 /* PIOE */
|
||||
#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */
|
||||
#define SAMA5D3_ID_USART0 12 /* USART0 */
|
||||
#define SAMA5D3_ID_USART1 13 /* USART1 */
|
||||
#define SAMA5D3_ID_USART2 14 /* USART2 */
|
||||
#define SAMA5D3_ID_USART3 15 /* USART3 */
|
||||
#define SAMA5D3_ID_UART0 16 /* UART 0 */
|
||||
#define SAMA5D3_ID_UART1 17 /* UART 1 */
|
||||
#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */
|
||||
#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */
|
||||
#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */
|
||||
#define SAMA5D3_ID_HSMCI0 21 /* MCI */
|
||||
#define SAMA5D3_ID_HSMCI1 22 /* MCI */
|
||||
#define SAMA5D3_ID_HSMCI2 23 /* MCI */
|
||||
#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */
|
||||
#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */
|
||||
#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */
|
||||
#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */
|
||||
#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */
|
||||
#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */
|
||||
#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */
|
||||
#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */
|
||||
#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */
|
||||
#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */
|
||||
#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */
|
||||
#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */
|
||||
#define SAMA5D3_ID_LCDC 36 /* LCD Controller */
|
||||
#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */
|
||||
#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */
|
||||
#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */
|
||||
#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */
|
||||
#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */
|
||||
#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */
|
||||
#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */
|
||||
#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */
|
||||
#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */
|
||||
#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
|
||||
|
||||
/*
|
||||
* Internal Memory
|
||||
*/
|
||||
#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */
|
||||
|
||||
#endif
|
|
@ -0,0 +1,377 @@
|
|||
/*
|
||||
* Chip-specific setup code for the SAMA5D3 family
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/sama5d3.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
#include "sam9_smc.h"
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Clocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The peripheral clocks.
|
||||
*/
|
||||
|
||||
static struct clk pioA_clk = {
|
||||
.name = "pioA_clk",
|
||||
.pid = SAMA5D3_ID_PIOA,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioB_clk = {
|
||||
.name = "pioB_clk",
|
||||
.pid = SAMA5D3_ID_PIOB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioC_clk = {
|
||||
.name = "pioC_clk",
|
||||
.pid = SAMA5D3_ID_PIOC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioD_clk = {
|
||||
.name = "pioD_clk",
|
||||
.pid = SAMA5D3_ID_PIOD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioE_clk = {
|
||||
.name = "pioE_clk",
|
||||
.pid = SAMA5D3_ID_PIOE,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pid = SAMA5D3_ID_USART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pid = SAMA5D3_ID_USART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pid = SAMA5D3_ID_USART2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk usart3_clk = {
|
||||
.name = "usart3_clk",
|
||||
.pid = SAMA5D3_ID_USART3,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0_clk",
|
||||
.pid = SAMA5D3_ID_UART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1_clk",
|
||||
.pid = SAMA5D3_ID_UART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk twi0_clk = {
|
||||
.name = "twi0_clk",
|
||||
.pid = SAMA5D3_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pid = SAMA5D3_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk twi2_clk = {
|
||||
.name = "twi2_clk",
|
||||
.pid = SAMA5D3_ID_TWI2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk mmc0_clk = {
|
||||
.name = "mci0_clk",
|
||||
.pid = SAMA5D3_ID_HSMCI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc1_clk = {
|
||||
.name = "mci1_clk",
|
||||
.pid = SAMA5D3_ID_HSMCI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc2_clk = {
|
||||
.name = "mci2_clk",
|
||||
.pid = SAMA5D3_ID_HSMCI2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pid = SAMA5D3_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pid = SAMA5D3_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tcb0_clk = {
|
||||
.name = "tcb0_clk",
|
||||
.pid = SAMA5D3_ID_TC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk tcb1_clk = {
|
||||
.name = "tcb1_clk",
|
||||
.pid = SAMA5D3_ID_TC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk adc_clk = {
|
||||
.name = "adc_clk",
|
||||
.pid = SAMA5D3_ID_ADC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk adc_op_clk = {
|
||||
.name = "adc_op_clk",
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.rate_hz = 5000000,
|
||||
};
|
||||
static struct clk dma0_clk = {
|
||||
.name = "dma0_clk",
|
||||
.pid = SAMA5D3_ID_DMA0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma1_clk = {
|
||||
.name = "dma1_clk",
|
||||
.pid = SAMA5D3_ID_DMA1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uhphs_clk = {
|
||||
.name = "uhphs",
|
||||
.pid = SAMA5D3_ID_UHPHS,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udphs_clk = {
|
||||
.name = "udphs_clk",
|
||||
.pid = SAMA5D3_ID_UDPHS,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* gmac only for sama5d33, sama5d34, sama5d35 */
|
||||
static struct clk macb0_clk = {
|
||||
.name = "macb0_clk",
|
||||
.pid = SAMA5D3_ID_GMAC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* emac only for sama5d31, sama5d35 */
|
||||
static struct clk macb1_clk = {
|
||||
.name = "macb1_clk",
|
||||
.pid = SAMA5D3_ID_EMAC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* lcd only for sama5d31, sama5d33, sama5d34 */
|
||||
static struct clk lcdc_clk = {
|
||||
.name = "lcdc_clk",
|
||||
.pid = SAMA5D3_ID_LCDC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* isi only for sama5d33, sama5d35 */
|
||||
static struct clk isi_clk = {
|
||||
.name = "isi_clk",
|
||||
.pid = SAMA5D3_ID_ISI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk can0_clk = {
|
||||
.name = "can0_clk",
|
||||
.pid = SAMA5D3_ID_CAN0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk can1_clk = {
|
||||
.name = "can1_clk",
|
||||
.pid = SAMA5D3_ID_CAN1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk ssc0_clk = {
|
||||
.name = "ssc0_clk",
|
||||
.pid = SAMA5D3_ID_SSC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk ssc1_clk = {
|
||||
.name = "ssc1_clk",
|
||||
.pid = SAMA5D3_ID_SSC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
};
|
||||
static struct clk sha_clk = {
|
||||
.name = "sha_clk",
|
||||
.pid = SAMA5D3_ID_SHA,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV8,
|
||||
};
|
||||
static struct clk aes_clk = {
|
||||
.name = "aes_clk",
|
||||
.pid = SAMA5D3_ID_AES,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tdes_clk = {
|
||||
.name = "tdes_clk",
|
||||
.pid = SAMA5D3_ID_TDES,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
static struct clk *periph_clocks[] __initdata = {
|
||||
&pioA_clk,
|
||||
&pioB_clk,
|
||||
&pioC_clk,
|
||||
&pioD_clk,
|
||||
&pioE_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&usart3_clk,
|
||||
&uart0_clk,
|
||||
&uart1_clk,
|
||||
&twi0_clk,
|
||||
&twi1_clk,
|
||||
&twi2_clk,
|
||||
&mmc0_clk,
|
||||
&mmc1_clk,
|
||||
&mmc2_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&tcb0_clk,
|
||||
&tcb1_clk,
|
||||
&adc_clk,
|
||||
&adc_op_clk,
|
||||
&dma0_clk,
|
||||
&dma1_clk,
|
||||
&uhphs_clk,
|
||||
&udphs_clk,
|
||||
&macb0_clk,
|
||||
&macb1_clk,
|
||||
&lcdc_clk,
|
||||
&isi_clk,
|
||||
&can0_clk,
|
||||
&can1_clk,
|
||||
&ssc0_clk,
|
||||
&ssc1_clk,
|
||||
&sha_clk,
|
||||
&aes_clk,
|
||||
&tdes_clk,
|
||||
};
|
||||
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static struct clk pck2 = {
|
||||
.name = "pck2",
|
||||
.pmc_mask = AT91_PMC_PCK2,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 2,
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
/* lookup table for DT entries */
|
||||
CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
|
||||
CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
|
||||
CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
|
||||
CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
|
||||
CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
|
||||
CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
|
||||
CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
|
||||
CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
|
||||
};
|
||||
|
||||
static void __init sama5d3_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
|
||||
clkdev_add_table(periph_clocks_lookups,
|
||||
ARRAY_SIZE(periph_clocks_lookups));
|
||||
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
clk_register(&pck2);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9x5 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init sama5d3_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
|
||||
}
|
||||
|
||||
AT91_SOC_START(sama5d3)
|
||||
.map_io = sama5d3_map_io,
|
||||
.register_clocks = sama5d3_register_clocks,
|
||||
AT91_SOC_END
|
|
@ -151,6 +151,11 @@ static void __init soc_detect(u32 dbgu_base)
|
|||
at91_soc_initdata.type = AT91_SOC_SAM9N12;
|
||||
at91_boot_soc = at91sam9n12_soc;
|
||||
break;
|
||||
|
||||
case ARCH_ID_SAMA5D3:
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
|
||||
at91_boot_soc = sama5d3_soc;
|
||||
break;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
|
@ -206,6 +211,23 @@ static void __init soc_detect(u32 dbgu_base)
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_SAMA5D31:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D33:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D34:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const char *soc_name[] = {
|
||||
|
@ -219,6 +241,7 @@ static const char *soc_name[] = {
|
|||
[AT91_SOC_SAM9RL] = "at91sam9rl",
|
||||
[AT91_SOC_SAM9X5] = "at91sam9x5",
|
||||
[AT91_SOC_SAM9N12] = "at91sam9n12",
|
||||
[AT91_SOC_SAMA5D3] = "sama5d3",
|
||||
[AT91_SOC_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
|
@ -241,6 +264,10 @@ static const char *soc_subtype_name[] = {
|
|||
[AT91_SOC_SAM9X35] = "at91sam9x35",
|
||||
[AT91_SOC_SAM9G25] = "at91sam9g25",
|
||||
[AT91_SOC_SAM9X25] = "at91sam9x25",
|
||||
[AT91_SOC_SAMA5D31] = "sama5d31",
|
||||
[AT91_SOC_SAMA5D33] = "sama5d33",
|
||||
[AT91_SOC_SAMA5D34] = "sama5d34",
|
||||
[AT91_SOC_SAMA5D35] = "sama5d35",
|
||||
[AT91_SOC_SUBTYPE_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
|
|
|
@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc;
|
|||
extern struct at91_init_soc at91sam9rl_soc;
|
||||
extern struct at91_init_soc at91sam9x5_soc;
|
||||
extern struct at91_init_soc at91sam9n12_soc;
|
||||
extern struct at91_init_soc sama5d3_soc;
|
||||
|
||||
#define AT91_SOC_START(_name) \
|
||||
struct at91_init_soc __initdata at91##_name##_soc \
|
||||
struct at91_init_soc __initdata _name##_soc \
|
||||
__used \
|
||||
= { \
|
||||
.builtin = 1, \
|
||||
|
@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void)
|
|||
#if !defined(CONFIG_SOC_AT91SAM9N12)
|
||||
#define at91sam9n12_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SOC_SAMA5D3)
|
||||
#define sama5d3_soc at91_boot_soc
|
||||
#endif
|
||||
|
|
|
@ -246,7 +246,6 @@ static struct davinci_mmc_config da830_evm_mmc_config = {
|
|||
.wires = 8,
|
||||
.max_freq = 50000000,
|
||||
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.version = MMC_CTLR_VERSION_2,
|
||||
};
|
||||
|
||||
static inline void da830_evm_init_mmc(void)
|
||||
|
|
|
@ -802,7 +802,6 @@ static struct davinci_mmc_config da850_mmc_config = {
|
|||
.wires = 4,
|
||||
.max_freq = 50000000,
|
||||
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.version = MMC_CTLR_VERSION_2,
|
||||
};
|
||||
|
||||
static const short da850_evm_mmcsd0_pins[] __initconst = {
|
||||
|
@ -1372,7 +1371,6 @@ static struct davinci_mmc_config da850_wl12xx_mmc_config = {
|
|||
.max_freq = 25000000,
|
||||
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
|
||||
MMC_CAP_POWER_OFF_CARD,
|
||||
.version = MMC_CTLR_VERSION_2,
|
||||
};
|
||||
|
||||
static const short da850_wl12xx_pins[] __initconst = {
|
||||
|
|
|
@ -345,7 +345,6 @@ static struct davinci_mmc_config dm355evm_mmc_config = {
|
|||
.wires = 4,
|
||||
.max_freq = 50000000,
|
||||
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.version = MMC_CTLR_VERSION_1,
|
||||
};
|
||||
|
||||
/* Don't connect anything to J10 unless you're only using USB host
|
||||
|
|
|
@ -255,7 +255,6 @@ static struct davinci_mmc_config dm365evm_mmc_config = {
|
|||
.wires = 4,
|
||||
.max_freq = 50000000,
|
||||
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.version = MMC_CTLR_VERSION_2,
|
||||
};
|
||||
|
||||
static void dm365evm_emac_configure(void)
|
||||
|
|
|
@ -570,7 +570,6 @@ static struct davinci_mmc_config dm6446evm_mmc_config = {
|
|||
.get_cd = dm6444evm_mmc_get_cd,
|
||||
.get_ro = dm6444evm_mmc_get_ro,
|
||||
.wires = 4,
|
||||
.version = MMC_CTLR_VERSION_1
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata i2c_info[] = {
|
||||
|
|
|
@ -164,7 +164,6 @@ static void __init davinci_ntosd2_map_io(void)
|
|||
|
||||
static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
|
||||
.wires = 4,
|
||||
.version = MMC_CTLR_VERSION_1
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -136,7 +136,6 @@ static struct davinci_mmc_config da850_mmc_config = {
|
|||
.wires = 4,
|
||||
.max_freq = 50000000,
|
||||
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.version = MMC_CTLR_VERSION_2,
|
||||
};
|
||||
|
||||
static __init void omapl138_hawk_mmc_init(void)
|
||||
|
|
|
@ -85,7 +85,6 @@ static struct davinci_mmc_config mmc_config = {
|
|||
.wires = 4,
|
||||
.max_freq = 50000000,
|
||||
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.version = MMC_CTLR_VERSION_1,
|
||||
};
|
||||
|
||||
static const short sdio1_pins[] __initconst = {
|
||||
|
|
|
@ -35,19 +35,26 @@ static void __clk_enable(struct clk *clk)
|
|||
{
|
||||
if (clk->parent)
|
||||
__clk_enable(clk->parent);
|
||||
if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
|
||||
davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
|
||||
true, clk->flags);
|
||||
if (clk->usecount++ == 0) {
|
||||
if (clk->flags & CLK_PSC)
|
||||
davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
|
||||
true, clk->flags);
|
||||
else if (clk->clk_enable)
|
||||
clk->clk_enable(clk);
|
||||
}
|
||||
}
|
||||
|
||||
static void __clk_disable(struct clk *clk)
|
||||
{
|
||||
if (WARN_ON(clk->usecount == 0))
|
||||
return;
|
||||
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
|
||||
(clk->flags & CLK_PSC))
|
||||
davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
|
||||
false, clk->flags);
|
||||
if (--clk->usecount == 0) {
|
||||
if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
|
||||
davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
|
||||
false, clk->flags);
|
||||
else if (clk->clk_disable)
|
||||
clk->clk_disable(clk);
|
||||
}
|
||||
if (clk->parent)
|
||||
__clk_disable(clk->parent);
|
||||
}
|
||||
|
|
|
@ -104,6 +104,8 @@ struct clk {
|
|||
int (*set_rate) (struct clk *clk, unsigned long rate);
|
||||
int (*round_rate) (struct clk *clk, unsigned long rate);
|
||||
int (*reset) (struct clk *clk, bool reset);
|
||||
void (*clk_enable) (struct clk *clk);
|
||||
void (*clk_disable) (struct clk *clk);
|
||||
};
|
||||
|
||||
/* Clock flags: SoC-specific flags start at BIT(16) */
|
||||
|
|
|
@ -394,7 +394,7 @@ static struct clk_lookup da830_clks[] = {
|
|||
CLK(NULL, "tpcc", &tpcc_clk),
|
||||
CLK(NULL, "tptc0", &tptc0_clk),
|
||||
CLK(NULL, "tptc1", &tptc1_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd_clk),
|
||||
CLK("da830-mmc.0", NULL, &mmcsd_clk),
|
||||
CLK(NULL, "uart0", &uart0_clk),
|
||||
CLK(NULL, "uart1", &uart1_clk),
|
||||
CLK(NULL, "uart2", &uart2_clk),
|
||||
|
|
|
@ -383,6 +383,49 @@ static struct clk dsp_clk = {
|
|||
.flags = PSC_LRST | PSC_FORCE,
|
||||
};
|
||||
|
||||
static struct clk ehrpwm_clk = {
|
||||
.name = "ehrpwm",
|
||||
.parent = &pll0_sysclk2,
|
||||
.lpsc = DA8XX_LPSC1_PWM,
|
||||
.gpsc = 1,
|
||||
.flags = DA850_CLK_ASYNC3,
|
||||
};
|
||||
|
||||
#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
|
||||
|
||||
static void ehrpwm_tblck_enable(struct clk *clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
|
||||
val |= DA8XX_EHRPWM_TBCLKSYNC;
|
||||
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
|
||||
}
|
||||
|
||||
static void ehrpwm_tblck_disable(struct clk *clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
|
||||
val &= ~DA8XX_EHRPWM_TBCLKSYNC;
|
||||
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
|
||||
}
|
||||
|
||||
static struct clk ehrpwm_tbclk = {
|
||||
.name = "ehrpwm_tbclk",
|
||||
.parent = &ehrpwm_clk,
|
||||
.clk_enable = ehrpwm_tblck_enable,
|
||||
.clk_disable = ehrpwm_tblck_disable,
|
||||
};
|
||||
|
||||
static struct clk ecap_clk = {
|
||||
.name = "ecap",
|
||||
.parent = &pll0_sysclk2,
|
||||
.lpsc = DA8XX_LPSC1_ECAP,
|
||||
.gpsc = 1,
|
||||
.flags = DA850_CLK_ASYNC3,
|
||||
};
|
||||
|
||||
static struct clk_lookup da850_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll0", &pll0_clk),
|
||||
|
@ -420,8 +463,8 @@ static struct clk_lookup da850_clks[] = {
|
|||
CLK("davinci_emac.1", NULL, &emac_clk),
|
||||
CLK("davinci-mcasp.0", NULL, &mcasp_clk),
|
||||
CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK("da830-mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("da830-mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK(NULL, "aemif", &aemif_clk),
|
||||
CLK(NULL, "usb11", &usb11_clk),
|
||||
CLK(NULL, "usb20", &usb20_clk),
|
||||
|
@ -430,6 +473,9 @@ static struct clk_lookup da850_clks[] = {
|
|||
CLK("vpif", NULL, &vpif_clk),
|
||||
CLK("ahci", NULL, &sata_clk),
|
||||
CLK("davinci-rproc.0", NULL, &dsp_clk),
|
||||
CLK("ehrpwm", "fck", &ehrpwm_clk),
|
||||
CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
|
||||
CLK("ecap", "fck", &ecap_clk),
|
||||
CLK(NULL, NULL, NULL),
|
||||
};
|
||||
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
#define DA8XX_NUM_UARTS 3
|
||||
|
||||
void __init da8xx_uart_clk_enable(void)
|
||||
static void __init da8xx_uart_clk_enable(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < DA8XX_NUM_UARTS; i++)
|
||||
|
@ -37,9 +37,10 @@ static void __init da8xx_init_irq(void)
|
|||
of_irq_init(da8xx_irq_match);
|
||||
}
|
||||
|
||||
struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
|
||||
static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
|
||||
OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
|
||||
OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dma-contiguous.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/ahci_platform.h>
|
||||
#include <linux/clk.h>
|
||||
|
@ -664,7 +664,7 @@ static struct resource da8xx_mmcsd0_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device da8xx_mmcsd0_device = {
|
||||
.name = "davinci_mmc",
|
||||
.name = "da830-mmc",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
|
||||
.resource = da8xx_mmcsd0_resources,
|
||||
|
@ -701,7 +701,7 @@ static struct resource da850_mmcsd1_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device da850_mmcsd1_device = {
|
||||
.name = "davinci_mmc",
|
||||
.name = "da830-mmc",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
|
||||
.resource = da850_mmcsd1_resources,
|
||||
|
@ -714,6 +714,92 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
|
|||
}
|
||||
#endif
|
||||
|
||||
static struct resource da8xx_rproc_resources[] = {
|
||||
{ /* DSP boot address */
|
||||
.start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
|
||||
.end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{ /* DSP interrupt registers */
|
||||
.start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
|
||||
.end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{ /* dsp irq */
|
||||
.start = IRQ_DA8XX_CHIPINT0,
|
||||
.end = IRQ_DA8XX_CHIPINT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device da8xx_dsp = {
|
||||
.name = "davinci-rproc",
|
||||
.dev = {
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(da8xx_rproc_resources),
|
||||
.resource = da8xx_rproc_resources,
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
|
||||
|
||||
static phys_addr_t rproc_base __initdata;
|
||||
static unsigned long rproc_size __initdata;
|
||||
|
||||
static int __init early_rproc_mem(char *p)
|
||||
{
|
||||
char *endp;
|
||||
|
||||
if (p == NULL)
|
||||
return 0;
|
||||
|
||||
rproc_size = memparse(p, &endp);
|
||||
if (*endp == '@')
|
||||
rproc_base = memparse(endp + 1, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_param("rproc_mem", early_rproc_mem);
|
||||
|
||||
void __init da8xx_rproc_reserve_cma(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!rproc_base || !rproc_size) {
|
||||
pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
|
||||
" 'nn' and 'address' must both be non-zero\n",
|
||||
__func__);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
|
||||
__func__, rproc_size, (unsigned long)rproc_base);
|
||||
|
||||
ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
|
||||
if (ret)
|
||||
pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __init da8xx_rproc_reserve_cma(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int __init da8xx_register_rproc(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_device_register(&da8xx_dsp);
|
||||
if (ret)
|
||||
pr_err("%s: can't register DSP device: %d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
static struct resource da8xx_rtc_resources[] = {
|
||||
{
|
||||
.start = DA8XX_RTC_BASE,
|
||||
|
|
|
@ -218,7 +218,7 @@ static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
|
|||
|
||||
static struct platform_device mmc_devices[2] = {
|
||||
{
|
||||
.name = "davinci_mmc",
|
||||
.name = "dm6441-mmc",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &mmc0_dma_mask,
|
||||
|
@ -228,7 +228,7 @@ static struct platform_device mmc_devices[2] = {
|
|||
.resource = mmc0_resources
|
||||
},
|
||||
{
|
||||
.name = "davinci_mmc",
|
||||
.name = "dm6441-mmc",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &mmc1_dma_mask,
|
||||
|
|
|
@ -150,7 +150,7 @@ static struct resource mmcsd0_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device davinci_mmcsd0_device = {
|
||||
.name = "davinci_mmc",
|
||||
.name = "dm6441-mmc",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &mmcsd0_dma_mask,
|
||||
|
@ -187,7 +187,7 @@ static struct resource mmcsd1_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device davinci_mmcsd1_device = {
|
||||
.name = "davinci_mmc",
|
||||
.name = "dm6441-mmc",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &mmcsd1_dma_mask,
|
||||
|
@ -235,6 +235,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
|
|||
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
|
||||
SZ_4K - 1;
|
||||
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
|
||||
davinci_mmcsd1_device.name = "da830-mmc";
|
||||
} else
|
||||
break;
|
||||
|
||||
|
@ -256,6 +257,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
|
|||
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
|
||||
SZ_4K - 1;
|
||||
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
|
||||
davinci_mmcsd0_device.name = "da830-mmc";
|
||||
} else if (cpu_is_davinci_dm644x()) {
|
||||
/* REVISIT: should this be in board-init code? */
|
||||
/* Power-on 3.3V IO cells */
|
||||
|
|
|
@ -363,8 +363,8 @@ static struct clk_lookup dm355_clks[] = {
|
|||
CLK("i2c_davinci.1", NULL, &i2c_clk),
|
||||
CLK("davinci-mcbsp.0", NULL, &asp0_clk),
|
||||
CLK("davinci-mcbsp.1", NULL, &asp1_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK("spi_davinci.0", NULL, &spi0_clk),
|
||||
CLK("spi_davinci.1", NULL, &spi1_clk),
|
||||
CLK("spi_davinci.2", NULL, &spi2_clk),
|
||||
|
|
|
@ -458,8 +458,8 @@ static struct clk_lookup dm365_clks[] = {
|
|||
CLK(NULL, "uart0", &uart0_clk),
|
||||
CLK(NULL, "uart1", &uart1_clk),
|
||||
CLK("i2c_davinci.1", NULL, &i2c_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK("da830-mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("da830-mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK("spi_davinci.0", NULL, &spi0_clk),
|
||||
CLK("spi_davinci.1", NULL, &spi1_clk),
|
||||
CLK("spi_davinci.2", NULL, &spi2_clk),
|
||||
|
|
|
@ -310,7 +310,7 @@ static struct clk_lookup dm644x_clks[] = {
|
|||
CLK("i2c_davinci.1", NULL, &i2c_clk),
|
||||
CLK("palm_bk3710", NULL, &ide_clk),
|
||||
CLK("davinci-mcbsp", NULL, &asp_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd_clk),
|
||||
CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
|
||||
CLK(NULL, "spi", &spi_clk),
|
||||
CLK(NULL, "gpio", &gpio_clk),
|
||||
CLK(NULL, "usb", &usb_clk),
|
||||
|
|
|
@ -54,7 +54,10 @@ extern unsigned int da850_max_speed;
|
|||
#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
|
||||
#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
|
||||
#define DA8XX_JTAG_ID_REG 0x18
|
||||
#define DA8XX_HOST1CFG_REG 0x44
|
||||
#define DA8XX_CHIPSIG_REG 0x174
|
||||
#define DA8XX_CFGCHIP0_REG 0x17c
|
||||
#define DA8XX_CFGCHIP1_REG 0x180
|
||||
#define DA8XX_CFGCHIP2_REG 0x184
|
||||
#define DA8XX_CFGCHIP3_REG 0x188
|
||||
|
||||
|
@ -104,6 +107,8 @@ int __init da850_register_vpif_display
|
|||
int __init da850_register_vpif_capture
|
||||
(struct vpif_capture_config *capture_config);
|
||||
void da8xx_restart(char mode, const char *cmd);
|
||||
void da8xx_rproc_reserve_cma(void);
|
||||
int da8xx_register_rproc(void);
|
||||
|
||||
extern struct platform_device da8xx_serial_device;
|
||||
extern struct emac_platform_data da8xx_emac_pdata;
|
||||
|
|
|
@ -24,8 +24,6 @@
|
|||
|
||||
#if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0)
|
||||
#define UART_BASE DAVINCI_UART0_BASE
|
||||
#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART0)
|
||||
#define UART_BASE DA8XX_UART0_BASE
|
||||
#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1)
|
||||
#define UART_BASE DA8XX_UART1_BASE
|
||||
#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2)
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <asm/delay.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/da8xx.h>
|
||||
#include <mach/sram.h>
|
||||
#include <mach/pm.h>
|
||||
|
|
|
@ -62,7 +62,7 @@ static int __init sram_init(void)
|
|||
phys_addr_t phys = davinci_soc_info.sram_dma;
|
||||
unsigned len = davinci_soc_info.sram_len;
|
||||
int status = 0;
|
||||
void *addr;
|
||||
void __iomem *addr;
|
||||
|
||||
if (len) {
|
||||
len = min_t(unsigned, len, SRAM_SIZE);
|
||||
|
@ -75,7 +75,7 @@ static int __init sram_init(void)
|
|||
addr = ioremap(phys, len);
|
||||
if (!addr)
|
||||
return -ENOMEM;
|
||||
status = gen_pool_add_virt(sram_pool, (unsigned)addr,
|
||||
status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
|
||||
phys, len, -1);
|
||||
if (status < 0)
|
||||
iounmap(addr);
|
||||
|
|
|
@ -272,7 +272,7 @@ static struct clk_lookup clks[] = {
|
|||
CLK("tnetv107x-keypad.0", NULL, &clk_keypad),
|
||||
CLK(NULL, "clk_gpio", &clk_gpio),
|
||||
CLK(NULL, "clk_mdio", &clk_mdio),
|
||||
CLK("davinci_mmc.0", NULL, &clk_sdio0),
|
||||
CLK("dm6441-mmc.0", NULL, &clk_sdio0),
|
||||
CLK(NULL, "uart0", &clk_uart0),
|
||||
CLK(NULL, "uart1", &clk_uart1),
|
||||
CLK(NULL, "timer0", &clk_timer0),
|
||||
|
@ -292,7 +292,7 @@ static struct clk_lookup clks[] = {
|
|||
CLK(NULL, "clk_system", &clk_system),
|
||||
CLK(NULL, "clk_imcop", &clk_imcop),
|
||||
CLK(NULL, "clk_spare", &clk_spare),
|
||||
CLK("davinci_mmc.1", NULL, &clk_sdio1),
|
||||
CLK("dm6441-mmc.1", NULL, &clk_sdio1),
|
||||
CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst),
|
||||
CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst),
|
||||
CLK(NULL, NULL, NULL),
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/da8xx.h>
|
||||
#include <linux/platform_data/usb-davinci.h>
|
||||
|
||||
#define DAVINCI_USB_OTG_BASE 0x01c64000
|
||||
|
|
|
@ -463,6 +463,8 @@ void __init exynos4_init_irq(void)
|
|||
* uses GIC instead of VIC.
|
||||
*/
|
||||
s5p_init_irq(NULL, 0);
|
||||
|
||||
gic_arch_extn.irq_set_wake = s3c_irq_wake;
|
||||
}
|
||||
|
||||
void __init exynos5_init_irq(void)
|
||||
|
|
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