[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Коммит
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@ -47,9 +47,9 @@ extern asmlinkage void excite_handle_int(void);
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*/
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init(0);
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rm7k_cpu_irq_init(8);
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rm9k_cpu_irq_init(12);
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mips_cpu_irq_init();
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rm7k_cpu_irq_init();
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rm9k_cpu_irq_init();
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#ifdef CONFIG_KGDB
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excite_kgdb_init();
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@ -104,7 +104,7 @@ void __init arch_init_irq(void)
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GT_WRITE(GT_INTRMASK_OFS, 0);
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init_i8259_irqs(); /* 0 ... 15 */
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mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
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mips_cpu_irq_init(); /* 16 ... 23 */
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/*
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* Mask all cpu interrupts
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@ -17,6 +17,7 @@
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#include <linux/ptrace.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/system.h>
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#include <asm/mipsregs.h>
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#include <asm/debug.h>
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@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
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}
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extern void vrc5477_irq_init(u32 base);
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extern void mips_cpu_irq_init(u32 base);
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static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
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void __init arch_init_irq(void)
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@ -125,7 +125,7 @@ void __init arch_init_irq(void)
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/* init all controllers */
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init_i8259_irqs();
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mips_cpu_irq_init(CPU_IRQ_BASE);
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mips_cpu_irq_init();
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vrc5477_irq_init(VRC5477_IRQ_BASE);
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@ -234,7 +234,7 @@ static void __init dec_init_kn01(void)
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memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
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sizeof(kn01_cpu_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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mips_cpu_irq_init();
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} /* dec_init_kn01 */
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@ -309,7 +309,7 @@ static void __init dec_init_kn230(void)
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memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
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sizeof(kn230_cpu_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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mips_cpu_irq_init();
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} /* dec_init_kn230 */
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@ -403,7 +403,7 @@ static void __init dec_init_kn02(void)
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memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
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sizeof(kn02_asic_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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mips_cpu_irq_init();
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init_kn02_irqs(KN02_IRQ_BASE);
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} /* dec_init_kn02 */
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@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void)
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memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
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sizeof(kn02ba_asic_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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mips_cpu_irq_init();
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init_ioasic_irqs(IO_IRQ_BASE);
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} /* dec_init_kn02ba */
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@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void)
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memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
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sizeof(kn02ca_asic_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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mips_cpu_irq_init();
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init_ioasic_irqs(IO_IRQ_BASE);
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} /* dec_init_kn02ca */
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@ -702,7 +702,7 @@ static void __init dec_init_kn03(void)
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memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
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sizeof(kn03_asic_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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mips_cpu_irq_init();
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init_ioasic_irqs(IO_IRQ_BASE);
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} /* dec_init_kn03 */
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@ -106,7 +106,7 @@ void __init arch_init_irq(void)
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emma2rh_irq_init(EMMA2RH_IRQ_BASE);
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emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
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emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
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mips_cpu_irq_init(CPU_IRQ_BASE);
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mips_cpu_irq_init();
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/* setup cascade interrupts */
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setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
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@ -90,6 +90,6 @@ void __init arch_init_irq(void)
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clear_c0_status(ST0_IM);
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local_irq_disable();
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mips_cpu_irq_init(0);
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rm7k_cpu_irq_init(8);
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mips_cpu_irq_init();
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rm7k_cpu_irq_init();
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}
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@ -63,7 +63,7 @@ void gt64120_init_pic(void)
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void __init arch_init_irq(void)
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{
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/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
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mips_cpu_irq_init(0);
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mips_cpu_irq_init();
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gt64120_init_pic();
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}
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@ -17,16 +17,14 @@
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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static int irq_base;
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static inline void unmask_rm7k_irq(unsigned int irq)
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{
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set_c0_intcontrol(0x100 << (irq - irq_base));
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set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE));
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}
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static inline void mask_rm7k_irq(unsigned int irq)
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{
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clear_c0_intcontrol(0x100 << (irq - irq_base));
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clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE));
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}
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static struct irq_chip rm7k_irq_controller = {
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@ -37,8 +35,9 @@ static struct irq_chip rm7k_irq_controller = {
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.unmask = unmask_rm7k_irq,
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};
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void __init rm7k_cpu_irq_init(int base)
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void __init rm7k_cpu_irq_init(void)
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{
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int base = RM7K_CPU_IRQ_BASE;
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int i;
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clear_c0_intcontrol(0x00000f00); /* Mask all */
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@ -46,6 +45,4 @@ void __init rm7k_cpu_irq_init(int base)
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for (i = base; i < base + 4; i++)
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set_irq_chip_and_handler(i, &rm7k_irq_controller,
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handle_level_irq);
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irq_base = base;
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}
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@ -18,16 +18,14 @@
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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static int irq_base;
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static inline void unmask_rm9k_irq(unsigned int irq)
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{
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set_c0_intcontrol(0x1000 << (irq - irq_base));
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set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
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}
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static inline void mask_rm9k_irq(unsigned int irq)
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{
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clear_c0_intcontrol(0x1000 << (irq - irq_base));
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clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
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}
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static inline void rm9k_cpu_irq_enable(unsigned int irq)
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@ -93,8 +91,9 @@ unsigned int rm9000_perfcount_irq;
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EXPORT_SYMBOL(rm9000_perfcount_irq);
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void __init rm9k_cpu_irq_init(int base)
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void __init rm9k_cpu_irq_init(void)
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{
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int base = RM9K_CPU_IRQ_BASE;
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int i;
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clear_c0_intcontrol(0x0000f000); /* Mask all */
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@ -106,6 +105,4 @@ void __init rm9k_cpu_irq_init(int base)
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rm9000_perfcount_irq = base + 1;
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set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
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handle_level_irq);
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irq_base = base;
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}
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@ -25,7 +25,7 @@
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* Don't even think about using this on SMP. You have been warned.
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*
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* This file exports one global function:
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* void mips_cpu_irq_init(int irq_base);
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* void mips_cpu_irq_init(void);
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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@ -36,17 +36,15 @@
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#include <asm/mipsmtregs.h>
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#include <asm/system.h>
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static int mips_cpu_irq_base;
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static inline void unmask_mips_irq(unsigned int irq)
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{
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set_c0_status(0x100 << (irq - mips_cpu_irq_base));
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set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
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irq_enable_hazard();
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}
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static inline void mask_mips_irq(unsigned int irq)
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{
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clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
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clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
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irq_disable_hazard();
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}
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@ -70,7 +68,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
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clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
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evpe(vpflags);
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unmask_mips_mt_irq(irq);
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@ -84,7 +82,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
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static void mips_mt_cpu_irq_ack(unsigned int irq)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
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clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
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evpe(vpflags);
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mask_mips_mt_irq(irq);
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}
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@ -99,8 +97,9 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
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.eoi = unmask_mips_mt_irq,
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};
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void __init mips_cpu_irq_init(int irq_base)
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void __init mips_cpu_irq_init(void)
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{
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int irq_base = MIPS_CPU_IRQ_BASE;
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int i;
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/* Mask interrupts. */
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@ -118,6 +117,4 @@ void __init mips_cpu_irq_init(int irq_base)
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for (i = irq_base + 2; i < irq_base + 8; i++)
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set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
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handle_level_irq);
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mips_cpu_irq_base = irq_base;
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}
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@ -63,7 +63,7 @@ extern void *vpe_get_shared(int index);
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static void rtlx_dispatch(void)
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{
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do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ);
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
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}
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@ -491,7 +491,7 @@ static struct irqaction rtlx_irq = {
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.name = "RTLX",
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};
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static int rtlx_irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ;
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static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
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static char register_chrdev_failed[] __initdata =
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KERN_ERR "rtlx_module_init: unable to register device\n";
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@ -35,7 +35,6 @@
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/mips_mt.h>
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#include <asm/mips-boards/maltaint.h> /* This is f*cking wrong */
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#define MIPS_CPU_IPI_RESCHED_IRQ 0
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#define MIPS_CPU_IPI_CALL_IRQ 1
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@ -108,12 +107,12 @@ void __init sanitize_tlb_entries(void)
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static void ipi_resched_dispatch(void)
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{
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do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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}
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static void ipi_call_dispatch(void)
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{
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do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ);
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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@ -270,8 +269,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
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set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
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}
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cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
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cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
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cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
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cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
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setup_irq(cpu_ipi_resched_irq, &irq_resched);
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setup_irq(cpu_ipi_call_irq, &irq_call);
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@ -26,16 +26,6 @@
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* This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
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*/
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/*
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* MIPSCPU_INT_BASE is identically defined in both
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* asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h,
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* but as yet there's no properly organized include structure that
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* will ensure that the right *int.h file will be included for a
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* given platform build.
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*/
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#define MIPSCPU_INT_BASE 16
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#define MIPS_CPU_IPI_IRQ 1
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#define LOCK_MT_PRA() \
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@ -921,7 +911,7 @@ void smtc_timer_broadcast(int vpe)
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* interrupts.
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*/
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static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ;
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static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
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static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
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{
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@ -238,7 +238,7 @@ void __init arch_init_irq(void)
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init_atlas_irqs(ATLAS_INT_BASE);
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if (!cpu_has_veic)
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mips_cpu_irq_init(MIPSCPU_INT_BASE);
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mips_cpu_irq_init();
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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@ -310,7 +310,7 @@ void __init arch_init_irq(void)
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init_i8259_irqs();
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if (!cpu_has_veic)
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mips_cpu_irq_init (MIPSCPU_INT_BASE);
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mips_cpu_irq_init();
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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@ -113,5 +113,5 @@ asmlinkage void plat_irq_dispatch(void)
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init(MIPSCPU_INT_BASE);
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mips_cpu_irq_init();
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}
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@ -21,9 +21,7 @@
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <asm/mips-boards/simint.h>
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extern void mips_cpu_irq_init(int);
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#include <asm/irq_cpu.h>
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static inline int clz(unsigned long x)
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{
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@ -86,5 +84,5 @@ asmlinkage void plat_irq_dispatch(void)
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init(MIPSCPU_INT_BASE);
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mips_cpu_irq_init();
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}
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@ -82,8 +82,8 @@ void __init arch_init_irq(void)
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*/
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clear_c0_status(ST0_IM);
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mips_cpu_irq_init(0);
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rm7k_cpu_irq_init(8);
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mips_cpu_irq_init();
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rm7k_cpu_irq_init();
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||||
/* set up the cascading interrupts */
|
||||
setup_irq(8, &cascade_mv64340);
|
||||
|
|
|
@ -65,7 +65,7 @@ void __init arch_init_irq(void)
|
|||
*/
|
||||
clear_c0_status(ST0_IM | ST0_BEV);
|
||||
|
||||
rm7k_cpu_irq_init(8);
|
||||
rm7k_cpu_irq_init();
|
||||
|
||||
/* set up the cascading interrupts */
|
||||
setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
|
||||
|
|
|
@ -94,7 +94,7 @@ void __init arch_init_irq(void)
|
|||
*/
|
||||
clear_c0_status(ST0_IM);
|
||||
|
||||
mips_cpu_irq_init(0);
|
||||
mips_cpu_irq_init();
|
||||
|
||||
/* set up the cascading interrupts */
|
||||
setup_irq(3, &cascade_fpga);
|
||||
|
|
|
@ -94,8 +94,8 @@ void __init arch_init_irq(void)
|
|||
clear_c0_status(ST0_IM);
|
||||
local_irq_disable();
|
||||
|
||||
mips_cpu_irq_init(0);
|
||||
rm7k_cpu_irq_init(8);
|
||||
mips_cpu_irq_init();
|
||||
rm7k_cpu_irq_init();
|
||||
|
||||
gt64240_irq_init();
|
||||
}
|
||||
|
|
|
@ -148,9 +148,9 @@ void __init arch_init_irq(void)
|
|||
{
|
||||
clear_c0_status(ST0_IM);
|
||||
|
||||
mips_cpu_irq_init(0);
|
||||
rm7k_cpu_irq_init(8);
|
||||
rm9k_cpu_irq_init(12);
|
||||
mips_cpu_irq_init();
|
||||
rm7k_cpu_irq_init();
|
||||
rm9k_cpu_irq_init();
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
/* At this point, initialize the second serial port */
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
|
||||
#include <asm/sgi/ioc.h>
|
||||
#include <asm/sgi/hpc3.h>
|
||||
|
@ -253,8 +254,6 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
indy_8254timer_irq();
|
||||
}
|
||||
|
||||
extern void mips_cpu_irq_init(unsigned int irq_base);
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
@ -316,7 +315,7 @@ void __init arch_init_irq(void)
|
|||
sgint->cmeimask1 = 0;
|
||||
|
||||
/* init CPU irqs */
|
||||
mips_cpu_irq_init(SGINT_CPU);
|
||||
mips_cpu_irq_init();
|
||||
|
||||
for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
|
||||
struct irq_chip *handler;
|
||||
|
|
|
@ -117,5 +117,5 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
|
||||
mips_cpu_irq_init();
|
||||
}
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#ifndef __ASM_DDB5XXX_DDB5477_H
|
||||
#define __ASM_DDB5XXX_DDB5477_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* This contains macros that are specific to DDB5477 or renamed from
|
||||
|
@ -257,8 +258,8 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
|
|||
#define DDB_IRQ_BASE 0
|
||||
|
||||
#define I8259_IRQ_BASE DDB_IRQ_BASE
|
||||
#define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
|
||||
#define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
|
||||
#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
|
||||
#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
|
||||
|
||||
/*
|
||||
* vrc5477 irq defs
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#ifndef __ASM_DEC_INTERRUPTS_H
|
||||
#define __ASM_DEC_INTERRUPTS_H
|
||||
|
||||
#include <irq.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
|
||||
|
@ -87,7 +88,7 @@
|
|||
#define DEC_CPU_INR_SW1 1 /* software #1 */
|
||||
#define DEC_CPU_INR_SW0 0 /* software #0 */
|
||||
|
||||
#define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */
|
||||
#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
|
||||
|
||||
#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
|
||||
#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
|
||||
|
|
|
@ -24,6 +24,8 @@
|
|||
#ifndef __ASM_EMMA2RH_EMMA2RH_H
|
||||
#define __ASM_EMMA2RH_EMMA2RH_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* EMMA2RH registers
|
||||
*/
|
||||
|
@ -104,7 +106,8 @@
|
|||
#define NUM_EMMA2RH_IRQ 96
|
||||
|
||||
#define CPU_EMMA2RH_CASCADE 2
|
||||
#define EMMA2RH_IRQ_BASE 0
|
||||
#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
|
||||
#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
|
||||
|
||||
/*
|
||||
* emma2rh irq defs
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
|
||||
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
|
||||
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
|
||||
#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
|
||||
|
||||
#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
|
||||
#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
|
||||
|
|
|
@ -13,8 +13,8 @@
|
|||
#ifndef _ASM_IRQ_CPU_H
|
||||
#define _ASM_IRQ_CPU_H
|
||||
|
||||
extern void mips_cpu_irq_init(int irq_base);
|
||||
extern void rm7k_cpu_irq_init(int irq_base);
|
||||
extern void rm9k_cpu_irq_init(int irq_base);
|
||||
extern void mips_cpu_irq_init(void);
|
||||
extern void rm7k_cpu_irq_init(void);
|
||||
extern void rm9k_cpu_irq_init(void);
|
||||
|
||||
#endif /* _ASM_IRQ_CPU_H */
|
||||
|
|
|
@ -12,6 +12,8 @@
|
|||
#ifndef __ASM_COBALT_H
|
||||
#define __ASM_COBALT_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* i8259 legacy interrupts used on Cobalt:
|
||||
*
|
||||
|
@ -25,7 +27,7 @@
|
|||
/*
|
||||
* CPU IRQs are 16 ... 23
|
||||
*/
|
||||
#define COBALT_CPU_IRQ 16
|
||||
#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
|
||||
|
||||
#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
|
||||
#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
|
||||
|
|
|
@ -10,4 +10,6 @@
|
|||
|
||||
#define NR_IRQS 256
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
|
||||
|
|
|
@ -8,6 +8,32 @@
|
|||
#ifndef __ASM_MACH_GENERIC_IRQ_H
|
||||
#define __ASM_MACH_GENERIC_IRQ_H
|
||||
|
||||
#ifndef NR_IRQS
|
||||
#define NR_IRQS 128
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IRQ_CPU
|
||||
|
||||
#ifndef MIPS_CPU_IRQ_BASE
|
||||
#ifdef CONFIG_I8259
|
||||
#define MIPS_CPU_IRQ_BASE 16
|
||||
#else
|
||||
#define MIPS_CPU_IRQ_BASE 0
|
||||
#endif /* CONFIG_I8259 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IRQ_CPU_RM7K
|
||||
#ifndef RM7K_CPU_IRQ_BASE
|
||||
#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IRQ_CPU_RM9K
|
||||
#ifndef RM9K_CPU_IRQ_BASE
|
||||
#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_IRQ_CPU */
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_IRQ_H */
|
||||
|
|
|
@ -4,4 +4,6 @@
|
|||
|
||||
#define NR_IRQS 256
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif /* __ASM_MACH_MIPS_IRQ_H */
|
||||
|
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef __ASM_MACH_VR41XX_IRQ_H
|
||||
#define __ASM_MACH_VR41XX_IRQ_H
|
||||
|
||||
#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif /* __ASM_MACH_VR41XX_IRQ_H */
|
|
@ -26,10 +26,12 @@
|
|||
#ifndef _MIPS_ATLASINT_H
|
||||
#define _MIPS_ATLASINT_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
|
||||
*/
|
||||
#define MIPSCPU_INT_BASE 0
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
|
||||
/* CPU interrupt offsets */
|
||||
#define MIPSCPU_INT_SW0 0
|
||||
|
|
|
@ -25,6 +25,8 @@
|
|||
#ifndef _MIPS_MALTAINT_H
|
||||
#define _MIPS_MALTAINT_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* Interrupts 0..15 are used for Malta ISA compatible interrupts
|
||||
*/
|
||||
|
@ -33,7 +35,7 @@
|
|||
/*
|
||||
* Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
|
||||
*/
|
||||
#define MIPSCPU_INT_BASE 16
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
|
||||
/* CPU interrupt offsets */
|
||||
#define MIPSCPU_INT_SW0 0
|
||||
|
|
|
@ -20,10 +20,12 @@
|
|||
#ifndef _MIPS_SEADINT_H
|
||||
#define _MIPS_SEADINT_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* Interrupts 0..7 are used for SEAD CPU interrupts
|
||||
*/
|
||||
#define MIPSCPU_INT_BASE 0
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
|
||||
#define MIPSCPU_INT_UART0 2
|
||||
#define MIPSCPU_INT_UART1 3
|
||||
|
|
|
@ -17,10 +17,11 @@
|
|||
#ifndef _MIPS_SIMINT_H
|
||||
#define _MIPS_SIMINT_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
#define SIM_INT_BASE 0
|
||||
#define MIPSCPU_INT_MB0 2
|
||||
#define MIPSCPU_INT_BASE 16
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
|
||||
|
|
|
@ -6,9 +6,10 @@
|
|||
#ifndef __ASM_RTLX_H
|
||||
#define __ASM_RTLX_H_
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
#define LX_NODE_BASE 10
|
||||
|
||||
#define MIPSCPU_INT_BASE 16
|
||||
#define MIPS_CPU_RTLX_IRQ 0
|
||||
|
||||
#define RTLX_VERSION 2
|
||||
|
|
|
@ -21,15 +21,16 @@
|
|||
* HAL2 driver). This will prevent many complications, trust me ;-)
|
||||
*/
|
||||
|
||||
#include <irq.h>
|
||||
#include <asm/sgi/ioc.h>
|
||||
|
||||
#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */
|
||||
#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */
|
||||
#define SGINT_LOCAL0 24 /* 8 local0 irq levels */
|
||||
#define SGINT_LOCAL1 32 /* 8 local1 irq levels */
|
||||
#define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */
|
||||
#define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */
|
||||
#define SGINT_END 56 /* End of 'spaces' */
|
||||
#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
|
||||
#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */
|
||||
#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */
|
||||
#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */
|
||||
#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */
|
||||
#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
|
||||
|
||||
/*
|
||||
* Individual interrupt definitions for the Indy and Indigo2
|
||||
|
|
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