drm/msm/mdp5: Use the interconnect API
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the most appropriate power/performance profile. Use the API to configure the interconnects and request bandwidth between DDR and the display hardware (MDP port(s) and rotator downscaler). v2: update the path names to be consistent with dpu, handle the NULL path case, updated commit msg from Georgi. v3: split out icc setup into it's own function, and rework logic slightly so no interconnect paths is not fatal. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-By: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
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@ -16,6 +16,7 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interconnect.h>
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#include <linux/of_irq.h>
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#include "msm_drv.h"
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@ -1048,9 +1049,46 @@ static const struct component_ops mdp5_ops = {
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.unbind = mdp5_unbind,
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};
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static int mdp5_setup_interconnect(struct platform_device *pdev)
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{
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struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem");
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struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem");
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struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem");
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if (IS_ERR(path0))
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return PTR_ERR(path0);
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if (!path0) {
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/* no interconnect support is not necessarily a fatal
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* condition, the platform may simply not have an
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* interconnect driver yet. But warn about it in case
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* bootloader didn't setup bus clocks high enough for
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* scanout.
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*/
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dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
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return 0;
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}
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icc_set_bw(path0, 0, MBps_to_icc(6400));
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if (!IS_ERR_OR_NULL(path1))
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icc_set_bw(path1, 0, MBps_to_icc(6400));
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if (!IS_ERR_OR_NULL(path_rot))
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icc_set_bw(path_rot, 0, MBps_to_icc(6400));
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return 0;
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}
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static int mdp5_dev_probe(struct platform_device *pdev)
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{
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int ret;
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DBG("");
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ret = mdp5_setup_interconnect(pdev);
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if (ret)
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return ret;
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return component_add(&pdev->dev, &mdp5_ops);
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}
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