drivers/char/synclink_gt.c: add extended sync feature
Add support for extended byte synchronous mode feature of hardware. Signed-off-by: Paul Fulghum <paulkf@microgate.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Paul Fulghum
Linus Torvalds
Родитель
ed77ed6112
Коммит
9807224f1d
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@ -301,6 +301,8 @@ struct slgt_info {
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unsigned int rx_pio;
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unsigned int if_mode;
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unsigned int base_clock;
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unsigned int xsync;
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unsigned int xctrl;
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/* device status */
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@ -405,6 +407,8 @@ static MGSL_PARAMS default_params = {
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#define TDCSR 0x94 /* tx DMA control/status */
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#define RDDAR 0x98 /* rx DMA descriptor address */
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#define TDDAR 0x9c /* tx DMA descriptor address */
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#define XSR 0x40 /* extended sync pattern */
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#define XCR 0x44 /* extended control */
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#define RXIDLE BIT14
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#define RXBREAK BIT14
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@ -517,6 +521,10 @@ static int set_interface(struct slgt_info *info, int if_mode);
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static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
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static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
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static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
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static int get_xsync(struct slgt_info *info, int __user *if_mode);
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static int set_xsync(struct slgt_info *info, int if_mode);
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static int get_xctrl(struct slgt_info *info, int __user *if_mode);
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static int set_xctrl(struct slgt_info *info, int if_mode);
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/*
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* driver functions
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@ -1056,6 +1064,14 @@ static int ioctl(struct tty_struct *tty, struct file *file,
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return get_gpio(info, argp);
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case MGSL_IOCWAITGPIO:
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return wait_gpio(info, argp);
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case MGSL_IOCGXSYNC:
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return get_xsync(info, argp);
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case MGSL_IOCSXSYNC:
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return set_xsync(info, (int)arg);
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case MGSL_IOCGXCTRL:
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return get_xctrl(info, argp);
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case MGSL_IOCSXCTRL:
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return set_xctrl(info, (int)arg);
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}
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mutex_lock(&info->port.mutex);
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switch (cmd) {
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@ -1213,12 +1229,16 @@ static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
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case MGSL_IOCSGPIO:
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case MGSL_IOCGGPIO:
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case MGSL_IOCWAITGPIO:
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case MGSL_IOCGXSYNC:
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case MGSL_IOCGXCTRL:
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case MGSL_IOCSTXIDLE:
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case MGSL_IOCTXENABLE:
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case MGSL_IOCRXENABLE:
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case MGSL_IOCTXABORT:
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case TIOCMIWAIT:
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case MGSL_IOCSIF:
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case MGSL_IOCSXSYNC:
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case MGSL_IOCSXCTRL:
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rc = ioctl(tty, file, cmd, arg);
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break;
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}
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@ -1961,6 +1981,7 @@ static void bh_handler(struct work_struct *work)
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case MGSL_MODE_RAW:
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case MGSL_MODE_MONOSYNC:
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case MGSL_MODE_BISYNC:
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case MGSL_MODE_XSYNC:
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while(rx_get_buf(info));
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break;
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}
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@ -2889,6 +2910,69 @@ static int set_interface(struct slgt_info *info, int if_mode)
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return 0;
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}
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static int get_xsync(struct slgt_info *info, int __user *xsync)
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{
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DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
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if (put_user(info->xsync, xsync))
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return -EFAULT;
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return 0;
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}
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/*
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* set extended sync pattern (1 to 4 bytes) for extended sync mode
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*
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* sync pattern is contained in least significant bytes of value
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* most significant byte of sync pattern is oldest (1st sent/detected)
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*/
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static int set_xsync(struct slgt_info *info, int xsync)
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{
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unsigned long flags;
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DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
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spin_lock_irqsave(&info->lock, flags);
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info->xsync = xsync;
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wr_reg32(info, XSR, xsync);
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spin_unlock_irqrestore(&info->lock, flags);
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return 0;
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}
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static int get_xctrl(struct slgt_info *info, int __user *xctrl)
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{
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DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
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if (put_user(info->xctrl, xctrl))
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return -EFAULT;
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return 0;
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}
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/*
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* set extended control options
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*
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* xctrl[31:19] reserved, must be zero
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* xctrl[18:17] extended sync pattern length in bytes
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* 00 = 1 byte in xsr[7:0]
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* 01 = 2 bytes in xsr[15:0]
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* 10 = 3 bytes in xsr[23:0]
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* 11 = 4 bytes in xsr[31:0]
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* xctrl[16] 1 = enable terminal count, 0=disabled
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* xctrl[15:0] receive terminal count for fixed length packets
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* value is count minus one (0 = 1 byte packet)
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* when terminal count is reached, receiver
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* automatically returns to hunt mode and receive
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* FIFO contents are flushed to DMA buffers with
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* end of frame (EOF) status
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*/
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static int set_xctrl(struct slgt_info *info, int xctrl)
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{
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unsigned long flags;
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DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
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spin_lock_irqsave(&info->lock, flags);
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info->xctrl = xctrl;
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wr_reg32(info, XCR, xctrl);
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spin_unlock_irqrestore(&info->lock, flags);
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return 0;
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}
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/*
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* set general purpose IO pin state and direction
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*
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@ -3768,7 +3852,9 @@ module_exit(slgt_exit);
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#define CALC_REGADDR() \
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unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
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if (addr >= 0x80) \
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reg_addr += (info->port_num) * 32;
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reg_addr += (info->port_num) * 32; \
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else if (addr >= 0x40) \
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reg_addr += (info->port_num) * 16;
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static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
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{
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@ -4187,7 +4273,13 @@ static void sync_mode(struct slgt_info *info)
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/* TCR (tx control)
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*
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* 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
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* 15..13 mode
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* 000=HDLC/SDLC
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* 001=raw bit synchronous
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* 010=asynchronous/isochronous
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* 011=monosync byte synchronous
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* 100=bisync byte synchronous
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* 101=xsync byte synchronous
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* 12..10 encoding
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* 09 CRC enable
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* 08 CRC32
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@ -4202,6 +4294,9 @@ static void sync_mode(struct slgt_info *info)
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val = BIT2;
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switch(info->params.mode) {
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case MGSL_MODE_XSYNC:
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val |= BIT15 + BIT13;
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break;
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case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
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case MGSL_MODE_BISYNC: val |= BIT15; break;
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case MGSL_MODE_RAW: val |= BIT13; break;
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@ -4256,7 +4351,13 @@ static void sync_mode(struct slgt_info *info)
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/* RCR (rx control)
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*
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* 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
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* 15..13 mode
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* 000=HDLC/SDLC
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* 001=raw bit synchronous
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* 010=asynchronous/isochronous
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* 011=monosync byte synchronous
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* 100=bisync byte synchronous
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* 101=xsync byte synchronous
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* 12..10 encoding
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* 09 CRC enable
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* 08 CRC32
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@ -4268,6 +4369,9 @@ static void sync_mode(struct slgt_info *info)
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val = 0;
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switch(info->params.mode) {
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case MGSL_MODE_XSYNC:
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val |= BIT15 + BIT13;
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break;
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case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
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case MGSL_MODE_BISYNC: val |= BIT15; break;
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case MGSL_MODE_RAW: val |= BIT13; break;
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@ -4684,6 +4788,7 @@ static bool rx_get_buf(struct slgt_info *info)
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switch(info->params.mode) {
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case MGSL_MODE_MONOSYNC:
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case MGSL_MODE_BISYNC:
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case MGSL_MODE_XSYNC:
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/* ignore residue in byte synchronous modes */
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if (desc_residue(info->rbufs[i]))
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count--;
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@ -126,6 +126,7 @@
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#define MGSL_MODE_BISYNC 4
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#define MGSL_MODE_RAW 6
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#define MGSL_MODE_BASE_CLOCK 7
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#define MGSL_MODE_XSYNC 8
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#define MGSL_BUS_TYPE_ISA 1
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#define MGSL_BUS_TYPE_EISA 2
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@ -290,6 +291,10 @@ struct gpio_desc {
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#define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc)
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#define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc)
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#define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc)
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#define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19)
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#define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20)
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#define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21)
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#define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22)
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#ifdef __KERNEL__
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/* provide 32 bit ioctl compatibility on 64 bit systems */
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