ARM: sun5i: Convert to CCU
Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Maxime Ripard
Родитель
5e73761786
Коммит
98a59a0fbf
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@ -65,8 +65,9 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
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<&ahb_gates 43>, <&ahb_gates 44>;
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clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
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<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
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<&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
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status = "disabled";
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};
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@ -74,8 +75,8 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
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<&ahb_gates 44>;
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clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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@ -83,77 +84,19 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
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<&ahb_gates 36>, <&ahb_gates 44>;
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clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
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<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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};
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clocks {
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-indices = <0>, <1>,
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<2>, <5>, <6>,
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<7>, <8>, <9>,
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<10>, <13>,
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<14>, <17>, <18>,
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<20>, <21>, <22>,
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<26>, <28>, <32>,
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<34>, <36>, <40>,
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<43>, <44>,
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<46>, <51>,
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<52>;
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clock-output-names = "ahb_usbotg", "ahb_ehci",
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"ahb_ohci", "ahb_ss", "ahb_dma",
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"ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_nand",
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"ahb_sdram", "ahb_emac", "ahb_ts",
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"ahb_spi0", "ahb_spi1", "ahb_spi2",
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"ahb_gps", "ahb_stimer", "ahb_ve",
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"ahb_tve", "ahb_lcd", "ahb_csi",
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"ahb_hdmi", "ahb_de_be",
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"ahb_de_fe", "ahb_iep",
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"ahb_mali400";
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};
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-indices = <0>, <3>,
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<5>, <6>,
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<10>;
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clock-output-names = "apb0_codec", "apb0_iis",
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"apb0_pio", "apb0_ir",
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"apb0_keypad";
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};
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <1>,
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<2>, <16>,
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<17>, <18>,
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<19>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_uart0",
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"apb1_uart1", "apb1_uart2",
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"apb1_uart3";
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};
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};
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soc@01c00000 {
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <55>;
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clocks = <&ahb_gates 17>;
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clocks = <&ccu CLK_AHB_EMAC>;
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allwinner,sram = <&emac_sram 1>;
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status = "disabled";
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};
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@ -169,7 +112,7 @@
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun5i-a10s-pwm";
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reg = <0x01c20e00 0xc>;
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clocks = <&osc24M>;
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clocks = <&ccu CLK_HOSC>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -180,7 +123,7 @@
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 16>;
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clocks = <&ccu CLK_APB1_UART0>;
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status = "disabled";
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};
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@ -190,12 +133,16 @@
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 18>;
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clocks = <&ccu CLK_APB1_UART2>;
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status = "disabled";
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};
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};
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};
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&ccu {
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compatible = "allwinner,sun5i-a10s-ccu";
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};
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&pio {
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compatible = "allwinner,sun5i-a10s-pinctrl";
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@ -61,8 +61,8 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
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<&tcon_ch0_clk>, <&dram_gates 26>;
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clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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};
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@ -99,114 +99,6 @@
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};
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};
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clocks {
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-indices = <0>, <1>,
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<2>, <5>, <6>,
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<7>, <8>, <9>,
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<10>, <13>,
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<14>, <20>,
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<21>, <22>,
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<28>, <32>, <34>,
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<36>, <40>, <44>,
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<46>, <51>,
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<52>;
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clock-output-names = "ahb_usbotg", "ahb_ehci",
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"ahb_ohci", "ahb_ss", "ahb_dma",
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"ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_nand",
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"ahb_sdram", "ahb_spi0",
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"ahb_spi1", "ahb_spi2",
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"ahb_stimer", "ahb_ve", "ahb_tve",
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"ahb_lcd", "ahb_csi", "ahb_de_be",
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"ahb_de_fe", "ahb_iep",
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"ahb_mali400";
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};
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-indices = <0>, <5>,
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<6>;
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clock-output-names = "apb0_codec", "apb0_pio",
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"apb0_ir";
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};
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <1>,
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<2>, <17>,
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<19>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_uart1",
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"apb1_uart3";
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};
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dram_gates: clk@01c20100 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-dram-gates-clk",
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"allwinner,sun4i-a10-gates-clk";
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reg = <0x01c20100 0x4>;
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clocks = <&pll5 0>;
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clock-indices = <0>,
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<1>,
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<25>,
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<26>,
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<29>,
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<31>;
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clock-output-names = "dram_ve",
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"dram_csi",
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"dram_de_fe",
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"dram_de_be",
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"dram_ace",
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"dram_iep";
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};
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de_be_clk: clk@01c20104 {
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#clock-cells = <0>;
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#reset-cells = <0>;
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compatible = "allwinner,sun4i-a10-display-clk";
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reg = <0x01c20104 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll5 1>;
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clock-output-names = "de-be";
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};
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de_fe_clk: clk@01c2010c {
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#clock-cells = <0>;
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#reset-cells = <0>;
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compatible = "allwinner,sun4i-a10-display-clk";
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reg = <0x01c2010c 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll5 1>;
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clock-output-names = "de-fe";
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};
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tcon_ch0_clk: clk@01c20118 {
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#clock-cells = <0>;
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#reset-cells = <1>;
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compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
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reg = <0x01c20118 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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clock-output-names = "tcon-ch0-sclk";
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};
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tcon_ch1_clk: clk@01c2012c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
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reg = <0x01c2012c 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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clock-output-names = "tcon-ch1-sclk";
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};
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};
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display-engine {
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compatible = "allwinner,sun5i-a13-display-engine";
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allwinner,pipelines = <&fe0>;
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@ -217,11 +109,11 @@
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&tcon_ch0_clk 1>;
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resets = <&ccu RST_LCD>;
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reset-names = "lcd";
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clocks = <&ahb_gates 36>,
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<&tcon_ch0_clk>,
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<&tcon_ch1_clk>;
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clocks = <&ccu CLK_AHB_LCD>,
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<&ccu CLK_TCON_CH0>,
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<&ccu CLK_TCON_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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@ -254,7 +146,7 @@
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun5i-a13-pwm";
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reg = <0x01c20e00 0xc>;
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clocks = <&osc24M>;
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clocks = <&ccu CLK_HOSC>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -263,11 +155,11 @@
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compatible = "allwinner,sun5i-a13-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <47>;
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clocks = <&ahb_gates 46>, <&de_fe_clk>,
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<&dram_gates 25>;
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clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&de_fe_clk>;
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resets = <&ccu RST_DE_FE>;
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status = "disabled";
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ports {
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@ -290,14 +182,14 @@
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be0: display-backend@01e60000 {
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compatible = "allwinner,sun5i-a13-display-backend";
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reg = <0x01e60000 0x10000>;
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clocks = <&ahb_gates 44>, <&de_be_clk>,
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<&dram_gates 26>;
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clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&de_be_clk>;
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resets = <&ccu RST_DE_BE>;
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status = "disabled";
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assigned-clocks = <&de_be_clk>;
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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ports {
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@ -330,6 +222,10 @@
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};
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};
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&ccu {
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compatible = "allwinner,sun5i-a13-ccu";
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};
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&cpu0 {
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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@ -51,9 +51,9 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&ahb_gates 34>, <&ahb_gates 36>,
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<&ahb_gates 44>, <&de_be_clk>,
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<&tcon_ch1_clk>, <&dram_gates 26>;
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clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
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<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
|
||||
};
|
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};
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@ -62,8 +62,8 @@
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tve0: tv-encoder@01c0a000 {
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compatible = "allwinner,sun4i-a10-tv-encoder";
|
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reg = <0x01c0a000 0x1000>;
|
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clocks = <&ahb_gates 34>;
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resets = <&tcon_ch0_clk 0>;
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clocks = <&ccu CLK_AHB_TVE>;
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resets = <&ccu RST_TVE>;
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status = "disabled";
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port {
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|
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@ -44,9 +44,10 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/sun4i-a10-pll2.h>
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#include <dt-bindings/clock/sun5i-ccu.h>
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#include <dt-bindings/dma/sun4i-a10.h>
|
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/reset/sun5i-ccu.h>
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/ {
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interrupt-parent = <&intc>;
|
||||
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@ -59,7 +60,7 @@
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|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
clocks = <&cpu>;
|
||||
clocks = <&ccu CLK_CPU>;
|
||||
};
|
||||
};
|
||||
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||||
|
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@ -68,291 +69,19 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* This is a dummy clock, to be used as placeholder on
|
||||
* other mux clocks when a specific parent clock is not
|
||||
* yet implemented. It should be dropped when the driver
|
||||
* is complete.
|
||||
*/
|
||||
dummy: dummy {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc24M: clk@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
osc3M: osc3M_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "osc3M";
|
||||
};
|
||||
|
||||
osc32k: clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc32k";
|
||||
};
|
||||
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
pll2: clk@01c20008 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-pll2-clk";
|
||||
reg = <0x01c20008 0x8>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll2-1x", "pll2-2x",
|
||||
"pll2-4x", "pll2-8x";
|
||||
};
|
||||
|
||||
pll3: clk@01c20010 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-pll3-clk";
|
||||
reg = <0x01c20010 0x4>;
|
||||
clocks = <&osc3M>;
|
||||
clock-output-names = "pll3";
|
||||
};
|
||||
|
||||
pll3x2: pll3x2_clk {
|
||||
compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <2>;
|
||||
clocks = <&pll3>;
|
||||
clock-output-names = "pll3-2x";
|
||||
};
|
||||
|
||||
pll4: clk@01c20018 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20018 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll4";
|
||||
};
|
||||
|
||||
pll5: clk@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: clk@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
};
|
||||
|
||||
pll7: clk@01c20030 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-pll3-clk";
|
||||
reg = <0x01c20030 0x4>;
|
||||
clocks = <&osc3M>;
|
||||
clock-output-names = "pll7";
|
||||
};
|
||||
|
||||
pll7x2: pll7x2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <2>;
|
||||
clocks = <&pll7>;
|
||||
clock-output-names = "pll7-2x";
|
||||
};
|
||||
|
||||
/* dummy is 200M */
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
axi: axi@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-axi-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
ahb: ahb@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun5i-a13-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>, <&cpu>, <&pll6 1>;
|
||||
clock-output-names = "ahb";
|
||||
/*
|
||||
* Use PLL6 as parent, instead of CPU/AXI
|
||||
* which has rate changes due to cpufreq
|
||||
*/
|
||||
assigned-clocks = <&ahb>;
|
||||
assigned-clock-parents = <&pll6 1>;
|
||||
};
|
||||
|
||||
apb0: apb0@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
apb1: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
axi_gates: clk@01c2005c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-axi-gates-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-indices = <0>;
|
||||
clock-output-names = "axi_dram";
|
||||
};
|
||||
|
||||
nand_clk: clk@01c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
ms_clk: clk@01c20084 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20084 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ms";
|
||||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0",
|
||||
"mmc0_output",
|
||||
"mmc0_sample";
|
||||
};
|
||||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1",
|
||||
"mmc1_output",
|
||||
"mmc1_sample";
|
||||
};
|
||||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2",
|
||||
"mmc2_output",
|
||||
"mmc2_sample";
|
||||
};
|
||||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
};
|
||||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
};
|
||||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
};
|
||||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
};
|
||||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
};
|
||||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
};
|
||||
|
||||
usb_clk: clk@01c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_phy";
|
||||
};
|
||||
|
||||
codec_clk: clk@01c20140 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-codec-clk";
|
||||
reg = <0x01c20140 0x4>;
|
||||
clocks = <&pll2 SUN4I_A10_PLL2_1X>;
|
||||
clock-output-names = "codec";
|
||||
};
|
||||
|
||||
mbus_clk: clk@01c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun5i-a13-mbus-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
|
|
@ -395,7 +124,7 @@
|
|||
compatible = "allwinner,sun4i-a10-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&ahb_gates 6>;
|
||||
clocks = <&ccu CLK_AHB_DMA>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
|
||||
|
|
@ -403,7 +132,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
|
||||
<&dma SUN4I_DMA_DEDICATED 26>;
|
||||
|
|
@ -417,7 +146,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
|
||||
<&dma SUN4I_DMA_DEDICATED 8>;
|
||||
|
|
@ -430,14 +159,8 @@
|
|||
mmc0: mmc@01c0f000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb_gates 8>,
|
||||
<&mmc0_clk 0>,
|
||||
<&mmc0_clk 1>,
|
||||
<&mmc0_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <32>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -447,14 +170,8 @@
|
|||
mmc1: mmc@01c10000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c10000 0x1000>;
|
||||
clocks = <&ahb_gates 9>,
|
||||
<&mmc1_clk 0>,
|
||||
<&mmc1_clk 1>,
|
||||
<&mmc1_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <33>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -464,14 +181,8 @@
|
|||
mmc2: mmc@01c11000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c11000 0x1000>;
|
||||
clocks = <&ahb_gates 10>,
|
||||
<&mmc2_clk 0>,
|
||||
<&mmc2_clk 1>,
|
||||
<&mmc2_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <34>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -481,7 +192,7 @@
|
|||
usb_otg: usb@01c13000 {
|
||||
compatible = "allwinner,sun4i-a10-musb";
|
||||
reg = <0x01c13000 0x0400>;
|
||||
clocks = <&ahb_gates 0>;
|
||||
clocks = <&ccu CLK_AHB_OTG>;
|
||||
interrupts = <38>;
|
||||
interrupt-names = "mc";
|
||||
phys = <&usbphy 0>;
|
||||
|
|
@ -496,9 +207,9 @@
|
|||
compatible = "allwinner,sun5i-a13-usb-phy";
|
||||
reg = <0x01c13400 0x10 0x01c14800 0x4>;
|
||||
reg-names = "phy_ctrl", "pmu1";
|
||||
clocks = <&usb_clk 8>;
|
||||
clocks = <&ccu CLK_USB_PHY0>;
|
||||
clock-names = "usb_phy";
|
||||
resets = <&usb_clk 0>, <&usb_clk 1>;
|
||||
resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
|
||||
reset-names = "usb0_reset", "usb1_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -507,7 +218,7 @@
|
|||
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
|
||||
reg = <0x01c14000 0x100>;
|
||||
interrupts = <39>;
|
||||
clocks = <&ahb_gates 1>;
|
||||
clocks = <&ccu CLK_AHB_EHCI>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -517,7 +228,7 @@
|
|||
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
|
||||
reg = <0x01c14400 0x100>;
|
||||
interrupts = <40>;
|
||||
clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
||||
clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -527,7 +238,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
||||
<&dma SUN4I_DMA_DEDICATED 28>;
|
||||
|
|
@ -537,6 +248,14 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ccu: clock@01c20000 {
|
||||
reg = <0x01c20000 0x400>;
|
||||
clocks = <&osc24M>, <&osc32k>;
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
|
|
@ -547,7 +266,7 @@
|
|||
pio: pinctrl@01c20800 {
|
||||
reg = <0x01c20800 0x400>;
|
||||
interrupts = <28>;
|
||||
clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
|
||||
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
||||
clock-names = "apb", "hosc", "losc";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
|
@ -642,7 +361,7 @@
|
|||
compatible = "allwinner,sun4i-a10-timer";
|
||||
reg = <0x01c20c00 0x90>;
|
||||
interrupts = <22>;
|
||||
clocks = <&osc24M>;
|
||||
clocks = <&ccu CLK_HOSC>;
|
||||
};
|
||||
|
||||
wdt: watchdog@01c20c90 {
|
||||
|
|
@ -662,7 +381,7 @@
|
|||
compatible = "allwinner,sun4i-a10-codec";
|
||||
reg = <0x01c22c00 0x40>;
|
||||
interrupts = <30>;
|
||||
clocks = <&apb0_gates 0>, <&codec_clk>;
|
||||
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
||||
clock-names = "apb", "codec";
|
||||
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
||||
<&dma SUN4I_DMA_NORMAL 19>;
|
||||
|
|
@ -688,7 +407,7 @@
|
|||
interrupts = <2>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
clocks = <&ccu CLK_APB1_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -698,7 +417,7 @@
|
|||
interrupts = <4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
clocks = <&ccu CLK_APB1_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -706,7 +425,7 @@
|
|||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2ac00 0x400>;
|
||||
interrupts = <7>;
|
||||
clocks = <&apb1_gates 0>;
|
||||
clocks = <&ccu CLK_APB1_I2C0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -716,7 +435,7 @@
|
|||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b000 0x400>;
|
||||
interrupts = <8>;
|
||||
clocks = <&apb1_gates 1>;
|
||||
clocks = <&ccu CLK_APB1_I2C1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -726,7 +445,7 @@
|
|||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b400 0x400>;
|
||||
interrupts = <9>;
|
||||
clocks = <&apb1_gates 2>;
|
||||
clocks = <&ccu CLK_APB1_I2C2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -736,7 +455,7 @@
|
|||
compatible = "allwinner,sun5i-a13-hstimer";
|
||||
reg = <0x01c60000 0x1000>;
|
||||
interrupts = <82>, <83>;
|
||||
clocks = <&ahb_gates 28>;
|
||||
clocks = <&ccu CLK_AHB_HSTIMER>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
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