ARM: Kirkwood: Replace clock gating
Add a varient of the basic clk-gate code. This variant calls a function before gating the clock off. This function is used to disable the SATA or PCIe PHY. Now that all the drivers prepare and enable there clk as needed, there is no need for the common code to keep track of which clocks need gating on. Let the common clock framework turn off clocks which are not used. Buy using the added clk varient, when the clk framework turns off SATA or PCIe clocks, we also disabled SATA and PCIe PHYs which were not needed. The function kirkwood_pcie_id() can now be called outside of __init code, so remove this property for it, and functions it calls. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Andrew Lunn
Mike Turquette
Родитель
e919c71665
Коммит
98d9986cb8
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@ -63,27 +63,136 @@ void __init kirkwood_map_io(void)
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iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
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}
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/*
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* Default clock control bits. Any bit _not_ set in this variable
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* will be cleared from the hardware after platform devices have been
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* registered. Some reserved bits must be set to 1.
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*/
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unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static void disable_sata0(void)
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{
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/* Disable PLL and IVREF */
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writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
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/* Disable PHY */
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writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
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}
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static void disable_sata1(void)
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{
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/* Disable PLL and IVREF */
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writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
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/* Disable PHY */
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writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
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}
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static void disable_pcie0(void)
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{
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writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
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while (1)
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if (readl(PCIE_STATUS) & 0x1)
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break;
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writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
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}
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static void disable_pcie1(void)
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{
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u32 dev, rev;
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kirkwood_pcie_id(&dev, &rev);
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if (dev == MV88F6282_DEV_ID) {
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writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
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while (1)
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if (readl(PCIE1_STATUS) & 0x1)
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break;
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writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
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}
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}
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/* An extended version of the gated clk. This calls fn() before
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* disabling the clock. We use this to turn off PHYs etc. */
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struct clk_gate_fn {
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struct clk_gate gate;
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void (*fn)(void);
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};
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#define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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static void clk_gate_fn_disable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
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if (gate_fn->fn)
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gate_fn->fn();
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clk_gate_ops.disable(hw);
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}
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static struct clk_ops clk_gate_fn_ops;
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static struct clk __init *clk_register_gate_fn(struct device *dev,
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const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock,
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void (*fn)(void))
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{
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struct clk_gate_fn *gate_fn;
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struct clk *clk;
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struct clk_init_data init;
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gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
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if (!gate_fn) {
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pr_err("%s: could not allocate gated clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_gate_fn_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_gate assignments */
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gate_fn->gate.reg = reg;
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gate_fn->gate.bit_idx = bit_idx;
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gate_fn->gate.flags = clk_gate_flags;
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gate_fn->gate.lock = lock;
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gate_fn->gate.hw.init = &init;
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/* ops is the gate ops, but with our disable function */
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if (clk_gate_fn_ops.disable != clk_gate_fn_disable) {
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clk_gate_fn_ops = clk_gate_ops;
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clk_gate_fn_ops.disable = clk_gate_fn_disable;
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}
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clk = clk_register(dev, &gate_fn->gate.hw);
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if (IS_ERR(clk))
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kfree(gate_fn);
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return clk;
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}
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static DEFINE_SPINLOCK(gating_lock);
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static struct clk *tclk;
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static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
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{
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return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
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return clk_register_gate(NULL, name, "tclk", 0,
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(void __iomem *)CLOCK_GATING_CTRL,
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bit_idx, 0, &gating_lock);
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}
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static struct clk __init *kirkwood_register_gate_fn(const char *name,
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u8 bit_idx,
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void (*fn)(void))
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{
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return clk_register_gate_fn(NULL, name, "tclk", 0,
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(void __iomem *)CLOCK_GATING_CTRL,
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bit_idx, 0, &gating_lock, fn);
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}
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void __init kirkwood_clk_init(void)
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{
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struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio;
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@ -95,15 +204,19 @@ void __init kirkwood_clk_init(void)
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runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
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ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
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ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
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sata0 = kirkwood_register_gate("sata0", CGC_BIT_SATA0);
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sata1 = kirkwood_register_gate("sata1", CGC_BIT_SATA1);
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sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
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disable_sata0);
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sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
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disable_sata1);
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usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
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sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
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crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
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xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
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xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
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pex0 = kirkwood_register_gate("pex0", CGC_BIT_PEX0);
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pex1 = kirkwood_register_gate("pex1", CGC_BIT_PEX1);
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pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
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disable_pcie0);
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pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
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disable_pcie1);
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audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
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kirkwood_register_gate("tdm", CGC_BIT_TDM);
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kirkwood_register_gate("tsu", CGC_BIT_TSU);
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@ -132,7 +245,6 @@ void __init kirkwood_clk_init(void)
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****************************************************************************/
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void __init kirkwood_ehci_init(void)
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{
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kirkwood_clk_ctrl |= CGC_USB0;
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orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
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}
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@ -142,8 +254,6 @@ void __init kirkwood_ehci_init(void)
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****************************************************************************/
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void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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kirkwood_clk_ctrl |= CGC_GE0;
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orion_ge00_init(eth_data,
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GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
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IRQ_KIRKWOOD_GE00_ERR);
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@ -155,9 +265,6 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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****************************************************************************/
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void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
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{
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kirkwood_clk_ctrl |= CGC_GE1;
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orion_ge01_init(eth_data,
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GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
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IRQ_KIRKWOOD_GE01_ERR);
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@ -202,7 +309,6 @@ static struct platform_device kirkwood_nand_flash = {
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void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
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int chip_delay)
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{
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kirkwood_clk_ctrl |= CGC_RUNIT;
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kirkwood_nand_data.parts = parts;
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kirkwood_nand_data.nr_parts = nr_parts;
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kirkwood_nand_data.chip_delay = chip_delay;
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@ -212,7 +318,6 @@ void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
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void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
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int (*dev_ready)(struct mtd_info *))
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{
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kirkwood_clk_ctrl |= CGC_RUNIT;
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kirkwood_nand_data.parts = parts;
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kirkwood_nand_data.nr_parts = nr_parts;
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kirkwood_nand_data.dev_ready = dev_ready;
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@ -233,10 +338,6 @@ static void __init kirkwood_rtc_init(void)
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****************************************************************************/
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void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
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{
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kirkwood_clk_ctrl |= CGC_SATA0;
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if (sata_data->n_ports > 1)
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kirkwood_clk_ctrl |= CGC_SATA1;
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orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
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}
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@ -279,7 +380,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
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mvsdio_data->clock = 100000000;
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else
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mvsdio_data->clock = 200000000;
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kirkwood_clk_ctrl |= CGC_SDIO;
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kirkwood_sdio.dev.platform_data = mvsdio_data;
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platform_device_register(&kirkwood_sdio);
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}
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@ -290,7 +390,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
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****************************************************************************/
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void __init kirkwood_spi_init()
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{
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kirkwood_clk_ctrl |= CGC_RUNIT;
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orion_spi_init(SPI_PHYS_BASE);
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}
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@ -329,7 +428,6 @@ void __init kirkwood_uart1_init(void)
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****************************************************************************/
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void __init kirkwood_crypto_init(void)
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{
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kirkwood_clk_ctrl |= CGC_CRYPTO;
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orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
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KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
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}
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@ -340,7 +438,6 @@ void __init kirkwood_crypto_init(void)
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****************************************************************************/
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void __init kirkwood_xor0_init(void)
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{
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kirkwood_clk_ctrl |= CGC_XOR0;
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orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
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IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
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}
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@ -351,7 +448,6 @@ void __init kirkwood_xor0_init(void)
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****************************************************************************/
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void __init kirkwood_xor1_init(void)
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{
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kirkwood_clk_ctrl |= CGC_XOR1;
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orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
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IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
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}
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@ -438,7 +534,6 @@ static struct platform_device kirkwood_pcm_device = {
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void __init kirkwood_audio_init(void)
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{
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kirkwood_clk_ctrl |= CGC_AUDIO;
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platform_device_register(&kirkwood_i2s_device);
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platform_device_register(&kirkwood_pcm_device);
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}
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@ -537,61 +632,6 @@ void __init kirkwood_init(void)
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#endif
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}
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static int __init kirkwood_clock_gate(void)
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{
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unsigned int curr = readl(CLOCK_GATING_CTRL);
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u32 dev, rev;
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kirkwood_pcie_id(&dev, &rev);
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printk(KERN_DEBUG "Gating clock of unused units\n");
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printk(KERN_DEBUG "before: 0x%08x\n", curr);
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/* Make sure those units are accessible */
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writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
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/* For SATA: first shutdown the phy */
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if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
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/* Disable PLL and IVREF */
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writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
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/* Disable PHY */
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writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
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}
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if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
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/* Disable PLL and IVREF */
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writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
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/* Disable PHY */
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writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
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}
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/* For PCIe: first shutdown the phy */
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if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
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writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
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while (1)
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if (readl(PCIE_STATUS) & 0x1)
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break;
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writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
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}
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/* For PCIe 1: first shutdown the phy */
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if (dev == MV88F6282_DEV_ID) {
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if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
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writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
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while (1)
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if (readl(PCIE1_STATUS) & 0x1)
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break;
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writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
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}
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} else /* keep this bit set for devices that don't have PCIe1 */
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kirkwood_clk_ctrl |= CGC_PEX1;
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/* Now gate clock the required units */
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writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
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printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
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return 0;
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}
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late_initcall(kirkwood_clock_gate);
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void kirkwood_restart(char mode, const char *cmd)
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{
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/*
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@ -44,7 +44,7 @@ void kirkwood_enable_pcie(void)
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writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
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}
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void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
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void kirkwood_pcie_id(u32 *dev, u32 *rev)
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{
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kirkwood_enable_pcie();
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*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
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@ -181,7 +181,6 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
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static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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extern unsigned int kirkwood_clk_ctrl;
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struct pcie_port *pp;
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int index;
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@ -200,12 +199,10 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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switch (index) {
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case 0:
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kirkwood_clk_ctrl |= CGC_PEX0;
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kirkwood_enable_pcie_clk("0");
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pcie0_ioresources_init(pp);
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break;
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case 1:
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kirkwood_clk_ctrl |= CGC_PEX1;
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kirkwood_enable_pcie_clk("1");
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pcie1_ioresources_init(pp);
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break;
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@ -52,12 +52,12 @@
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#define PCIE_DEBUG_SOFT_RESET (1<<20)
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u32 __init orion_pcie_dev_id(void __iomem *base)
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u32 orion_pcie_dev_id(void __iomem *base)
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{
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return readl(base + PCIE_DEV_ID_OFF) >> 16;
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}
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u32 __init orion_pcie_rev(void __iomem *base)
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u32 orion_pcie_rev(void __iomem *base)
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{
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return readl(base + PCIE_DEV_REV_OFF) & 0xff;
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}
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