microsoft
/
WSL2-Linux-Kernel
зеркало из https://github.com/microsoft/WSL2-Linux-Kernel.git
1
0
Форкнуть 0
Код Задачи Пакеты Проекты Релизы Вики Активность

[ARM] 5532/1: Freescale STMP: register definitions [3/3] 

Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls

Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
dmitry pervushin 2009-05-31 13:32:11 +01:00 коммит произвёл Russell King
Родитель 3f52326a85
Коммит 98f420b23a
13 изменённых файлов: 460 добавлений и 579 удалений
Показать статистику Скачать Patch файл Скачать Diff файл Показать все файлы Свернуть все файлы

109
arch/arm/mach-stmp378x/stmp378x.c
Просмотреть файл

@ -47,25 +47,28 @@
static void stmp378x_ack_irq(unsigned int irq)
{
/* Tell ICOLL to release IRQ line */
HW_ICOLL_VECTOR_WR(0x0);
__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
/* ACK current interrupt */
HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0);
__raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
/* Barrier */
(void) HW_ICOLL_STAT_RD();
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
}
static void stmp378x_mask_irq(unsigned int irq)
{
/* IRQ disable */
HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE);
stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
}
static void stmp378x_unmask_irq(unsigned int irq)
{
/* IRQ enable */
HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE);
stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
}
static struct irq_chip stmp378x_chip = {
@ -84,52 +87,63 @@ void __init stmp378x_init_irq(void)
*/
void stmp3xxx_arch_dma_enable_interrupt(int channel)
{
int dmabus = channel / 16;
void __iomem *c1, *c2;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL1_SET(1 << (16 + (channel % 16)));
HW_APBH_CTRL2_SET(1 << (16 + (channel % 16)));
c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CTRL1_SET(1 << (16 + (channel % 16)));
HW_APBX_CTRL2_SET(1 << (16 + (channel % 16)));
c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
break;
default:
return;
}
stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
void stmp3xxx_arch_dma_clear_interrupt(int channel)
{
int dmabus = channel / 16;
void __iomem *c1, *c2;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL1_CLR(1 << (channel % 16));
HW_APBH_CTRL2_CLR(1 << (channel % 16));
c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CTRL1_CLR(1 << (channel % 16));
HW_APBX_CTRL2_CLR(1 << (channel % 16));
c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
break;
default:
return;
}
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
int stmp3xxx_arch_dma_is_interrupt(int channel)
{
int dmabus = channel / 16;
int r = 0;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
case STMP3XXX_BUS_APBX:
r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));
r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
}
return r;
@ -138,42 +152,41 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
void stmp3xxx_arch_dma_reset_channel(int channel)
{
int dmabus = channel / 16;
unsigned chbit = 1 << (channel % 16);
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
void __iomem *c0;
u32 mask;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
/* Reset channel and wait for it to complete */
HW_APBH_CTRL0_SET(chbit <<
BP_APBH_CTRL0_RESET_CHANNEL);
while (HW_APBH_CTRL0_RD() &
(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
continue;
c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
break;
case STMP3XXX_BUS_APBX:
/* Reset channel and wait for it to complete */
HW_APBX_CHANNEL_CTRL_SET(
BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit));
while (HW_APBX_CHANNEL_CTRL_RD() &
BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit))
continue;
c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
break;
default:
return;
}
/* Reset channel and wait for it to complete */
stmp3xxx_setl(mask, c0);
while (__raw_readl(c0) & mask)
cpu_relax();
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
void stmp3xxx_arch_dma_freeze(int channel)
{
int dmabus = channel / 16;
unsigned chbit = 1 << (channel % 16);
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
u32 mask = 1 << chbit;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL0_SET(1<<chbit);
stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CHANNEL_CTRL_SET(1<<chbit);
stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
break;
}
}
@ -181,15 +194,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
void stmp3xxx_arch_dma_unfreeze(int channel)
{
int dmabus = channel / 16;
unsigned chbit = 1 << (channel % 16);
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
u32 mask = 1 << chbit;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL0_CLR(1<<chbit);
stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CHANNEL_CTRL_CLR(1<<chbit);
stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
break;
}
}
@ -201,7 +214,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
*
* Logical Physical
* f0000000 80000000 On-chip registers
* f1000000 00000000 256k on-chip SRAM
* f1000000 00000000 32k on-chip SRAM
*/
static struct map_desc stmp378x_io_desc[] __initdata = {

84
arch/arm/mach-stmp37xx/stmp37xx.c
Просмотреть файл

@ -34,6 +34,7 @@
#include <mach/stmp3xxx.h>
#include <mach/dma.h>
#include <mach/platform.h>
#include <mach/regs-icoll.h>
#include <mach/regs-apbh.h>
#include <mach/regs-apbx.h>
@ -45,25 +46,28 @@
static void stmp37xx_ack_irq(unsigned int irq)
{
/* Disable IRQ */
HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8));
stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
/* ACK current interrupt */
HW_ICOLL_LEVELACK_WR(1);
__raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
/* Barrier */
(void) HW_ICOLL_STAT_RD();
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
}
static void stmp37xx_mask_irq(unsigned int irq)
{
/* IRQ disable */
HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8));
stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
}
static void stmp37xx_unmask_irq(unsigned int irq)
{
/* IRQ enable */
HW_ICOLL_PRIORITYn_SET(irq / 4, 0x04 << ((irq % 4) * 8));
stmp3xxx_setl(0x04 << ((irq % 4) * 8),
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
}
static struct irq_chip stmp37xx_chip = {
@ -82,15 +86,15 @@ void __init stmp37xx_init_irq(void)
*/
void stmp3xxx_arch_dma_enable_interrupt(int channel)
{
int dmabus = channel / 16;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL1_SET(1 << (8 + (channel % 16)));
stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
REGS_APBH_BASE + HW_APBH_CTRL1);
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CTRL1_SET(1 << (8 + (channel % 16)));
stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
REGS_APBX_BASE + HW_APBX_CTRL1);
break;
}
}
@ -98,15 +102,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
void stmp3xxx_arch_dma_clear_interrupt(int channel)
{
int dmabus = channel / 16;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL1_CLR(1 << (channel % 16));
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
REGS_APBH_BASE + HW_APBH_CTRL1);
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CTRL1_CLR(1 << (channel % 16));
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
REGS_APBX_BASE + HW_APBX_CTRL1);
break;
}
}
@ -116,15 +120,15 @@ int stmp3xxx_arch_dma_is_interrupt(int channel)
{
int r = 0;
int dmabus = channel / 16;
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
case STMP3XXX_BUS_APBX:
r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
}
return r;
@ -133,24 +137,24 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
void stmp3xxx_arch_dma_reset_channel(int channel)
{
int dmabus = channel / 16;
unsigned chbit = 1 << (channel % 16);
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
/* Reset channel and wait for it to complete */
HW_APBH_CTRL0_SET(chbit << BP_APBH_CTRL0_RESET_CHANNEL);
while (HW_APBH_CTRL0_RD() &
stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
REGS_APBH_BASE + HW_APBH_CTRL0);
while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
continue;
cpu_relax();
break;
case STMP3XXX_BUS_APBX:
/* Reset channel and wait for it to complete */
HW_APBX_CTRL0_SET(chbit << BP_APBX_CTRL0_RESET_CHANNEL);
while (HW_APBX_CTRL0_RD() &
stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
REGS_APBX_BASE + HW_APBX_CTRL0);
while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
(chbit << BP_APBX_CTRL0_RESET_CHANNEL))
continue;
cpu_relax();
break;
}
}
@ -158,15 +162,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
void stmp3xxx_arch_dma_freeze(int channel)
{
int dmabus = channel / 16;
unsigned chbit = 1 << (channel % 16);
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL0_SET(1<<chbit);
stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CTRL0_SET(1<<chbit);
stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
}
}
@ -174,15 +177,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
void stmp3xxx_arch_dma_unfreeze(int channel)
{
int dmabus = channel / 16;
unsigned chbit = 1 << (channel % 16);
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
switch (dmabus) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_CTRL0_CLR(1<<chbit);
stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
HW_APBX_CTRL0_CLR(1<<chbit);
stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
}
}
@ -194,7 +196,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
*
* Logical Physical
* f0000000 80000000 On-chip registers
* f1000000 00000000 256k on-chip SRAM
* f1000000 00000000 32k on-chip SRAM
*/
static struct map_desc stmp37xx_io_desc[] __initdata = {
{

167
arch/arm/plat-stmp3xxx/clock.c
Просмотреть файл

@ -15,6 +15,7 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define DEBUG
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
@ -27,6 +28,7 @@
#include <asm/mach-types.h>
#include <asm/clkdev.h>
#include <mach/platform.h>
#include <mach/regs-clkctrl.h>
#include "clock.h"
@ -187,8 +189,8 @@ static long lcdif_get_rate(struct clk *clk)
div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
if (div) {
rate /= div;
div = (HW_CLKCTRL_FRAC_RD() & BM_CLKCTRL_FRAC_PIXFRAC) >>
BP_CLKCTRL_FRAC_PIXFRAC;
div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
rate /= div;
}
clk->rate = rate;
@ -263,15 +265,19 @@ static int lcdif_set_rate(struct clk *clk, u32 rate)
lowest_result / 1000, lowest_result % 1000);
/* Program ref_pix phase fractional divider */
HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) |
BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv));
reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
/* Ungate PFD */
HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX);
stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
/* Program pix divider */
reg_val = __raw_readl(clk->scale_reg);
reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div);
reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
__raw_writel(reg_val, clk->scale_reg);
/* Wait for divider update */
@ -287,7 +293,9 @@ static int lcdif_set_rate(struct clk *clk, u32 rate)
}
/* Switch to ref_pix source */
HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX);
reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
out:
return ret;
@ -296,6 +304,8 @@ out:
static int cpu_set_rate(struct clk *clk, u32 rate)
{
u32 reg_val;
if (rate < 24000)
return -EINVAL;
else if (rate == 24000) {
@ -344,7 +354,12 @@ static int cpu_set_rate(struct clk *clk, u32 rate)
__raw_writel(1<<7, clk->scale_reg + 8);
/* write clkctrl_cpu */
clk->saved_div = clkctrl_cpu;
HW_CLKCTRL_CPU_WR((HW_CLKCTRL_CPU_RD() & ~0x3f) | clkctrl_cpu);
reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
reg_val &= ~0x3F;
reg_val |= clkctrl_cpu;
__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
@ -364,7 +379,7 @@ static long cpu_get_rate(struct clk *clk)
long rate = clk->parent->rate * 18;
rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
rate /= HW_CLKCTRL_CPU_RD() & 0x3f;
rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
rate = ((rate + 9) / 10) * 10;
clk->rate = rate;
@ -411,7 +426,7 @@ static long emi_get_rate(struct clk *clk)
long rate = clk->parent->rate * 18;
rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
rate /= HW_CLKCTRL_EMI_RD() & 0x3f;
rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
clk->rate = rate;
return rate;
@ -427,44 +442,52 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent)
shift = 4;
if (clk->bypass_reg) {
u32 hbus_mask = BM_CLKCTRL_HBUS_DIV_FRAC_EN |
BM_CLKCTRL_HBUS_DIV;
#ifdef CONFIG_ARCH_STMP378X
u32 hbus_val, cpu_val;
if (clk == &cpu_clk && shift == 4) {
u32 hbus_val = HW_CLKCTRL_HBUS_RD();
u32 cpu_val = HW_CLKCTRL_CPU_RD();
hbus_val &= ~hbus_mask;
hbus_val |= 1;
hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_HBUS);
cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_CPU);
hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
BM_CLKCTRL_HBUS_DIV);
clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
cpu_val |= 1;
__raw_writel(1 << clk->bypass_shift,
clk->bypass_reg + shift);
if (machine_is_stmp378x()) {
HW_CLKCTRL_HBUS_WR(hbus_val);
HW_CLKCTRL_CPU_WR(cpu_val);
__raw_writel(hbus_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
__raw_writel(cpu_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
hclk.rate = 0;
}
} else if (clk == &cpu_clk && shift == 8) {
u32 hbus_val = HW_CLKCTRL_HBUS_RD();
u32 cpu_val = HW_CLKCTRL_CPU_RD();
hbus_val &= ~hbus_mask;
hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_HBUS);
cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_CPU);
hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
BM_CLKCTRL_HBUS_DIV);
hbus_val |= 2;
cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
if (clk->saved_div)
cpu_val |= clk->saved_div;
else
cpu_val |= 2;
if (machine_is_stmp378x()) {
HW_CLKCTRL_HBUS_WR(hbus_val);
HW_CLKCTRL_CPU_WR(cpu_val);
__raw_writel(hbus_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
__raw_writel(cpu_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
hclk.rate = 0;
}
__raw_writel(1 << clk->bypass_shift,
clk->bypass_reg + shift);
} else
__raw_writel(1 << clk->bypass_shift,
clk->bypass_reg + shift);
}
#endif
__raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
ret = 0;
}
@ -640,7 +663,7 @@ static struct clk osc_24M = {
static struct clk pll_clk = {
.parent = &osc_24M,
.enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
.enable_shift = 16,
.enable_wait = 10,
.flags = FIXED_RATE | ENABLED,
@ -650,11 +673,11 @@ static struct clk pll_clk = {
static struct clk cpu_clk = {
.parent = &pll_clk,
.scale_reg = HW_CLKCTRL_FRAC_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.scale_shift = 0,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 7,
.busy_reg = HW_CLKCTRL_CPU_ADDR,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
.busy_bit = 28,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &cpu_ops,
@ -662,10 +685,10 @@ static struct clk cpu_clk = {
static struct clk io_clk = {
.parent = &pll_clk,
.enable_reg = HW_CLKCTRL_FRAC_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.enable_shift = 31,
.enable_negate = 1,
.scale_reg = HW_CLKCTRL_FRAC_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.scale_shift = 24,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &io_ops,
@ -673,10 +696,10 @@ static struct clk io_clk = {
static struct clk hclk = {
.parent = &cpu_clk,
.scale_reg = HW_CLKCTRL_HBUS_ADDR,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 7,
.busy_reg = HW_CLKCTRL_HBUS_ADDR,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
.busy_bit = 29,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &hbus_ops,
@ -684,8 +707,8 @@ static struct clk hclk = {
static struct clk xclk = {
.parent = &osc_24M,
.scale_reg = HW_CLKCTRL_XBUS_ADDR,
.busy_reg = HW_CLKCTRL_XBUS_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
.busy_bit = 31,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &xbus_ops,
@ -693,7 +716,7 @@ static struct clk xclk = {
static struct clk uart_clk = {
.parent = &xclk,
.enable_reg = HW_CLKCTRL_XTAL_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 31,
.enable_negate = 1,
.flags = ENABLED,
@ -702,7 +725,7 @@ static struct clk uart_clk = {
static struct clk audio_clk = {
.parent = &xclk,
.enable_reg = HW_CLKCTRL_XTAL_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 30,
.enable_negate = 1,
.ops = &min_ops,
@ -710,7 +733,7 @@ static struct clk audio_clk = {
static struct clk pwm_clk = {
.parent = &xclk,
.enable_reg = HW_CLKCTRL_XTAL_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 29,
.enable_negate = 1,
.ops = &min_ops,
@ -718,7 +741,7 @@ static struct clk pwm_clk = {
static struct clk dri_clk = {
.parent = &xclk,
.enable_reg = HW_CLKCTRL_XTAL_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 28,
.enable_negate = 1,
.ops = &min_ops,
@ -726,7 +749,7 @@ static struct clk dri_clk = {
static struct clk digctl_clk = {
.parent = &xclk,
.enable_reg = HW_CLKCTRL_XTAL_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 27,
.enable_negate = 1,
.ops = &min_ops,
@ -734,7 +757,7 @@ static struct clk digctl_clk = {
static struct clk timer_clk = {
.parent = &xclk,
.enable_reg = HW_CLKCTRL_XTAL_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 26,
.enable_negate = 1,
.flags = ENABLED,
@ -743,13 +766,13 @@ static struct clk timer_clk = {
static struct clk lcdif_clk = {
.parent = &pll_clk,
.scale_reg = HW_CLKCTRL_PIX_ADDR,
.busy_reg = HW_CLKCTRL_PIX_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
.busy_bit = 29,
.enable_reg = HW_CLKCTRL_PIX_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 1,
.flags = NEEDS_SET_PARENT,
.ops = &lcdif_ops,
@ -757,12 +780,12 @@ static struct clk lcdif_clk = {
static struct clk ssp_clk = {
.parent = &io_clk,
.scale_reg = HW_CLKCTRL_SSP_ADDR,
.busy_reg = HW_CLKCTRL_SSP_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
.busy_bit = 29,
.enable_reg = HW_CLKCTRL_SSP_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
.enable_shift = 31,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 5,
.enable_negate = 1,
.flags = NEEDS_SET_PARENT,
@ -771,13 +794,13 @@ static struct clk ssp_clk = {
static struct clk gpmi_clk = {
.parent = &io_clk,
.scale_reg = HW_CLKCTRL_GPMI_ADDR,
.busy_reg = HW_CLKCTRL_GPMI_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
.busy_bit = 29,
.enable_reg = HW_CLKCTRL_GPMI_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 4,
.flags = NEEDS_SET_PARENT,
.ops = &std_ops,
@ -785,7 +808,7 @@ static struct clk gpmi_clk = {
static struct clk spdif_clk = {
.parent = &pll_clk,
.enable_reg = HW_CLKCTRL_SPDIF_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
.enable_shift = 31,
.enable_negate = 1,
.ops = &min_ops,
@ -793,14 +816,14 @@ static struct clk spdif_clk = {
static struct clk emi_clk = {
.parent = &pll_clk,
.enable_reg = HW_CLKCTRL_EMI_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
.enable_shift = 31,
.enable_negate = 1,
.scale_reg = HW_CLKCTRL_FRAC_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.scale_shift = 8,
.busy_reg = HW_CLKCTRL_EMI_ADDR,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
.busy_bit = 28,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 6,
.flags = ENABLED,
.ops = &emi_ops,
@ -808,37 +831,37 @@ static struct clk emi_clk = {
static struct clk ir_clk = {
.parent = &io_clk,
.enable_reg = HW_CLKCTRL_IR_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 3,
.ops = &min_ops,
};
static struct clk saif_clk = {
.parent = &pll_clk,
.scale_reg = HW_CLKCTRL_SAIF_ADDR,
.busy_reg = HW_CLKCTRL_SAIF_ADDR,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
.busy_bit = 29,
.enable_reg = HW_CLKCTRL_SAIF_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 0,
.ops = &std_ops,
};
static struct clk usb_clk = {
.parent = &pll_clk,
.enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
.enable_shift = 18,
.enable_negate = 1,
.ops = &min_ops,
};
/* list of all the clocks */
static __initdata struct clk_lookup onchip_clks[] = {
static struct clk_lookup onchip_clks[] = {
{
.con_id = "osc_24M",
.clk = &osc_24M,

3
arch/arm/plat-stmp3xxx/core.c
Просмотреть файл

@ -20,6 +20,7 @@
#include <linux/io.h>
#include <mach/stmp3xxx.h>
#include <mach/platform.h>
#include <mach/dma.h>
#include <mach/regs-clkctrl.h>
@ -121,7 +122,7 @@ struct platform_device stmp3xxx_dbguart = {
void __init stmp3xxx_init(void)
{
/* Turn off auto-slow and other tricks */
HW_CLKCTRL_HBUS_CLR(0x07f00000U);
stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
stmp3xxx_dma_init();
}

137
arch/arm/plat-stmp3xxx/dma.c
Просмотреть файл

@ -23,6 +23,7 @@
#include <asm/page.h>
#include <mach/platform.h>
#include <mach/dma.h>
#include <mach/regs-apbx.h>
#include <mach/regs-apbh.h>
@ -35,16 +36,6 @@ static struct stmp3xxx_dma_user {
const char *name;
} channels[MAX_DMA_CHANNELS];
static inline int dmach(int ch)
{
return ch % 16;
}
static inline int dmabus(int ch)
{
return ch / 16;
}
#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
#define IS_USED(ch) (channels[ch].inuse)
@ -101,17 +92,19 @@ int stmp3xxx_dma_read_semaphore(int channel)
{
int sem = -1;
switch (dmabus(channel)) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
sem =
(HW_APBH_CHn_SEMA_RD(dmach(channel)) &
BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE;
sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
STMP3XXX_DMA_CHANNEL(channel) * 0x70);
sem &= BM_APBH_CHn_SEMA_PHORE;
sem >>= BP_APBH_CHn_SEMA_PHORE;
break;
case STMP3XXX_BUS_APBX:
sem =
(HW_APBX_CHn_SEMA_RD(dmach(channel)) &
BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE;
sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
STMP3XXX_DMA_CHANNEL(channel) * 0x70);
sem &= BM_APBX_CHn_SEMA_PHORE;
sem >>= BP_APBX_CHn_SEMA_PHORE;
break;
default:
BUG();
@ -189,39 +182,44 @@ EXPORT_SYMBOL(stmp3xxx_dma_free_command);
void stmp3xxx_dma_go(int channel,
struct stmp3xxx_dma_descriptor *head, u32 semaphore)
{
int ch = dmach(channel);
int ch = STMP3XXX_DMA_CHANNEL(channel);
void __iomem *c, *s;
switch (dmabus(channel)) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
/* Set next command */
HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle);
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
HW_APBH_CHn_SEMA_WR(ch, semaphore);
c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
break;
case STMP3XXX_BUS_APBX:
/* Set next command */
HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle);
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
HW_APBX_CHn_SEMA_WR(ch, semaphore);
c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
break;
default:
return;
}
/* Set next command */
__raw_writel(head->handle, c);
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
__raw_writel(semaphore, s);
}
EXPORT_SYMBOL(stmp3xxx_dma_go);
int stmp3xxx_dma_running(int channel)
{
switch (dmabus(channel)) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
return HW_APBH_CHn_SEMA_RD(dmach(channel)) &
BM_APBH_CHn_SEMA_PHORE;
return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
BM_APBH_CHn_SEMA_PHORE;
case STMP3XXX_BUS_APBX:
return HW_APBX_CHn_SEMA_RD(dmach(channel)) &
BM_APBX_CHn_SEMA_PHORE;
return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
BM_APBX_CHn_SEMA_PHORE;
default:
BUG();
return 0;
@ -238,7 +236,7 @@ void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
for (i = 0; i < chain->total_count; i++)
stmp3xxx_dma_free_command(
STMP3xxx_DMA(chain->channel, chain->bus),
STMP3XXX_DMA(chain->channel, chain->bus),
&chain->chain[i]);
}
EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
@ -291,16 +289,15 @@ int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
chain->free_count = items;
chain->active_count = 0;
chain->cooked_count = 0;
chain->bus = dmabus(ch);
chain->channel = dmach(ch);
chain->bus = STMP3XXX_DMA_BUS(ch);
chain->channel = STMP3XXX_DMA_CHANNEL(ch);
return err;
}
EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
{
BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) >
0);
BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
chain->free_index = 0;
chain->active_index = 0;
chain->cooked_index = 0;
@ -325,6 +322,8 @@ EXPORT_SYMBOL(stmp37xx_circ_advance_free);
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
unsigned count)
{
void __iomem *c;
u32 mask_clr, mask;
BUG_ON(chain->free_count < count);
chain->free_count -= count;
@ -334,26 +333,24 @@ void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
switch (chain->bus) {
case STMP3XXX_BUS_APBH:
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
HW_APBH_CHn_SEMA_CLR(chain->channel,
BM_APBH_CHn_SEMA_INCREMENT_SEMA);
HW_APBH_CHn_SEMA_SET(chain->channel,
BF_APBH_CHn_SEMA_INCREMENT_SEMA(count));
c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
break;
case STMP3XXX_BUS_APBX:
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
HW_APBX_CHn_SEMA_CLR(chain->channel,
BM_APBX_CHn_SEMA_INCREMENT_SEMA);
HW_APBX_CHn_SEMA_SET(chain->channel,
BF_APBX_CHn_SEMA_INCREMENT_SEMA(count));
c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
break;
default:
BUG();
return;
}
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
stmp3xxx_clearl(mask_clr, c);
stmp3xxx_setl(mask, c);
}
EXPORT_SYMBOL(stmp37xx_circ_advance_active);
@ -362,7 +359,7 @@ unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
unsigned cooked;
cooked = chain->active_count -
stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus));
stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
chain->active_count -= cooked;
chain->active_index += cooked;
@ -383,38 +380,41 @@ void stmp3xxx_dma_set_alt_target(int channel, int function)
#else
#error wrong arch
#endif
int shift = dmach(channel) * bits;
int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
unsigned mask = (1<<bits) - 1;
void __iomem *c;
BUG_ON(function < 0 || function >= (1<<bits));
pr_debug("%s: channel = %d, using mask %x, "
"shift = %d\n", __func__, channel, mask, shift);
switch (dmabus(channel)) {
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
HW_APBH_DEVSEL_CLR(mask<<shift);
HW_APBH_DEVSEL_SET(function<<shift);
c = REGS_APBH_BASE + HW_APBH_DEVSEL;
break;
case STMP3XXX_BUS_APBX:
HW_APBX_DEVSEL_CLR(mask<<shift);
HW_APBX_DEVSEL_SET(function<<shift);
c = REGS_APBX_BASE + HW_APBX_DEVSEL;
break;
default:
BUG();
}
stmp3xxx_clearl(mask << shift, c);
stmp3xxx_setl(mask << shift, c);
}
EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
void stmp3xxx_dma_suspend(void)
{
HW_APBH_CTRL0_SET(BM_APBH_CTRL0_CLKGATE);
HW_APBX_CTRL0_SET(BM_APBX_CTRL0_CLKGATE);
stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
}
void stmp3xxx_dma_resume(void)
{
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST);
HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST);
stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
REGS_APBH_BASE + HW_APBH_CTRL0);
stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
REGS_APBX_BASE + HW_APBX_CTRL0);
}
#ifdef CONFIG_CPU_FREQ
@ -452,11 +452,12 @@ static struct dma_notifier_block dma_cpufreq_nb = {
void __init stmp3xxx_dma_init(void)
{
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST);
HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST);
stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
REGS_APBH_BASE + HW_APBH_CTRL0);
stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
REGS_APBX_BASE + HW_APBX_CTRL0);
#ifdef CONFIG_CPU_FREQ
cpufreq_register_notifier(&dma_cpufreq_nb.nb,
CPUFREQ_TRANSITION_NOTIFIER);
#endif /* CONFIG_CPU_FREQ */
}

16
arch/arm/plat-stmp3xxx/include/mach/dma.h
Просмотреть файл

@ -25,16 +25,14 @@
#define MAX_PIO_WORDS (15)
#endif
#define STMP3XXX_BUS_APBH 0
#define STMP3XXX_BUS_APBX 1
#define STMP3XXX_BUS_APBH 0
#define STMP3XXX_BUS_APBX 1
#define STMP3XXX_DMA_MAX_CHANNEL 16
#define STMP3xxx_DMA(channel, bus) ((bus) * 16 + (channel))
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 32
#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 32
struct stmp3xxx_dma_command {
u32 next;

7
arch/arm/plat-stmp3xxx/include/mach/pinmux.h
Просмотреть файл

@ -146,10 +146,9 @@ struct stmp3xxx_pinmux_bank {
u8 strengths[HW_DRIVE_PINDRV_NUM];
/* GPIO things */
void __iomem *hw_gpio_read,
*hw_gpio_set,
*hw_gpio_clr,
*hw_gpio_doe;
void __iomem *hw_gpio_in,
*hw_gpio_out,
*hw_gpio_doe;
int irq, virq;
};

21
arch/arm/plat-stmp3xxx/include/mach/platform.h
Просмотреть файл

@ -14,6 +14,9 @@
#ifndef __ASM_PLAT_PLATFORM_H
#define __ASM_PLAT_PLATFORM_H
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
#include <asm/sizes.h>
/* Virtual address where registers are mapped */
@ -44,4 +47,22 @@
#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
#endif
#define HW_STMP3XXX_SET 0x04
#define HW_STMP3XXX_CLR 0x08
#define HW_STMP3XXX_TOG 0x0c
#ifndef __ASSEMBLER__
static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
{
__raw_writel(v, r + HW_STMP3XXX_CLR);
}
static inline void stmp3xxx_setl(u32 v, void __iomem *r)
{
__raw_writel(v, r + HW_STMP3XXX_SET);
}
#endif
#define BF(value, field) (((value) << BP_##field) & BM_##field)
#endif /* __ASM_ARCH_PLATFORM_H */

195
arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h
Просмотреть файл

@ -1,195 +0,0 @@
/*
* Freescale STMP37XX/STMP378X SoC register access interfaces
*
* The SoC registers may be accessed via:
*
* - single 32 bit address, or
* - four 32 bit addresses - general purpose, set, clear and toggle bits
*
* Multiple IP blocks (e.g. SSP, UART) provide identical register sets per
* each module
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_STMP3XXX_REGS_H
#define __ASM_PLAT_STMP3XXX_REGS_H
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
#include "platform.h"
#define REGS_BASE STMP3XXX_REGS_BASE
#define HW_STMP3xxx_SET 0x04
#define HW_STMP3xxx_CLR 0x08
#define HW_STMP3xxx_TOG 0x0c
#ifndef __ASSEMBLER__
#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \
static const u32 id##_OFFSET = offset; \
static inline u32 id##_RD_NB(const void __iomem *regbase) { \
if (!rd) \
printk(KERN_ERR"%s: cannot READ at %p+%x\n", \
#id, regbase, offset); \
return __raw_readl(regbase + offset); \
} \
static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \
#id, regbase, offset); \
__raw_writel(v, regbase + offset); \
} \
static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot SET at %p+%x\n", \
#id, regbase, offset); \
if (regset) \
__raw_writel(v, regbase + \
offset + HW_STMP3xxx_SET); \
else \
__raw_writel(v | __raw_readl(regbase + offset), \
regbase + offset); \
} \
static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \
#id, regbase, offset); \
if (regset) \
__raw_writel(v, regbase + \
offset + HW_STMP3xxx_CLR); \
else \
__raw_writel( \
~v & __raw_readl(regbase + offset), \
regbase + offset); \
} \
static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \
#id, regbase, offset); \
if (regset) \
__raw_writel(v, regbase + \
offset + HW_STMP3xxx_TOG); \
else \
__raw_writel(v ^ __raw_readl(regbase + offset), \
regbase + offset); \
} \
static inline u32 id##_RD(void) { return id##_RD_NB(base); } \
static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \
static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \
static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \
static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); }
#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\
static inline u32 id##_OFFSET(int i) { \
return offset + i * step; \
} \
static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\
if (!rd) \
printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \
#id, i, regbase, offset + i * step); \
return __raw_readl(regbase + offset + i * step); \
} \
static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\
#id, i, regbase, offset + i * step); \
__raw_writel(v, regbase + offset + i * step); \
} \
static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \
#id, i, regbase, offset + i * step); \
if (regset) \
__raw_writel(v, regbase + offset + \
i * step + HW_STMP3xxx_SET); \
else \
__raw_writel(v | __raw_readl(regbase + \
offset + i * step), \
regbase + offset + i * step); \
} \
static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \
#id, i, regbase, offset + i * step); \
if (regset) \
__raw_writel(v, regbase + offset + \
i * step + HW_STMP3xxx_CLR); \
else \
__raw_writel(~v & __raw_readl(regbase + \
offset + i * step), \
regbase + offset + i * step); \
} \
static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \
#id, i, regbase, offset + i * step); \
if (regset) \
__raw_writel(v, regbase + offset + \
i * step + HW_STMP3xxx_TOG); \
else \
__raw_writel(v ^ __raw_readl(regbase + offset \
+ i * step), \
regbase + offset + i * step); \
} \
static inline u32 id##_RD(int i) \
{ \
return id##_RD_NB(base, i); \
} \
static inline void id##_WR(int i, u32 v) \
{ \
id##_WR_NB(base, i, v); \
} \
static inline void id##_SET(int i, u32 v) \
{ \
id##_SET_NB(base, i, v); \
} \
static inline void id##_CLR(int i, u32 v) \
{ \
id##_CLR_NB(base, i, v); \
} \
static inline void id##_TOG(int i, u32 v) \
{ \
id##_TOG_NB(base, i, v); \
}
#define HW_REGISTER_WO(id, base, offset)\
HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1)
#define HW_REGISTER_RO(id, base, offset)\
HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0)
#define HW_REGISTER(id, base, offset) \
HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1)
#define HW_REGISTER_0(id, base, offset) \
HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1)
#define HW_REGISTER_INDEXED(id, base, offset, step) \
HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step)
#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \
HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step)
#define HW_REGISTER_0_INDEXED(id, base, offset, step) \
HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step)
#else /* __ASSEMBLER__ */
#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)
#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)
#define HW_REGISTER_WO(id, base, offset)
#define HW_REGISTER_RO(id, base, offset)
#define HW_REGISTER(id, base, offset)
#define HW_REGISTER_0(id, base, offset)
#define HW_REGISTER_INDEXED(id, base, offset, step)
#define HW_REGISTER_RO_INDEXED(id, base, offset, step)
#define HW_REGISTER_0_INDEXED(id, base, offset, step)
#endif /* __ASSEMBLER__ */
#endif /* __ASM_PLAT_STMP3XXX_REGS_H */

8
arch/arm/plat-stmp3xxx/include/mach/system.h
Просмотреть файл

@ -17,6 +17,7 @@
#define __ASM_ARCH_SYSTEM_H
#include <asm/proc-fns.h>
#include <mach/platform.h>
#include <mach/regs-clkctrl.h>
#include <mach/regs-power.h>
@ -33,13 +34,14 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode, const char *cmd)
{
/* Set BATTCHRG to default value */
HW_POWER_CHARGE_WR(0x00010000);
__raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
/* Set MINPWR to default value */
HW_POWER_MINPWR_WR(0);
__raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
/* Reset digital side of chip (but not power or RTC) */
HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG);
__raw_writel(BM_CLKCTRL_RESET_DIG,
REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
/* Should not return */
}

22
arch/arm/plat-stmp3xxx/irq.c
Просмотреть файл

@ -22,21 +22,15 @@
#include <linux/sysdev.h>
#include <mach/stmp3xxx.h>
#include <mach/platform.h>
#include <mach/regs-icoll.h>
void __init stmp3xxx_init_irq(struct irq_chip *chip)
{
unsigned int i;
unsigned int i, lv;
/* Reset the interrupt controller */
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE);
udelay(10);
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST);
udelay(10);
HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST);
while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE))
continue;
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE);
stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
/* Disable all interrupts initially */
for (i = 0; i < NR_REAL_IRQS; i++) {
@ -47,13 +41,11 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
}
/* Ensure vector is cleared */
HW_ICOLL_LEVELACK_WR(1);
HW_ICOLL_LEVELACK_WR(2);
HW_ICOLL_LEVELACK_WR(4);
HW_ICOLL_LEVELACK_WR(8);
for (lv = 0; lv < 4; lv++)
__raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
HW_ICOLL_VECTOR_WR(0);
/* Barrier */
(void) HW_ICOLL_STAT_RD();
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
}

163
arch/arm/plat-stmp3xxx/pinmux.c
Просмотреть файл

@ -15,6 +15,7 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
@ -25,6 +26,7 @@
#include <linux/irq.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <mach/regs-pinctrl.h>
#include <mach/pins.h>
#include <mach/pinmux.h>
@ -33,97 +35,94 @@
static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
[0] = {
.hw_muxsel = {
HW_PINCTRL_MUXSEL0_ADDR,
HW_PINCTRL_MUXSEL1_ADDR
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
},
.hw_drive = {
HW_PINCTRL_DRIVE0_ADDR,
HW_PINCTRL_DRIVE1_ADDR,
HW_PINCTRL_DRIVE2_ADDR,
HW_PINCTRL_DRIVE3_ADDR
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
},
.hw_pull = HW_PINCTRL_PULL0_ADDR,
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
.functions = { 0x0, 0x1, 0x2, 0x3 },
.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
.hw_gpio_read = HW_PINCTRL_DIN0_ADDR,
.hw_gpio_set = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_SET,
.hw_gpio_clr = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_CLR,
.hw_gpio_doe = HW_PINCTRL_DOE0_ADDR,
.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
.irq = IRQ_GPIO0,
.pin2irq = HW_PINCTRL_PIN2IRQ0_ADDR,
.irqstat = HW_PINCTRL_IRQSTAT0_ADDR,
.irqlevel = HW_PINCTRL_IRQLEVEL0_ADDR,
.irqpolarity = HW_PINCTRL_IRQPOL0_ADDR,
.irqen = HW_PINCTRL_IRQEN0_ADDR,
.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
},
[1] = {
.hw_muxsel = {
HW_PINCTRL_MUXSEL2_ADDR,
HW_PINCTRL_MUXSEL3_ADDR
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
},
.hw_drive = {
HW_PINCTRL_DRIVE4_ADDR,
HW_PINCTRL_DRIVE5_ADDR,
HW_PINCTRL_DRIVE6_ADDR,
HW_PINCTRL_DRIVE7_ADDR
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
},
.hw_pull = HW_PINCTRL_PULL1_ADDR,
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
.functions = { 0x0, 0x1, 0x2, 0x3 },
.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
.hw_gpio_read = HW_PINCTRL_DIN1_ADDR,
.hw_gpio_set = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_SET,
.hw_gpio_clr = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_CLR,
.hw_gpio_doe = HW_PINCTRL_DOE1_ADDR,
.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
.irq = IRQ_GPIO1,
.pin2irq = HW_PINCTRL_PIN2IRQ1_ADDR,
.irqstat = HW_PINCTRL_IRQSTAT1_ADDR,
.irqlevel = HW_PINCTRL_IRQLEVEL1_ADDR,
.irqpolarity = HW_PINCTRL_IRQPOL1_ADDR,
.irqen = HW_PINCTRL_IRQEN1_ADDR,
.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
},
[2] = {
.hw_muxsel = {
HW_PINCTRL_MUXSEL4_ADDR,
HW_PINCTRL_MUXSEL5_ADDR,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
},
.hw_drive = {
HW_PINCTRL_DRIVE8_ADDR,
HW_PINCTRL_DRIVE9_ADDR,
HW_PINCTRL_DRIVE10_ADDR,
HW_PINCTRL_DRIVE11_ADDR,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
},
.hw_pull = HW_PINCTRL_PULL2_ADDR,
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
.functions = { 0x0, 0x1, 0x2, 0x3 },
.strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
.hw_gpio_read = HW_PINCTRL_DIN2_ADDR,
.hw_gpio_set = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_SET,
.hw_gpio_clr = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_CLR,
.hw_gpio_doe = HW_PINCTRL_DOE2_ADDR,
.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
.irq = IRQ_GPIO2,
.pin2irq = HW_PINCTRL_PIN2IRQ2_ADDR,
.irqstat = HW_PINCTRL_IRQSTAT2_ADDR,
.irqlevel = HW_PINCTRL_IRQLEVEL2_ADDR,
.irqpolarity = HW_PINCTRL_IRQPOL2_ADDR,
.irqen = HW_PINCTRL_IRQEN2_ADDR,
.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
},
[3] = {
.hw_muxsel = {
HW_PINCTRL_MUXSEL6_ADDR,
HW_PINCTRL_MUXSEL7_ADDR,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
},
.hw_drive = {
HW_PINCTRL_DRIVE12_ADDR,
HW_PINCTRL_DRIVE13_ADDR,
HW_PINCTRL_DRIVE14_ADDR,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
NULL,
},
.hw_pull = HW_PINCTRL_PULL3_ADDR,
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
.functions = {0x0, 0x1, 0x2, 0x3},
.strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
},
@ -196,8 +195,8 @@ void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
val << shift, hwdrive);
__raw_writel(HW_DRIVE_PINDRV_MASK << shift, hwdrive + HW_STMP3xxx_CLR);
__raw_writel(val << shift, hwdrive + HW_STMP3xxx_SET);
stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
stmp3xxx_setl(val << shift, hwdrive);
}
void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
@ -221,11 +220,9 @@ void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
pr_debug("%s: changing 0x%x bit in 0x%p register\n",
__func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
if (voltage == PIN_1_8V)
__raw_writel(HW_DRIVE_PINV_MASK << shift,
hwdrive + HW_STMP3xxx_CLR);
stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
else
__raw_writel(HW_DRIVE_PINV_MASK << shift,
hwdrive + HW_STMP3xxx_SET);
stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
}
void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
@ -245,8 +242,10 @@ void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
pr_debug("%s: changing 0x%x bit in 0x%p register\n",
__func__, 1 << pin, hwpull);
__raw_writel(1 << pin,
hwpull + (enable ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR));
if (enable)
stmp3xxx_setl(1 << pin, hwpull);
else
stmp3xxx_clearl(1 << pin, hwpull);
}
int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
@ -290,8 +289,8 @@ void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
pr_debug("%s: writing 0x%x to 0x%p register\n",
__func__, val << shift, hwmux);
__raw_writel(HW_MUXSEL_PINFUN_MASK << shift, hwmux + HW_STMP3xxx_CLR);
__raw_writel(val << shift, hwmux + HW_STMP3xxx_SET);
stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
stmp3xxx_setl(val << shift, hwmux);
}
void stmp3xxx_release_pin(unsigned id, const char *label)
@ -388,10 +387,15 @@ static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
__func__, type);
return -ENXIO;
}
__raw_writel(1 << gpio,
pm->irqlevel + (l ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR));
__raw_writel(1 << gpio,
pm->irqpolarity + (p ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR));
if (l)
stmp3xxx_setl(1 << gpio, pm->irqlevel);
else
stmp3xxx_clearl(1 << gpio, pm->irqlevel);
if (p)
stmp3xxx_setl(1 << gpio, pm->irqpolarity);
else
stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
return 0;
}
@ -402,8 +406,8 @@ static void stmp3xxx_pin_ack_irq(unsigned irq)
unsigned gpio;
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
stat = __raw_readl(pm->irqstat) & (1<<gpio);
__raw_writel(stat, pm->irqstat + HW_STMP3xxx_CLR);
stat = __raw_readl(pm->irqstat) & (1 << gpio);
stmp3xxx_clearl(stat, pm->irqstat);
}
static void stmp3xxx_pin_mask_irq(unsigned irq)
@ -412,8 +416,8 @@ static void stmp3xxx_pin_mask_irq(unsigned irq)
unsigned gpio;
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
__raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_CLR);
__raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_CLR);
stmp3xxx_clearl(1 << gpio, pm->irqen);
stmp3xxx_clearl(1 << gpio, pm->pin2irq);
}
static void stmp3xxx_pin_unmask_irq(unsigned irq)
@ -422,8 +426,8 @@ static void stmp3xxx_pin_unmask_irq(unsigned irq)
unsigned gpio;
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
__raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_SET);
__raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_SET);
stmp3xxx_setl(1 << gpio, pm->irqen);
stmp3xxx_setl(1 << gpio, pm->pin2irq);
}
static inline
@ -443,7 +447,7 @@ static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
unsigned v;
v = __raw_readl(pm->hw_gpio_read) & (1 << offset);
v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
return v ? 1 : 0;
}
@ -451,14 +455,17 @@ static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
__raw_writel(1 << offset, v ? pm->hw_gpio_set : pm->hw_gpio_clr);
if (v)
stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
else
stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
}
static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
__raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_SET);
stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
stmp3xxx_gpio_set(chip, offset, v);
return 0;
}
@ -467,7 +474,7 @@ static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
__raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_CLR);
stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
return 0;
}

107
arch/arm/plat-stmp3xxx/timer.c
Просмотреть файл

@ -26,6 +26,7 @@
#include <asm/mach/time.h>
#include <mach/stmp3xxx.h>
#include <mach/platform.h>
#include <mach/regs-timrot.h>
static irqreturn_t
@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) {
HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
/* timer 0 */
if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
BM_TIMROT_TIMCTRLn_IRQ) {
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
c->event_handler(c);
} else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) {
HW_TIMROT_TIMCTRLn_CLR(1, (1<<15));
HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN);
HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF);
}
/* timer 1 */
else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
& BM_TIMROT_TIMCTRLn_IRQ) {
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
}
return IRQ_HANDLED;
@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
{
return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16);
return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
& 0xFFFF0000) >> 16);
}
static int
stmp3xxx_timrot_set_next_event(unsigned long delta,
struct clock_event_device *dev)
{
HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */
/* reload the timer */
__raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
return 0;
}
@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void)
ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
ckevt_timrot.cpumask = cpumask_of(0);
HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
BM_TIMROT_ROTCTRL_CLKGATE);
HW_TIMROT_TIMCOUNTn_WR(0, 0);
HW_TIMROT_TIMCOUNTn_WR(1, 0);
stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
HW_TIMROT_TIMCTRLn_WR(0,
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN));
HW_TIMROT_TIMCTRLn_WR(1,
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE));
/* clear two timers */
__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
/* configure them */
__raw_writel(
(8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
__raw_writel(
(8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
__raw_writel(CLOCK_TICK_RATE / HZ - 1,
REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void)
void stmp3xxx_suspend_timer(void)
{
HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN);
HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE);
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
}
void stmp3xxx_resume_timer(void)
{
HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
BM_TIMROT_ROTCTRL_CLKGATE);
HW_TIMROT_TIMCTRLn_WR(0,
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN));
HW_TIMROT_TIMCTRLn_WR(1,
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE));
HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
__raw_writel(
8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
__raw_writel(
8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
__raw_writel(CLOCK_TICK_RATE / HZ - 1,
REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
}
#else