clk: tegra: fix clk_out parents list
Number of parents for clk_out_2 and clk_out_3 was incorrectly set to clk_out1_parents. Even though it did not break anything since the size was same better to fix. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -1602,7 +1602,7 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
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/* clk_out_2 */
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clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
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ARRAY_SIZE(clk_out1_parents), 0,
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ARRAY_SIZE(clk_out2_parents), 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
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&clk_out_lock);
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clks[clk_out_2_mux] = clk;
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@ -1614,7 +1614,7 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
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/* clk_out_3 */
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clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
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ARRAY_SIZE(clk_out1_parents), 0,
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ARRAY_SIZE(clk_out3_parents), 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
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&clk_out_lock);
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clks[clk_out_3_mux] = clk;
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@ -1223,7 +1223,7 @@ static void __init tegra30_pmc_clk_init(void)
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/* clk_out_2 */
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clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
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ARRAY_SIZE(clk_out1_parents), 0,
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ARRAY_SIZE(clk_out2_parents), 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
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&clk_out_lock);
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clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
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@ -1234,7 +1234,7 @@ static void __init tegra30_pmc_clk_init(void)
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/* clk_out_3 */
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clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
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ARRAY_SIZE(clk_out1_parents), 0,
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ARRAY_SIZE(clk_out3_parents), 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
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&clk_out_lock);
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clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
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