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mt76: mt7915: add support for MT7986 

This adds MT7986 SoC integrated multi-band 4x4 WiFi 6/6E.

Co-developed-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Co-developed-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Bo Jiao 2022-02-09 14:11:56 +08:00 коммит произвёл Felix Fietkau
Родитель 56bd1c86e0
Коммит 99ad32a4ca
15 изменённых файлов: 1817 добавлений и 80 удалений
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5
drivers/net/wireless/mediatek/mt76/mt76_connac.h
Просмотреть файл

@ -117,6 +117,11 @@ static inline bool is_mt7916(struct mt76_dev *dev)
return mt76_chip(dev) == 0x7906;
}
static inline bool is_mt7986(struct mt76_dev *dev)
{
return mt76_chip(dev) == 0x7986;
}
static inline bool is_mt7622(struct mt76_dev *dev)
{
if (!IS_ENABLED(CONFIG_MT7622_WMAC))

10
drivers/net/wireless/mediatek/mt76/mt7915/Kconfig
Просмотреть файл

@ -12,3 +12,13 @@ config MT7915E
OFDMA, spatial reuse and dual carrier modulation.
To compile this driver as a module, choose M here.
config MT7986_WMAC
bool "MT7986 (SoC) WMAC support"
depends on MT7915E
depends on ARCH_MEDIATEK || COMPILE_TEST
select REGMAP
help
This adds support for the built-in WMAC on MT7986 SoC device
which has the same feature set as a MT7915, but enables 6E
support.

1
drivers/net/wireless/mediatek/mt76/mt7915/Makefile
Просмотреть файл

@ -6,3 +6,4 @@ mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
debugfs.o mmio.o
mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
mt7915e-$(CONFIG_MT7986_WMAC) += soc.o

59
drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
Просмотреть файл

@ -36,27 +36,48 @@ static int mt7915_check_eeprom(struct mt7915_dev *dev)
switch (val) {
case 0x7915:
case 0x7916:
case 0x7986:
return 0;
default:
return -EINVAL;
}
}
static char *mt7915_eeprom_name(struct mt7915_dev *dev)
{
switch (mt76_chip(&dev->mt76)) {
case 0x7915:
return dev->dbdc_support ?
MT7915_EEPROM_DEFAULT_DBDC : MT7915_EEPROM_DEFAULT;
case 0x7986:
switch (mt7915_check_adie(dev, true)) {
case MT7976_ONE_ADIE_DBDC:
return MT7986_EEPROM_MT7976_DEFAULT_DBDC;
case MT7975_ONE_ADIE:
return MT7986_EEPROM_MT7975_DEFAULT;
case MT7976_ONE_ADIE:
return MT7986_EEPROM_MT7976_DEFAULT;
case MT7975_DUAL_ADIE:
return MT7986_EEPROM_MT7975_DUAL_DEFAULT;
case MT7976_DUAL_ADIE:
return MT7986_EEPROM_MT7976_DUAL_DEFAULT;
default:
break;
}
return NULL;
default:
return MT7916_EEPROM_DEFAULT;
}
}
static int
mt7915_eeprom_load_default(struct mt7915_dev *dev)
{
char *default_bin = MT7915_EEPROM_DEFAULT;
u8 *eeprom = dev->mt76.eeprom.data;
const struct firmware *fw = NULL;
int ret;
if (dev->dbdc_support)
default_bin = MT7915_EEPROM_DEFAULT_DBDC;
if (!is_mt7915(&dev->mt76))
default_bin = MT7916_EEPROM_DEFAULT;
ret = request_firmware(&fw, default_bin, dev->mt76.dev);
ret = request_firmware(&fw, mt7915_eeprom_name(dev), dev->mt76.dev);
if (ret)
return ret;
@ -135,7 +156,7 @@ static void mt7915_eeprom_parse_band_config(struct mt7915_phy *phy)
void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
struct mt7915_phy *phy)
{
u8 nss, nss_band, *eeprom = dev->mt76.eeprom.data;
u8 nss, nss_band, nss_band_max, *eeprom = dev->mt76.eeprom.data;
struct mt76_phy *mphy = phy->mt76;
bool ext_phy = phy != &dev->phy;
@ -155,6 +176,7 @@ void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
/* read tx/rx stream */
nss_band = nss;
if (dev->dbdc_support) {
if (is_mt7915(&dev->mt76)) {
nss_band = FIELD_GET(MT_EE_WIFI_CONF3_TX_PATH_B0,
@ -167,20 +189,29 @@ void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
eeprom[MT_EE_WIFI_CONF + 2 + ext_phy]);
}
if (!nss_band || nss_band > 2)
nss_band = 2;
nss_band_max = is_mt7986(&dev->mt76) ?
MT_EE_NSS_MAX_DBDC_MA7986 : MT_EE_NSS_MAX_DBDC_MA7915;
} else {
nss_band_max = is_mt7986(&dev->mt76) ?
MT_EE_NSS_MAX_MA7986 : MT_EE_NSS_MAX_MA7915;
}
if (!nss_band || nss_band > nss_band_max)
nss_band = nss_band_max;
if (nss_band > nss) {
dev_err(dev->mt76.dev,
dev_warn(dev->mt76.dev,
"nss mismatch, nss(%d) nss_band(%d) ext_phy(%d)\n",
nss, nss_band, ext_phy);
nss = nss_band;
}
mphy->chainmask = ext_phy ? (BIT(nss_band) - 1) << 2 : (BIT(nss_band) - 1);
mphy->antenna_mask = BIT(hweight8(mphy->chainmask)) - 1;
mphy->chainmask = BIT(nss) - 1;
if (ext_phy)
mphy->chainmask <<= dev->chainshift;
mphy->antenna_mask = BIT(nss_band) - 1;
dev->chainmask |= mphy->chainmask;
dev->chainshift = hweight8(dev->mphy.chainmask);
}
int mt7915_eeprom_init(struct mt7915_dev *dev)

13
drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h
Просмотреть файл

@ -56,6 +56,19 @@ enum mt7915_eeprom_field {
#define MT_EE_RATE_DELTA_SIGN BIT(6)
#define MT_EE_RATE_DELTA_EN BIT(7)
#define MT_EE_NSS_MAX_MA7915 4
#define MT_EE_NSS_MAX_DBDC_MA7915 2
#define MT_EE_NSS_MAX_MA7986 4
#define MT_EE_NSS_MAX_DBDC_MA7986 4
enum mt7915_adie_sku {
MT7976_ONE_ADIE_DBDC = 0x7,
MT7975_ONE_ADIE = 0x8,
MT7976_ONE_ADIE = 0xa,
MT7975_DUAL_ADIE = 0xd,
MT7976_DUAL_ADIE = 0xf,
};
enum mt7915_eeprom_band {
MT_EE_BAND_SEL_DEFAULT,
MT_EE_BAND_SEL_5GHZ,

20
drivers/net/wireless/mediatek/mt76/mt7915/init.c
Просмотреть файл

@ -582,6 +582,12 @@ static void mt7915_wfsys_reset(struct mt7915_dev *dev)
mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
msleep(100);
} else if (is_mt7986(&dev->mt76)) {
mt7986_wmac_disable(dev);
msleep(20);
mt7986_wmac_enable(dev);
msleep(20);
} else {
mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
msleep(20);
@ -767,9 +773,17 @@ static int
mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
struct ieee80211_sband_iftype_data *data)
{
struct mt7915_dev *dev = phy->dev;
int i, idx = 0, nss = hweight8(phy->mt76->chainmask);
u16 mcs_map = 0;
u16 mcs_map_160 = 0;
u8 nss_160;
/* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
if (is_mt7915(&dev->mt76) && !dev->dbdc_support)
nss_160 = nss / 2;
else
nss_160 = nss;
for (i = 0; i < 8; i++) {
if (i < nss)
@ -777,8 +791,7 @@ mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
else
mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
/* Can do 1/2 of NSS streams in 160Mhz mode. */
if (i < nss / 2)
if (i < nss_160)
mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
else
mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
@ -1011,5 +1024,8 @@ void mt7915_unregister_device(struct mt7915_dev *dev)
mt7915_dma_cleanup(dev);
tasklet_disable(&dev->irq_tasklet);
if (is_mt7986(&dev->mt76))
mt7986_wmac_disable(dev);
mt76_free_device(&dev->mt76);
}

32
drivers/net/wireless/mediatek/mt76/mt7915/mac.c
Просмотреть файл

@ -1971,16 +1971,22 @@ mt7915_dma_reset(struct mt7915_dev *dev)
int i;
mt76_clear(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
MT_WFDMA0_GLO_CFG_TX_DMA_EN |
MT_WFDMA0_GLO_CFG_RX_DMA_EN);
if (is_mt7915(&dev->mt76))
mt76_clear(dev, MT_WFDMA1_GLO_CFG,
MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
MT_WFDMA1_GLO_CFG_TX_DMA_EN |
MT_WFDMA1_GLO_CFG_RX_DMA_EN);
if (dev->hif2) {
mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
(MT_WFDMA0_GLO_CFG_TX_DMA_EN |
MT_WFDMA0_GLO_CFG_RX_DMA_EN));
MT_WFDMA0_GLO_CFG_TX_DMA_EN |
MT_WFDMA0_GLO_CFG_RX_DMA_EN);
if (is_mt7915(&dev->mt76))
mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
(MT_WFDMA1_GLO_CFG_TX_DMA_EN |
MT_WFDMA1_GLO_CFG_RX_DMA_EN));
MT_WFDMA1_GLO_CFG_TX_DMA_EN |
MT_WFDMA1_GLO_CFG_RX_DMA_EN);
}
usleep_range(1000, 2000);
@ -2004,19 +2010,23 @@ mt7915_dma_reset(struct mt7915_dev *dev)
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
if (is_mt7915(&dev->mt76))
mt76_set(dev, MT_WFDMA1_GLO_CFG,
MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN |
MT_WFDMA1_GLO_CFG_TX_DMA_EN |
MT_WFDMA1_GLO_CFG_RX_DMA_EN |
MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
if (dev->hif2) {
mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
(MT_WFDMA0_GLO_CFG_TX_DMA_EN |
MT_WFDMA0_GLO_CFG_RX_DMA_EN));
MT_WFDMA0_GLO_CFG_TX_DMA_EN |
MT_WFDMA0_GLO_CFG_RX_DMA_EN);
if (is_mt7915(&dev->mt76))
mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
(MT_WFDMA1_GLO_CFG_TX_DMA_EN |
MT_WFDMA1_GLO_CFG_TX_DMA_EN |
MT_WFDMA1_GLO_CFG_RX_DMA_EN |
MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
MT_WFDMA1_GLO_CFG_OMIT_RX_INFO));
MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
}
}

9
drivers/net/wireless/mediatek/mt76/mt7915/main.c
Просмотреть файл

@ -969,12 +969,9 @@ mt7915_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
phy->mt76->antenna_mask = tx_ant;
if (ext_phy) {
if (dev->chainmask == 0xf)
tx_ant <<= 2;
else
tx_ant <<= 1;
}
if (ext_phy)
tx_ant <<= dev->chainshift;
phy->mt76->chainmask = tx_ant;
mt76_set_stream_caps(phy->mt76, true);

53
drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
Просмотреть файл

@ -64,6 +64,26 @@ struct mt7915_fw_region {
u8 reserved1[15];
} __packed;
#define fw_name(_dev, name, ...) ({ \
char *_fw; \
switch (mt76_chip(&(_dev)->mt76)) { \
case 0x7915: \
_fw = MT7915_##name; \
break; \
case 0x7986: \
_fw = MT7986_##name##__VA_ARGS__; \
break; \
default: \
_fw = MT7916_##name; \
break; \
} \
_fw; \
})
#define fw_name_var(_dev, name) (mt7915_check_adie(dev, false) ? \
fw_name(_dev, name) : \
fw_name(_dev, name, _MT7975))
#define MCU_PATCH_ADDRESS 0x200000
#define HE_PHY(p, c) u8_get_bits(c, IEEE80211_HE_PHY_##p)
@ -89,6 +109,7 @@ mt7915_mcu_set_sta_he_mcs(struct ieee80211_sta *sta, __le16 *he_mcs,
u16 mcs_map)
{
struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
struct mt7915_dev *dev = msta->vif->phy->dev;
enum nl80211_band band = msta->vif->phy->mt76->chandef.chan->band;
const u16 *mask = msta->vif->bitrate_mask.control[band].he_mcs;
int nss, max_nss = sta->rx_nss > 3 ? 4 : sta->rx_nss;
@ -129,8 +150,9 @@ mt7915_mcu_set_sta_he_mcs(struct ieee80211_sta *sta, __le16 *he_mcs,
mcs_map &= ~(0x3 << (nss * 2));
mcs_map |= mcs << (nss * 2);
/* only support 2ss on 160MHz */
if (nss > 1 && (sta->bandwidth == IEEE80211_STA_RX_BW_160))
/* only support 2ss on 160MHz for mt7915 */
if (is_mt7915(&dev->mt76) && nss > 1 &&
sta->bandwidth == IEEE80211_STA_RX_BW_160)
break;
}
@ -141,6 +163,8 @@ static void
mt7915_mcu_set_sta_vht_mcs(struct ieee80211_sta *sta, __le16 *vht_mcs,
const u16 *mask)
{
struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
struct mt7915_dev *dev = msta->vif->phy->dev;
u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
int nss, max_nss = sta->rx_nss > 3 ? 4 : sta->rx_nss;
u16 mcs;
@ -162,8 +186,9 @@ mt7915_mcu_set_sta_vht_mcs(struct ieee80211_sta *sta, __le16 *vht_mcs,
vht_mcs[nss] = cpu_to_le16(mcs & mask[nss]);
/* only support 2ss on 160MHz */
if (nss > 1 && (sta->bandwidth == IEEE80211_STA_RX_BW_160))
/* only support 2ss on 160MHz for mt7915 */
if (is_mt7915(&dev->mt76) && nss > 1 &&
sta->bandwidth == IEEE80211_STA_RX_BW_160)
break;
}
}
@ -1962,7 +1987,6 @@ static int mt7915_load_patch(struct mt7915_dev *dev)
{
const struct mt7915_patch_hdr *hdr;
const struct firmware *fw = NULL;
const char *patch;
int i, ret, sem;
sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, 1);
@ -1976,8 +2000,8 @@ static int mt7915_load_patch(struct mt7915_dev *dev)
return -EAGAIN;
}
patch = is_mt7915(&dev->mt76) ? MT7915_ROM_PATCH : MT7916_ROM_PATCH;
ret = request_firmware(&fw, patch, dev->mt76.dev);
ret = request_firmware(&fw, fw_name_var(dev, ROM_PATCH),
dev->mt76.dev);
if (ret)
goto out;
@ -2096,11 +2120,10 @@ static int mt7915_load_ram(struct mt7915_dev *dev)
{
const struct mt7915_fw_trailer *hdr;
const struct firmware *fw;
const char *mcu;
int ret;
mcu = is_mt7915(&dev->mt76) ? MT7915_FIRMWARE_WM : MT7916_FIRMWARE_WM;
ret = request_firmware(&fw, mcu, dev->mt76.dev);
ret = request_firmware(&fw, fw_name_var(dev, FIRMWARE_WM),
dev->mt76.dev);
if (ret)
return ret;
@ -2124,8 +2147,8 @@ static int mt7915_load_ram(struct mt7915_dev *dev)
release_firmware(fw);
mcu = is_mt7915(&dev->mt76) ? MT7915_FIRMWARE_WA : MT7916_FIRMWARE_WA;
ret = request_firmware(&fw, mcu, dev->mt76.dev);
ret = request_firmware(&fw, fw_name(dev, FIRMWARE_WA),
dev->mt76.dev);
if (ret)
return ret;
@ -2777,10 +2800,8 @@ int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd)
req.tx_streams_num = fls(phy->mt76->test.tx_antenna_mask);
req.rx_streams = phy->mt76->test.tx_antenna_mask;
if (ext_phy) {
req.tx_streams_num = 2;
req.rx_streams >>= 2;
}
if (ext_phy)
req.rx_streams >>= dev->chainshift;
}
#endif

128
drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
Просмотреть файл

@ -17,6 +17,11 @@ static const u32 mt7915_reg[] = {
[INT1_MASK_CSR] = 0xd708c,
[INT_MCU_CMD_SOURCE] = 0xd51f0,
[INT_MCU_CMD_EVENT] = 0x3108,
[WFDMA0_ADDR] = 0xd4000,
[WFDMA0_PCIE1_ADDR] = 0xd8000,
[WFDMA_EXT_CSR_ADDR] = 0xd7000,
[CBTOP1_PHY_END] = 0x77ffffff,
[INFRA_MCU_ADDR_END] = 0x7c3fffff,
};
static const u32 mt7916_reg[] = {
@ -26,6 +31,25 @@ static const u32 mt7916_reg[] = {
[INT1_MASK_CSR] = 0xd8204,
[INT_MCU_CMD_SOURCE] = 0xd41f0,
[INT_MCU_CMD_EVENT] = 0x2108,
[WFDMA0_ADDR] = 0xd4000,
[WFDMA0_PCIE1_ADDR] = 0xd8000,
[WFDMA_EXT_CSR_ADDR] = 0xd7000,
[CBTOP1_PHY_END] = 0x7fffffff,
[INFRA_MCU_ADDR_END] = 0x7c085fff,
};
static const u32 mt7986_reg[] = {
[INT_SOURCE_CSR] = 0x24200,
[INT_MASK_CSR] = 0x24204,
[INT1_SOURCE_CSR] = 0x28200,
[INT1_MASK_CSR] = 0x28204,
[INT_MCU_CMD_SOURCE] = 0x241f0,
[INT_MCU_CMD_EVENT] = 0x54000108,
[WFDMA0_ADDR] = 0x24000,
[WFDMA0_PCIE1_ADDR] = 0x28000,
[WFDMA_EXT_CSR_ADDR] = 0x27000,
[CBTOP1_PHY_END] = 0x7fffffff,
[INFRA_MCU_ADDR_END] = 0x7c085fff,
};
static const u32 mt7915_offs[] = {
@ -264,11 +288,68 @@ static const struct __map mt7916_reg_map[] = {
{ 0x0, 0x0, 0x0 }, /* imply end of search */
};
static const struct __map mt7986_reg_map[] = {
{ 0x54000000, 0x402000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
{ 0x55000000, 0x403000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
{ 0x56000000, 0x404000, 0x1000 }, /* WFDMA_2 (Reserved) */
{ 0x57000000, 0x405000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
{ 0x58000000, 0x406000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
{ 0x59000000, 0x407000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
{ 0x820c0000, 0x408000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
{ 0x820c8000, 0x40c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
{ 0x820cc000, 0x40e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
{ 0x820e0000, 0x420000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
{ 0x820e1000, 0x420400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
{ 0x820e2000, 0x420800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
{ 0x820e3000, 0x420c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
{ 0x820e4000, 0x421000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
{ 0x820e5000, 0x421400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
{ 0x820ce000, 0x421c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
{ 0x820e7000, 0x421e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
{ 0x820cf000, 0x422000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
{ 0x820e9000, 0x423400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
{ 0x820ea000, 0x424000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
{ 0x820eb000, 0x424200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
{ 0x820ec000, 0x424600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
{ 0x820ed000, 0x424800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
{ 0x820ca000, 0x426000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
{ 0x820d0000, 0x430000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
{ 0x00400000, 0x480000, 0x10000}, /* WF_MCU_SYSRAM */
{ 0x00410000, 0x490000, 0x10000}, /* WF_MCU_SYSRAM */
{ 0x820f0000, 0x4a0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
{ 0x820f1000, 0x4a0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
{ 0x820f2000, 0x4a0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
{ 0x820f3000, 0x4a0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
{ 0x820f4000, 0x4a1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
{ 0x820f5000, 0x4a1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
{ 0x820f7000, 0x4a1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
{ 0x820f9000, 0x4a3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
{ 0x820fa000, 0x4a4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
{ 0x820fb000, 0x4a4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
{ 0x820fc000, 0x4a4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
{ 0x820fd000, 0x4a4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
{ 0x820c4000, 0x4a8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
{ 0x820b0000, 0x4ae000, 0x1000 }, /* [APB2] WFSYS_ON */
{ 0x80020000, 0x4b0000, 0x10000}, /* WF_TOP_MISC_OFF */
{ 0x81020000, 0x4c0000, 0x10000}, /* WF_TOP_MISC_ON */
{ 0x89000000, 0x4d0000, 0x1000 }, /* WF_MCU_CFG_ON */
{ 0x89010000, 0x4d1000, 0x1000 }, /* WF_MCU_CIRQ */
{ 0x89020000, 0x4d2000, 0x1000 }, /* WF_MCU_GPT */
{ 0x89030000, 0x4d3000, 0x1000 }, /* WF_MCU_WDT */
{ 0x80010000, 0x4d4000, 0x1000 }, /* WF_AXIDMA */
{ 0x0, 0x0, 0x0 }, /* imply end of search */
};
static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
{
u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
u32 l1_remap = is_mt7915(&dev->mt76) ?
u32 l1_remap;
if (is_mt7986(&dev->mt76))
return MT_CONN_INFRA_OFFSET(addr);
l1_remap = is_mt7915(&dev->mt76) ?
MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
dev->bus_ops->rmw(&dev->mt76, l1_remap,
@ -295,17 +376,19 @@ static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
/* use read to push write */
dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
} else {
u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0;
offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916,
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
MT_HIF_REMAP_L2_MASK_MT7916,
FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
/* use read to push write */
dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916);
dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
offset += MT_HIF_REMAP_BASE_L2_MT7916;
offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
}
return offset;
@ -338,11 +421,20 @@ static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
(addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
(addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END) ||
(addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
(addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))
(addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
return mt7915_reg_map_l1(dev, addr);
if (dev_is_pci(dev->mt76.dev) &&
((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
(addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END)))
return mt7915_reg_map_l1(dev, addr);
/* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
return mt7915_reg_map_l1(dev, addr);
}
return mt7915_reg_map_l2(dev, addr);
}
@ -393,6 +485,12 @@ static int mt7915_mmio_init(struct mt76_dev *mdev,
dev->reg.map = mt7916_reg_map;
dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
break;
case 0x7986:
dev->reg.reg_rev = mt7986_reg;
dev->reg.offs_rev = mt7916_offs;
dev->reg.map = mt7986_reg_map;
dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
break;
default:
return -EINVAL;
}
@ -585,6 +683,19 @@ static int __init mt7915_init(void)
ret = pci_register_driver(&mt7915_pci_driver);
if (ret)
goto error_pci;
if (IS_ENABLED(CONFIG_MT7986_WMAC)) {
ret = platform_driver_register(&mt7986_wmac_driver);
if (ret)
goto error_wmac;
}
return 0;
error_wmac:
pci_unregister_driver(&mt7915_pci_driver);
error_pci:
pci_unregister_driver(&mt7915_hif_driver);
return ret;
@ -592,6 +703,9 @@ static int __init mt7915_init(void)
static void __exit mt7915_exit(void)
{
if (IS_ENABLED(CONFIG_MT7986_WMAC))
platform_driver_unregister(&mt7986_wmac_driver);
pci_unregister_driver(&mt7915_pci_driver);
pci_unregister_driver(&mt7915_hif_driver);
}

40
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
Просмотреть файл

@ -35,9 +35,20 @@
#define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin"
#define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin"
#define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin"
#define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin"
#define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin"
#define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin"
#define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin"
#define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin"
#define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin"
#define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin"
#define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin"
#define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin"
#define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin"
#define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin"
#define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin"
#define MT7915_EEPROM_SIZE 3584
#define MT7916_EEPROM_SIZE 4096
@ -273,6 +284,7 @@ struct mt7915_dev {
struct mt7915_phy *rdd2_phy;
u16 chainmask;
u16 chainshift;
u32 hif_idx;
struct work_struct init_work;
@ -305,6 +317,10 @@ struct mt7915_dev {
u8 table_mask;
u8 n_agrt;
} twt;
struct reset_control *rstc;
void __iomem *dcm;
void __iomem *sku;
};
enum {
@ -377,11 +393,35 @@ mt7915_ext_phy(struct mt7915_dev *dev)
return phy->priv;
}
static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku)
{
u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK;
if (!is_mt7986(&dev->mt76))
return 0;
return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask;
}
extern const struct ieee80211_ops mt7915_ops;
extern const struct mt76_testmode_ops mt7915_testmode_ops;
extern struct pci_driver mt7915_pci_driver;
extern struct pci_driver mt7915_hif_driver;
extern struct platform_driver mt7986_wmac_driver;
#ifdef CONFIG_MT7986_WMAC
int mt7986_wmac_enable(struct mt7915_dev *dev);
void mt7986_wmac_disable(struct mt7915_dev *dev);
#else
static inline int mt7986_wmac_enable(struct mt7915_dev *dev)
{
return 0;
}
static inline void mt7986_wmac_disable(struct mt7915_dev *dev)
{
}
#endif
struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
void __iomem *mem_base, u32 device_id);
irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);

278
drivers/net/wireless/mediatek/mt76/mt7915/regs.h
Просмотреть файл

@ -25,6 +25,11 @@ enum reg_rev {
INT1_MASK_CSR,
INT_MCU_CMD_SOURCE,
INT_MCU_CMD_EVENT,
WFDMA0_ADDR,
WFDMA0_PCIE1_ADDR,
WFDMA_EXT_CSR_ADDR,
CBTOP1_PHY_END,
INFRA_MCU_ADDR_END,
__MT_REG_MAX,
};
@ -497,7 +502,7 @@ enum offs_rev {
#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
/* WFDMA0 */
#define MT_WFDMA0_BASE 0xd4000
#define MT_WFDMA0_BASE __REG(WFDMA0_ADDR)
#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
#define MT_WFDMA0_RST MT_WFDMA0(0x100)
@ -545,7 +550,7 @@ enum offs_rev {
#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
/* WFDMA CSR */
#define MT_WFDMA_EXT_CSR_BASE 0xd7000
#define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR)
#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
@ -559,7 +564,7 @@ enum offs_rev {
#define MT_PCIE_RECOG_ID_SEM BIT(31)
/* WFDMA0 PCIE1 */
#define MT_WFDMA0_PCIE1_BASE 0xd8000
#define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR)
#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
@ -662,6 +667,16 @@ enum offs_rev {
#define MT_TOP_PWR_HW_CTRL BIT(4)
#define MT_TOP_PWR_PWR_ON BIT(7)
#define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050)
#define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054)
#define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010)
#define MT_TOP_PWR_EN_MASK BIT(7)
#define MT_TOP_PWR_ACK_MASK BIT(6)
#define MT_TOP_PWR_KEY_MASK GENMASK(31, 16)
#define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120)
#define MT7986_TOP_WM_RESET_MASK BIT(0)
/* l1/l2 remap */
#define MT_HIF_REMAP_L1 0xf11ac
#define MT_HIF_REMAP_L1_MT7916 0xfe260
@ -685,9 +700,203 @@ enum offs_rev {
#define MT_WFSYS1_PHY_START 0x18800000
#define MT_WFSYS1_PHY_END 0x18bfffff
#define MT_CBTOP1_PHY_START 0x70000000
#define MT_CBTOP1_PHY_END 0x7fffffff
#define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END)
#define MT_CBTOP2_PHY_START 0xf0000000
#define MT_CBTOP2_PHY_END 0xffffffff
#define MT_INFRA_MCU_START 0x7c000000
#define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END)
#define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE)
/* CONN INFRA CFG */
#define MT_CONN_INFRA_BASE 0x18001000
#define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs))
#define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020)
#define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030)
#define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0)
#define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2)
#define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380)
#define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300)
#define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7)
#define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0)
#define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200)
#define MT_CONN_INFRA_HW_CTRL_MASK BIT(0)
#define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540)
#define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0)
#define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544)
#define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31))
#define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31))
#define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414)
#define MT_CONN_INFRA_EMI_REQ_MASK BIT(0)
#define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5)
/* AFE */
#define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19))
#define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs))
#define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00)
#define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04)
#define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08)
#define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c)
#define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4)
#define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))
#define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
FIELD_PREP(GENMASK(14, 0), 0x7e4))
#define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6)
#define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0)
#define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2)
#define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16)
#define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \
MT_AFE_WPLL_CFG_MASK | \
MT_AFE_MCU_WPLL_CFG_MASK | \
MT_AFE_MCU_BPLL_CFG_MASK)
#define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \
FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \
FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \
FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2))
#define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15)
#define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9)
#define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0)
#define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21)
#define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20)
#define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \
MT_AFE_RG_WBG_EN_WPLL_UP_MASK)
#define MT_AFE_RG_WBG_EN_TXCAL_MASK GENMASK(21, 17)
#define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19))
#define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs))
#define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120)
/* ADIE */
#define MT_ADIE_CHIP_ID 0x02c
#define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16)
#define MT_ADIE_IDX0 GENMASK(15, 0)
#define MT_ADIE_IDX1 GENMASK(31, 16)
#define MT_ADIE_RG_TOP_THADC_BG 0x034
#define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12)
#define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3)
#define MT_ADIE_RG_TOP_THADC 0x038
#define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23)
#define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0)
#define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26)
#define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5)
#define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070
#define MT_ADIE_EFUSE_RDATA0 0x130
#define MT_ADIE_EFUSE2_CTRL 0x148
#define MT_ADIE_EFUSE_CTRL_MASK BIT(1)
#define MT_ADIE_EFUSE_CFG 0x144
#define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6)
#define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16)
#define MT_ADIE_EFUSE_VALID_MASK BIT(29)
#define MT_ADIE_EFUSE_KICK_MASK BIT(30)
#define MT_ADIE_THADC_ANALOG 0x3a6
#define MT_ADIE_THADC_SLOP 0x3a7
#define MT_ADIE_ANA_EN_MASK BIT(7)
#define MT_ADIE_7975_XTAL_CAL 0x3a1
#define MT_ADIE_TRIM_MASK GENMASK(6, 0)
#define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0)
#define MT_ADIE_XO_TRIM_EN_MASK BIT(7)
#define MT_ADIE_XTAL_DECREASE_MASK BIT(6)
#define MT_ADIE_7975_XO_TRIM2 0x3a2
#define MT_ADIE_7975_XO_TRIM3 0x3a3
#define MT_ADIE_7975_XO_TRIM4 0x3a4
#define MT_ADIE_7975_XTAL_EN 0x3a5
#define MT_ADIE_XO_TRIM_FLOW 0x3ac
#define MT_ADIE_XTAL_AXM_80M_OSC 0x390
#define MT_ADIE_XTAL_AXM_40M_OSC 0x391
#define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398
#define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399
#define MT_ADIE_WRI_CK_SEL 0x4ac
#define MT_ADIE_RG_STRAP_PIN_IN 0x4fc
#define MT_ADIE_XTAL_C1 0x654
#define MT_ADIE_XTAL_C2 0x658
#define MT_ADIE_RG_XO_01 0x65c
#define MT_ADIE_RG_XO_03 0x664
#define MT_ADIE_CLK_EN 0xa00
#define MT_ADIE_7975_XTAL 0xa18
#define MT_ADIE_7975_XTAL_EN_MASK BIT(29)
#define MT_ADIE_7975_COCLK 0xa1c
#define MT_ADIE_7975_XO_2 0xa84
#define MT_ADIE_7975_XO_2_FIX_EN BIT(31)
#define MT_ADIE_7975_XO_CTRL2 0xa94
#define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20)
#define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12)
#define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \
MT_ADIE_7975_XO_CTRL2_C2_MASK)
#define MT_ADIE_7975_XO_CTRL6 0xaa4
#define MT_ADIE_7975_XO_CTRL6_MASK BIT(16)
/* TOP SPI */
#define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19))
#define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs))
#define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0)
#define MT_TOP_SPI_POLLING_BIT BIT(5)
#define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50)
#define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15))
#define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15))
#define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54)
#define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58)
/* CONN INFRA CKGEN */
#define MT_INFRA_CKGEN_BASE 0x18009000
#define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs))
#define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00)
#define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23)
#define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29)
#define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008)
#define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c)
#define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040)
#define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2)
#define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0)
/* CONN INFRA BUS */
#define MT_INFRA_BUS_BASE 0x1800e000
#define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs))
#define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300)
#define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7)
#define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0)
#define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c)
#define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360)
#define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364)
/* CONN_INFRA_SKU */
#define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000
#define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)
#define MT_ADIE_TYPE_MASK BIT(1)
/* FW MODE SYNC */
#define MT_SWDEF_MODE 0x41f23c
@ -746,6 +955,67 @@ enum offs_rev {
#define MT_HW_REV 0x70010204
#define MT_WF_SUBSYS_RST 0x70002600
#define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4)
#define MT_TOP_WFSYS_WAKEUP_MASK BIT(0)
#define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4)
#define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0)
#define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0)
#define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0)
#define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc)
#define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30)
/* SEMA */
#define MT_SEMA_BASE 0x18070000
#define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs))
#define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4))
#define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4))
#define MT_SEMA_RFSPI_STATUS_MASK BIT(1)
/* MCU BUS */
#define MT_MCU_BUS_BASE 0x18400000
#define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs))
#define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440)
#define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0)
#define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28)
#define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31)
#define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120)
/* TOP CFG */
#define MT_TOP_CFG_BASE 0x184b0000
#define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs))
#define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010)
/* TOP CFG ON */
#define MT_TOP_CFG_ON_BASE 0x184c1000
#define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs))
#define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604)
/* SLP CTRL */
#define MT_SLP_BASE 0x184c3000
#define MT_SLP(ofs) (MT_SLP_BASE + (ofs))
#define MT_SLP_STATUS MT_SLP(0x00c)
#define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23))
#define MT_SLP_CTRL_EN_MASK BIT(0)
#define MT_SLP_CTRL_BSY_MASK BIT(1)
/* MCU BUS DBG */
#define MT_MCU_BUS_DBG_BASE 0x18500000
#define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs))
#define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0)
#define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)
#define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
#define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2)
/* PCIE MAC */
#define MT_PCIE_MAC_BASE 0x74030000
#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))

1210
drivers/net/wireless/mediatek/mt76/mt7915/soc.c Normal file
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Разница между файлами не показана из-за своего большого размера Загрузить разницу

2
drivers/net/wireless/mediatek/mt76/mt7915/testmode.c
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@ -456,7 +456,7 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
u8 tx_ant = td->tx_antenna_mask;
if (phy != &dev->phy)
tx_ant >>= 2;
tx_ant >>= dev->chainshift;
phy->test.spe_idx = spe_idx_map[tx_ant];
}
}

5
drivers/net/wireless/mediatek/mt76/testmode.c
Просмотреть файл

@ -409,7 +409,6 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct mt76_dev *dev = phy->dev;
struct mt76_testmode_data *td = &phy->test;
struct nlattr *tb[NUM_MT76_TM_ATTRS];
bool ext_phy = phy != &dev->phy;
u32 state;
int err;
int i;
@ -447,8 +446,8 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_LDPC], &td->tx_rate_ldpc, 0, 1) ||
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_STBC], &td->tx_rate_stbc, 0, 1) ||
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_LTF], &td->tx_ltf, 0, 2) ||
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA], &td->tx_antenna_mask,
1 << (ext_phy * 2), phy->antenna_mask << (ext_phy * 2)) ||
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA],
&td->tx_antenna_mask, 0, 0xff) ||
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_SPE_IDX], &td->tx_spe_idx, 0, 27) ||
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE],
&td->tx_duty_cycle, 0, 99) ||