x86/mm/pat: Don't report PAT on CPUs that don't support it
The pat_enabled() logic is broken on CPUs which do not support PAT and
where the initialization code fails to call pat_init(). Due to that the
enabled flag stays true and pat_enabled() returns true wrongfully.
As a consequence the mappings, e.g. for Xorg, are set up with the wrong
caching mode and the required MTRR setups are omitted.
To cure this the following changes are required:
1) Make pat_enabled() return true only if PAT initialization was
invoked and successful.
2) Invoke init_cache_modes() unconditionally in setup_arch() and
remove the extra callsites in pat_disable() and the pat disabled
code path in pat_init().
Also rename __pat_enabled to pat_disabled to reflect the real purpose of
this variable.
Fixes: 9cd25aac1f
("x86/mm/pat: Emulate PAT when it is disabled")
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bernhard Held <berny156@gmx.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: "Luis R. Rodriguez" <mcgrof@suse.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/alpine.LRH.2.02.1707041749300.3456@file01.intranet.prod.int.rdu2.redhat.com
This commit is contained in:
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@ -7,6 +7,7 @@
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bool pat_enabled(void);
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void pat_disable(const char *reason);
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extern void pat_init(void);
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extern void init_cache_modes(void);
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extern int reserve_memtype(u64 start, u64 end,
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enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm);
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@ -1075,6 +1075,13 @@ void __init setup_arch(char **cmdline_p)
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max_possible_pfn = max_pfn;
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/*
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* This call is required when the CPU does not support PAT. If
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* mtrr_bp_init() invoked it already via pat_init() the call has no
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* effect.
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*/
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init_cache_modes();
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/*
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* Define random base addresses for memory sections after max_pfn is
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* defined and before each memory section base is used.
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@ -37,14 +37,14 @@
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#undef pr_fmt
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#define pr_fmt(fmt) "" fmt
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static bool boot_cpu_done;
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static int __read_mostly __pat_enabled = IS_ENABLED(CONFIG_X86_PAT);
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static void init_cache_modes(void);
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static bool __read_mostly boot_cpu_done;
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static bool __read_mostly pat_disabled = !IS_ENABLED(CONFIG_X86_PAT);
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static bool __read_mostly pat_initialized;
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static bool __read_mostly init_cm_done;
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void pat_disable(const char *reason)
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{
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if (!__pat_enabled)
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if (pat_disabled)
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return;
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if (boot_cpu_done) {
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@ -52,10 +52,8 @@ void pat_disable(const char *reason)
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return;
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}
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__pat_enabled = 0;
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pat_disabled = true;
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pr_info("x86/PAT: %s\n", reason);
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init_cache_modes();
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}
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static int __init nopat(char *str)
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@ -67,7 +65,7 @@ early_param("nopat", nopat);
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bool pat_enabled(void)
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{
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return !!__pat_enabled;
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return pat_initialized;
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}
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EXPORT_SYMBOL_GPL(pat_enabled);
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@ -205,6 +203,8 @@ static void __init_cache_modes(u64 pat)
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update_cache_mode_entry(i, cache);
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}
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pr_info("x86/PAT: Configuration [0-7]: %s\n", pat_msg);
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init_cm_done = true;
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}
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#define PAT(x, y) ((u64)PAT_ ## y << ((x)*8))
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@ -225,6 +225,7 @@ static void pat_bsp_init(u64 pat)
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}
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wrmsrl(MSR_IA32_CR_PAT, pat);
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pat_initialized = true;
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__init_cache_modes(pat);
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}
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@ -242,10 +243,9 @@ static void pat_ap_init(u64 pat)
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wrmsrl(MSR_IA32_CR_PAT, pat);
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}
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static void init_cache_modes(void)
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void init_cache_modes(void)
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{
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u64 pat = 0;
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static int init_cm_done;
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if (init_cm_done)
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return;
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@ -287,8 +287,6 @@ static void init_cache_modes(void)
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}
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__init_cache_modes(pat);
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init_cm_done = 1;
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}
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/**
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@ -306,10 +304,8 @@ void pat_init(void)
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u64 pat;
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (!pat_enabled()) {
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init_cache_modes();
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if (pat_disabled)
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return;
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}
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if ((c->x86_vendor == X86_VENDOR_INTEL) &&
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(((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
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