clk: qcom: Support display RCG clocks
Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Stephen Boyd
Mike Turquette
Родитель
9d011f3b71
Коммит
99cbd064b0
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@ -155,5 +155,8 @@ struct clk_rcg2 {
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#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_edp_pixel_ops;
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extern const struct clk_ops clk_byte_ops;
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extern const struct clk_ops clk_pixel_ops;
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#endif
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@ -19,6 +19,7 @@
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/math64.h>
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#include <asm/div64.h>
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@ -225,31 +226,25 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
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return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
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static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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const struct freq_tbl *f;
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u32 cfg, mask;
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int ret;
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f = find_freq(rcg->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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if (rcg->mnd_width && f->n) {
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mask = BIT(rcg->mnd_width) - 1;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
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mask, f->m);
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + M_REG, mask, f->m);
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if (ret)
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return ret;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
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mask, ~(f->n - f->m));
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
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if (ret)
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return ret;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
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mask, ~f->n);
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + D_REG, mask, ~f->n);
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if (ret)
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return ret;
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}
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@ -260,14 +255,26 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
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cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
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if (rcg->mnd_width && f->n)
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cfg |= CFG_MODE_DUAL_EDGE;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
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cfg);
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + CFG_REG, mask, cfg);
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if (ret)
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return ret;
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return update_config(rcg);
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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const struct freq_tbl *f;
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f = find_freq(rcg->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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return clk_rcg2_configure(rcg, f);
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}
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static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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@ -290,3 +297,265 @@ const struct clk_ops clk_rcg2_ops = {
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.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_ops);
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struct frac_entry {
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int num;
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int den;
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};
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static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
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{ 52, 295 }, /* 119 M */
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{ 11, 57 }, /* 130.25 M */
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{ 63, 307 }, /* 138.50 M */
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{ 11, 50 }, /* 148.50 M */
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{ 47, 206 }, /* 154 M */
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{ 31, 100 }, /* 205.25 M */
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{ 107, 269 }, /* 268.50 M */
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{ },
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};
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static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
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{ 31, 211 }, /* 119 M */
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{ 32, 199 }, /* 130.25 M */
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{ 63, 307 }, /* 138.50 M */
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{ 11, 60 }, /* 148.50 M */
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{ 50, 263 }, /* 154 M */
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{ 31, 120 }, /* 205.25 M */
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{ 119, 359 }, /* 268.50 M */
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{ },
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};
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static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct freq_tbl f = *rcg->freq_tbl;
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const struct frac_entry *frac;
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int delta = 100000;
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s64 src_rate = parent_rate;
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s64 request;
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u32 mask = BIT(rcg->hid_width) - 1;
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u32 hid_div;
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if (src_rate == 810000000)
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frac = frac_table_810m;
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else
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frac = frac_table_675m;
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for (; frac->num; frac++) {
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request = rate;
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request *= frac->den;
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request = div_s64(request, frac->num);
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if ((src_rate < (request - delta)) ||
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(src_rate > (request + delta)))
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continue;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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&hid_div);
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f.pre_div = hid_div;
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f.pre_div >>= CFG_SRC_DIV_SHIFT;
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f.pre_div &= mask;
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f.m = frac->num;
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f.n = frac->den;
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return clk_rcg2_configure(rcg, &f);
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}
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return -EINVAL;
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}
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static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate, u8 index)
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{
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/* Parent index is set statically in frequency table */
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return clk_edp_pixel_set_rate(hw, rate, parent_rate);
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}
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static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *p_rate, struct clk **p)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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const struct freq_tbl *f = rcg->freq_tbl;
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const struct frac_entry *frac;
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int delta = 100000;
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s64 src_rate = *p_rate;
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s64 request;
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u32 mask = BIT(rcg->hid_width) - 1;
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u32 hid_div;
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/* Force the correct parent */
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*p = clk_get_parent_by_index(hw->clk, f->src);
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if (src_rate == 810000000)
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frac = frac_table_810m;
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else
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frac = frac_table_675m;
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for (; frac->num; frac++) {
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request = rate;
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request *= frac->den;
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request = div_s64(request, frac->num);
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if ((src_rate < (request - delta)) ||
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(src_rate > (request + delta)))
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continue;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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&hid_div);
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hid_div >>= CFG_SRC_DIV_SHIFT;
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hid_div &= mask;
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return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
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hid_div);
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}
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return -EINVAL;
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}
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const struct clk_ops clk_edp_pixel_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.set_rate = clk_edp_pixel_set_rate,
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.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
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.determine_rate = clk_edp_pixel_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
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static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *p_rate, struct clk **p)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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const struct freq_tbl *f = rcg->freq_tbl;
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unsigned long parent_rate, div;
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u32 mask = BIT(rcg->hid_width) - 1;
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if (rate == 0)
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return -EINVAL;
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*p = clk_get_parent_by_index(hw->clk, f->src);
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*p_rate = parent_rate = __clk_round_rate(*p, rate);
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div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
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div = min_t(u32, div, mask);
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return calc_rate(parent_rate, 0, 0, 0, div);
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}
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static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct freq_tbl f = *rcg->freq_tbl;
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unsigned long div;
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u32 mask = BIT(rcg->hid_width) - 1;
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div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
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div = min_t(u32, div, mask);
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f.pre_div = div;
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return clk_rcg2_configure(rcg, &f);
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}
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static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate, u8 index)
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{
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/* Parent index is set statically in frequency table */
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return clk_byte_set_rate(hw, rate, parent_rate);
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}
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const struct clk_ops clk_byte_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.set_rate = clk_byte_set_rate,
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.set_rate_and_parent = clk_byte_set_rate_and_parent,
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.determine_rate = clk_byte_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_byte_ops);
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static const struct frac_entry frac_table_pixel[] = {
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{ 3, 8 },
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{ 2, 9 },
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{ 4, 9 },
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{ 1, 1 },
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{ }
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};
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static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *p_rate, struct clk **p)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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unsigned long request, src_rate;
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int delta = 100000;
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const struct freq_tbl *f = rcg->freq_tbl;
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const struct frac_entry *frac = frac_table_pixel;
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struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
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for (; frac->num; frac++) {
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request = (rate * frac->den) / frac->num;
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src_rate = __clk_round_rate(parent, request);
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if ((src_rate < (request - delta)) ||
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(src_rate > (request + delta)))
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continue;
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*p_rate = src_rate;
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return (src_rate * frac->num) / frac->den;
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}
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return -EINVAL;
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}
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static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct freq_tbl f = *rcg->freq_tbl;
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const struct frac_entry *frac = frac_table_pixel;
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unsigned long request, src_rate;
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int delta = 100000;
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u32 mask = BIT(rcg->hid_width) - 1;
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u32 hid_div;
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struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
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for (; frac->num; frac++) {
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request = (rate * frac->den) / frac->num;
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src_rate = __clk_round_rate(parent, request);
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if ((src_rate < (request - delta)) ||
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(src_rate > (request + delta)))
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continue;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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&hid_div);
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f.pre_div = hid_div;
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f.pre_div >>= CFG_SRC_DIV_SHIFT;
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f.pre_div &= mask;
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f.m = frac->num;
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f.n = frac->den;
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return clk_rcg2_configure(rcg, &f);
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}
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return -EINVAL;
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}
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static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate, u8 index)
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{
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/* Parent index is set statically in frequency table */
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return clk_pixel_set_rate(hw, rate, parent_rate);
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}
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const struct clk_ops clk_pixel_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.set_rate = clk_pixel_set_rate,
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.set_rate_and_parent = clk_pixel_set_rate_and_parent,
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.determine_rate = clk_pixel_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_pixel_ops);
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