ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and enet
Add missing pinctrl of usdhc and enet for imx6q-sabrelite board. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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52ccd49203
Коммит
99d5f0cc17
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@ -51,8 +51,13 @@
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gpios {
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pinctrl_gpio_hog: gpiohog {
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fsl,pins = <
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144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
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1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
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1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
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121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
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144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
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152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
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1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
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1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
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953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
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>;
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};
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@ -71,12 +76,16 @@
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};
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ethernet@02188000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_1>;
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phy-mode = "rgmii";
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phy-reset-gpios = <&gpio3 23 0>;
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status = "okay";
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};
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usdhc@02198000 { /* uSDHC3 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3_2>;
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cd-gpios = <&gpio7 0 0>;
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wp-gpios = <&gpio7 1 0>;
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vmmc-supply = <®_3p3v>;
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@ -84,6 +93,8 @@
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};
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usdhc@0219c000 { /* uSDHC4 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4_2>;
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cd-gpios = <&gpio2 6 0>;
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wp-gpios = <&gpio2 7 0>;
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vmmc-supply = <®_3p3v>;
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@ -532,6 +532,28 @@
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};
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};
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enet {
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pinctrl_enet_1: enetgrp-1 {
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fsl,pins = <
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695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
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756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
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24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
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30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
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34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
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39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
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44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
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56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
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702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
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74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
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52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
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61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
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66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
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70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
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48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
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>;
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};
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};
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gpmi-nand {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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@ -591,6 +613,17 @@
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1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
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>;
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};
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pinctrl_usdhc3_2: usdhc3grp-2 {
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fsl,pins = <
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1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
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1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
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1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
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1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
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1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
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1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
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>;
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};
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};
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usdhc4 {
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@ -608,6 +641,17 @@
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1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
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>;
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};
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pinctrl_usdhc4_2: usdhc4grp-2 {
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fsl,pins = <
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1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
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1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
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1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
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1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
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1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
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1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
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>;
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};
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};
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};
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